LADLD30G-SH2-R

UNISONIC TECHNOLOGIES CO., LTD Preliminary LADLD30 0.8V REFERENCE ULTRA LOW DROPOUT LINEAR REGULATOR DESCRIPTION The UTC LADLD30 is a typical LDO with the features of very low dropout voltage as low as 0.25V at output current 3A. For normal operation, tow supply voltages are necessary. One called control voltage from other equipment can shutdown the output voltage and it should pull and hold the voltage of EN pin less than 0.3V. Another one is the main supply voltage whose purpose is for main power conversion, to keep the power dissipation low, and to make the dropout voltage lower. Internally, in the UTC LADLD30, there’re many functions which can be seen in the block figure to prevent the IC from being damaged. Internal Power-On-Reset (POR) circuit can control the tow supply voltages to prevent fault operations of the circuit; the thermal shutdown circuit is able to protect the device from over thermal operation, and a current limit function will keep the device work safely under current over-loads. The UTC LADLD30 can be used as an ideal to provide well supply voltage in the applications, such as front-side-bus termination on motherboard, NB applications, front side bus VTT (1.2V/3A) and note book PC applications. CMOS IC HSOP-8 FEATURES * Low Dropout VD=0.25V(typ.)@ IOUT=3A * Low ESR Output Capacitor * VREF=0.8V * ±1.5% over Line, Load and Temperature Output Accuracy * Fast Transient Response * Output Voltage Adjustable through External Resistors * POR(Power-On-Reset) controlling VCNTL and VIN * With internal Soft-Start * Internal Current Limit Protection * Internal Under Voltage Protection * Hysteretic Thermal Shutdown * With Power-OK Output (with a Delay Time) * For Standby or Suspend Mode: Shutdown ORDERING INFORMATION Ordering Number Lead Free Halogen Free LADLD30L-SH2-R LADLD30G-SH2-R xx: Output Voltage, refer to Marking Information. Package HSOP-8 Packing Tape Reel www.unisonic.com.tw Copyright © 2010 Unisonic Technologies Co., Ltd 1 of 8 QW-R502-330.c LADLD30 MARKING INFORMATION Date Code UTC LADLD30 Preliminary CMOS IC L: Lead Free G: Halogen Free Lot Code PIN CONFIGURATION GND FB VOUT VOUT 1 2 VIN 3 4 8 7 6 5 EN POK VCNTL VIN PIN DESCRIPTION PIN NO. 1 PIN NAME GND DESCRIPTION Ground pin. There’s an external resistor divider connected to this pin which is necessary to give the feedback voltage to the regulator. The external circuit is combined as the follow: between VOUT and FB is R1(connected with a bypass capacitor which can improve the load transient response),and between FB and ground is R2.The value of R2 and R1 are recommended between 100Ω~10kΩ.So the output voltage is equals: R1 VOUT=0.8·(1+ )(V) R2 The output voltage pin of the regulator. There should be set an output capacitor to compensate for closed-loop and also to improve transient responses. It’s necessary to connect Pin 3 and Pin 4 together by wide tracks. This pin is the main supply input. It’s necessary to connect the Exposed Pad and VIN together for lower dropout voltage. Monitoring this pin’s voltage can reset Power-On. Power input pin of the control circuitry. Connecting this pin to a +5V (recommended) supply voltage provides the bias for the control circuitry. The voltage at this pin is monitored for Power-On Reset purpose. Output pin for Power-OK signal output. Being an open drain output, through senescing FB voltage, this pin can show the users the output voltage’s states. That’s this pin will be low under any of these tow situations: the rising FB voltage is not above the VPOK threshold; the falling FB voltage is below the VPNOK threshold. That indicates the output voltage is not ready for users. Input Enable control pin. The output voltage can be shut down when this pin is below 0.3V. This pin’s voltage can be set higher than VCNTL voltage by an internal 10μA current source, and then the regulator will begin working normally. 2 FB 3 4 5 VOUT VIN 6 VCNTL 7 POK 8 EN UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 8 QW-R502-330.c LADLD30 BLOCK DIAGRAM Preliminary CMOS IC EN VCNTL FB FB Power On Reset UV + 0.4V Soft-Start and Control Logic VIN Thermal Limit EAMP + VREF 0.8V + POK 90% VREF VOUT Current Limit Dealy POK GND UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 8 QW-R502-330.c LADLD30 ABSOLUTE MAXIMUM RATING Preliminary CMOS IC PARAMETER SYMBOL RATINGS UNIT Supply Voltage (VCNTL to GND) VCNTL -0.3 ~ +7 V Supply Voltage (VIN to GND) VIN -0.3 ~ +3.3 V EN and FB to GND VI/O -0.3 ~ VCNTL+0.3 V POK to GND VPOK -0.3 ~ +7 V Power Dissipation PD 3 W Junction Temperature TJ 150 °С Storage Temperature TSTG -65 ~ +150 °С Note: Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. THERMAL DATA PARAMETER SYMBOL RATINGS UNIT Junction to Ambient (Note 1) θJA 42 °C/W Junction to Case (Note 2) θJC 18 °C/W Note: 1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. The exposed pad of HSOP-8 is soldered directly on the PCB. 2. The Thermal Pad Temperature is measured on the PCB copper area connected to the thermal pad of package. OPERATING CONDITIONS PARAMETER Supply Voltage Control Supply Voltage Input VCNTL=3.3±5% Output Voltage VCNTL=5.0±5% Output Current Junction Temperature SYMBOL VCNTL VIN VOUT IOUT TJ RATINGS 3.1 ~ 6 1.1 ~ 3.3 0.8 ~ 1.2 +0.8 ~ VIN-0.2 0~4 -25 ~ +125 UNIT V V V V A °С ELECTRICAL CHARACTERISTICS (Refer to the typical application circuit. These specifications apply over, VCNTL = 5V, VIN = 1.5V, VOUT = 1.2V and Ta = 0 to 70°C, unless otherwise specified. Typical values refer to Ta = 25°C). PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT VCNTL Nominal Supply Current ICNTL EN = VCNTL 0.4 1 2 mA VCNTL Shutdown Current ISD EN = GND 180 380 µA 2.7 2.9 3.1 V VCNTL VCNTL Rising POR Threshold VTHR VIN 0.8 0.9 1.0 V VIN Rising VCNTL 0.4 V POR Hysteresis VHYS VIN 0.5 V Reference Voltage VREF FB =VOUT 0.8 V Output Voltage Accuracy IOUT=0A~3A, TJ= -25 ~125°С -1.5 +1.5 % ΔVOUT Line Regulation VCNTL=3.3~5V 0 0.13 %/V ΔVIN × VOUT ΔVOUT Load Regulation 0.06 0.15 % IOUT=0A~3A VOUT VCNTL=5V, TJ= 25°С 4.8 5.7 6.6 A VCNTL=5V, TJ= -25 ~ +125°С 4 A Current Limit ILIMIT VCNTL=3.3V, TJ= 25°С 4.6 5.5 6.4 A 3.8 A VCNTL=3.3V, TJ= -25 ~ +125°С VCNTL=5V, IOUT=3A, TJ= 25°С 0.17 0.25 V Dropout Voltage VD VCNTL=5V, IOUT=3A, TJ= -50~+125°С 0.3 V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 4 of 8 QW-R502-330.c LADLD30 Preliminary CMOS IC MIN TYP 150 50 0.4 0.3 0.4 30 10 2 90% 92% 79% 81% 0.25 1 3 MAX UNIT °С °С V 0.5 V mV μA ms 94% VREF 83% VREF 0.4 V 10 ms ELECTRICAL CHARACTERISTICS(Cont.) PARAMETER SYMBOL TEST CONDITIONS Over Temperature Shutdown OTS TJ Rising Over Temperature Hysteresis OTH Under-Voltage Threshold VFB Falling EN Logic High Threshold Voltage VEN Rising EN Hysteresis EN Pin Pull-Up Current EN=GND Soft-Start Interval TSS POK Threshold Voltage for Power OK VPOK VFB Rising POK Threshold Voltage for Power Not OK VPNOK VFB Falling POK Low Voltage POK sinks 5mA POK Delay Time TDELAY UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 8 QW-R502-330.c LADLD30 Preliminary CMOS IC TYPICAL APPLICATION CIRCUIT 1. Using an Output Capacitor with ESR≥18mΩ 2. Using an MLCC as the Output Capacitor R3=1kΩ VCNTL +5V CCNTL=1µF 6 VCNTL POK 7 POK VOUT 3 VOUT 4 R1=39kΩ EN Enable 8 EN GND 1 R2=78kΩ FB 2 C1=56pF COUT=22µF VOUT +1.2V/3A VIN 5 VIN +1.5V CIN=22µF VOUT (V) 1.05 1.5 1.8 R1 (kΩ) 43 27 15 R2 (kΩ) 137.6 30.86 12 C1 (pF) 47 82 150 UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 8 QW-R502-330.c LADLD30 APPLICATION INFORMATION Preliminary CMOS IC 1. Power Sequencing When there’s no main voltage applied at VIN, it is suggested not to apply a voltage to VOUT for a long time. Because the internal parasitic diode (between VOUT to VIN) will conduct and dissipate power, there’s no protection. 2. Output Capacitor A proper output capacitor to maintain stability and improve transient response over temperature and current is necessary. Proper ESR (equivalent series resistance) and capacitance of the output capacitor should be selected properly for stability of the normal operation and good load transient response. Many kinds of capacitors can be used as an output capacitor, such as ultra-low-ESR capacitors (like ceramic chip capacitors), low-ESR bulk capacitors (like solid Tantalum, POSCap, and Aluminum electrolytic capacitors). And also the value of the output capacitors’ can be increased without limit. In the applications with large stepping load current, the low-ESR bulk capacitors are normally recommended. Decoupling ceramic capacitors are recommended to be placed at the load and ground pins very closely and also the impedance of the layout must be minimized. 3. Input Capacitor In order to prevent the input rail from dropping, the proper input capacitor to supply current surge during stepping load transients is required. Because the limited slew rate of the surge currents, more parasitic inductance needs more input capacitance. Ultra-low-ESR capacitors (>100mF, ESR