UC2843BG-S08-R

UNISONIC TECHNOLOGIES CO., LTD UC2843B Preliminary LINEAR INTEGRATED CIRCUIT HIGH-PERFORMANCE CURRENT-MODE PWM CONTROLLERS DESCRIPTION The UTC UC2843B provides off-line or DC-DC fixed-frequency current-mode control design with minimum external components. Internally-implemented circuits include an under-voltage lockout (UVLO) and a precision reference with accuracy at the error amplifier input. The UTC UC2843B also contain internal circuits which include a pulse width modulation (PWM) comparator providing current-limit control, logic ensuring latched operation, and a totem-pole output stage designed to source or sink high-peak current. The output stage is low when it is in off-state condition and suitable for N-channel MOSFETs driving. The UTC UC2843B also has following advantages: the start-up current lower than 0.5mA while the oscillator discharge current is specified to 8.3mA (Typ.). In UVLO conditions, the output has a maximum saturation voltage of 1.2V when sinking 10mA@VCC = 5V. The typical UVLO threshold of the UTC UC2843B is 8.4V (on) and 7.6V (off) and can operate to duty cycles approximately 100%. FEATURES * * * * * * * * * Current mode operation:500 kHz Low start-up current value 5kΩ: f = 1.72 / RTCT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 9 QW-R103-048.a UC2843B Preliminary LINEAR INTEGRATED CIRCUIT APPLICATION INFORMATION(Cont.) Open-Loop Laboratory Test Fixture In the open-loop laboratory test fixture, high peak currents and loads need grounding techniques. The transistor and 5-kΩ potentiometer sample the oscillator waveform, applying an adjustable ramp to the ISENSE terminal. Timing and bypass capacitors should be connected closely to the GND terminal in a single-point ground. Shutdown Technique The PWM controller can be shut down through two methods: the one is raising voltage (above 1 V) at ISENSE, the other is pulling the COMP terminal below a voltage two diode drops above ground. Either method can leave the output of the PWM comparator high (refer to block diagram). To reset the PWM latch is dominant so the output can stay low in the case of the next clock cycle is coming and the COMP or ISENSE terminal is removed beyond this shutdown condition. For example, an externally-latched shutdown can be accomplished by adding an SCR reset by cycling VCC below the lower UVLO threshold. So the reference turns off then allows the SCR to reset at this condition. 1kΩ VREF Shutdown COMP 330Ω 500Ω ISENSE To Current-Sense Resistor UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 9 QW-R103-048.a UC2843B Shutdown Technique (cont.) Preliminary LINEAR INTEGRATED CIRCUIT APPLICATION INFORMATION(Cont.) A fraction of the triangular-wave oscillator can be summed resistively with the current-sense signal providing slope compensation for converters, which requiring duty cycles over 50%. Please note that capacitor C forms a filter with R2 to suppress the leading-edge switch spikes. VREF 0.1µF RT RT/CT CT R1 ISENSE C RSENSE R2 ISENSE UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 9 of 9 QW-R103-048.a