UC3843BL-D08-T

UNISONIC TECHNOLOGIES CO., LTD UC3842B/3843B HIGH PERFORMANCE CURRENT MODE CONTROLLERS DESCRIPTION The UTC UC3842B/3843B are specifically designed for off-line and dc-to-dc converter applications offering the designer a cost-effective solution with minimal external components. The UC3842B has UVLO thresholds 16V (on) and 10V(off), ideally suited for off-line converters. The UC3843B is tailored for lower voltage applications having UVLO thresholds of 8.4V(on) and 7.6V(off). LINEAR INTEGRATED CIRCUIT FEATURES * Trimmed oscillator for precise frequency control * Oscillator frequency guaranteed at 250kHz * Current mode operation to 500kHz * Automatic feed forward compensation * Latching PWM for cycle-by-cycle current limiting * Internally trimmed reference with undervoltage lockout * High current totem pole output * Undervoltage lockout with hysteresis * Low startup and operating current Lead-free: UC3842BL UC3843BL Halogen-free: UC3842BP UC3843BP ORDERING INFORMATION Normal UC3842B-D08-T UC3842B-S08-R UC3843B-D08-T UC3843B-S08-R Ordering Number Lead Free UC3842BL-D08-T UC3842BL-S08-R UC3843BL-D08-T UC3843BL-S08-R Halogen Free UC3842BP-D08-T UC3842BP-S08-R UC3843BP-D08-T UC3843BP-S08-R Package DIP-8 SOP-8 DIP-8 SOP-8 Packing Tube Tape Reel Tube Tape Reel www.unisonic.com.tw Copyright © 2008 Unisonic Technologies Co., Ltd 1 of 11 QW-R103-012.D UC3842B/3843B PIN CONFIGURATION LINEAR INTEGRATED CIRCUIT COMP 1 8 VREF VFB 2 7 VCC CS 3 6 OUTPUT RTCT 4 5 GND PIN DESCRIPTIONS PIN NO. 1 2 3 4 5 6 7 8 PIN NAME COMP VFB CS RTCT GND OUTPUT VCC VREF I/O O I I I O O DESCRIPTION Error amp output to provide loop compensation maintaing VFB at 2.5V Error amp inverting input, The non-inverting input of error amp is 2.5V band gap reference Current sense input to PWM control gate drive of output To set oscillator frequency and maximum output duty cycle Power ground To direct drive power MOSFET Power supply 5V regulated output provides charging current for CT through RT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 2 of 11 QW-R103-012.D UC3842B/3843B BLOCK DIAGRAM LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 3 of 11 QW-R103-012.D UC3842B/3843B ABSOLUTE MAXIMUM RATINGS(Ta=25°C) PARAMETER Total Power Supply and Zener Current Output Current, Source or Sink (note1) Output Energy (capacitive load per cycle) Current Sense and Voltage Feedback Inputs Error Amp. Output Sink Current LINEAR INTEGRATED CIRCUIT RATINGS 30 1.0 5.0 -0.3 ~ +5.5 10 DIP-8 1250 Power Dissipation PD SOP-8 702 Operating Junction Temperature TJ +150 Operating Temperature TOPR 0 ~ +70 Storage Temperature Range TSTG -65 ~ +150 Note Absolute maximum ratings are those values beyond which the device could be permanently damaged. Absolute maximum ratings are stress ratings only and functional device operation is not implied. SYMBOL (ICC + Iz) Io W VIN IO(SINK) UNIT mA A μJ V mA mW mW °C °C °C THERMAL DATA PARAMETER Thermal Resistance Junction to Ambient DIP-8 SOP-8 SYMBOL θJA RATINGS 100 178 UNIT °C/W °C/W ELECTRICAL CHARACTERISTICS (0°C ≤TA≤70°C, VCC=15V [note 2], RT=10k, CT=3.3nF, unless otherwise specified) PARAMETER SYMBOL TEST CONDITIONS REFERENCE SECTION Output Voltage VREF Io=1.0mA, TJ =25°C VCC=12V ~ 25V Line Regulation ΔVLINE Io=1.0mA ~ 20mA Load Regulation ΔVLOAD Temperature Stability Total Output Variation Output Noise Voltage Long Term Stability Output Short Circuit Current OSCILLATOR SECTION Frequency Frequency Change with Voltage Frequency Change with Temperature Oscillator Voltage Swing(Peak to Peak) Discharge Current ERROR AMPLIFIER SECTION Voltage Feedback Input Input Bias Current Open Loop Voltage Gain Unity Gain Bandwidth Power Supply Rejection Ratio Output Sink Current Output Source Current Output Voltage Swing High State TS VREF eN S ISC Line, Load, Temperature F=10kHz ~ 10Hz, TJ =25°C TA=125°C,1000Hrs -30 TJ =25°C Ta=0°C ~ 70°C TJ =25°C (RT=6.2k,CT=1.0nF) 12 ≤ VCC ≤25V 0°C ≤TA ≤70°C 49 48 225 MIN 4.9 TYP 5.0 2.0 3.0 0.2 50 5 -85 52 250 0.2 0.5 1.6 TJ =25°C 0°C ≤TA ≤70°C Vo=2.5V VFB=5.0V 2 ≤Vo≤4V TJ =25°C I2V≤Vcc≤25V Vo=1.1V,VFB =2.7V Vo=5.0V,VFB=2.3V VFB=2.3V, RL=15k to GND 7.8 7.6 2.42 65 0.7 60 2.0 -0.5 5.0 8.3 2.50 -0.1 90 1.0 70 12 -1.0 6.2 8.8 8.8 2.58 -2.0 MAX 5.1 20 25 5.18 UNIT V mV mV mV/°C V uV mV mA 4.82 -180 55 56 275 1.0 F ΔfOSC/ΔV ΔfOSC/ΔT VOSC Idischg VFB II(BIAS) GVO GBW PSRR ISINK ISOURCE VOH kHz % % V mA V μA dB MHz dB mA mA V UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 4 of 11 QW-R103-012.D UC3842B/3843B ELECTRICAL CHARACTERISTICS (Cont.) PARAMETER Output Voltage Swing Low State CURRENT SENSE SECTION Current Sense Input Voltage Gain Maximum Current Sense Input Threshold Power Supply Rejection Ratio Input Bias Current Propagation Delay OUTPUT SECTION Output Low Voltage Output High Voltage SYMBOL VOL GV VI(THR) PSRR II(BIAS) tD(IN/OUT) VOL VOH LINEAR INTEGRATED CIRCUIT TEST CONDITIONS VFB=2.7V, RL=15k to VREF (Note 3,4) (Note 3) 12≤Vcc≤25V (Note 3) Current Sense Input to Output ISINK=20mA ISINK=200mA ISOURCE=20mA ISOURCE=200mA VCC=6.0V,ISINK=1.0mA TJ =25°C,CL=1nF TJ =25°C,CL=1nF UTC UC3842B UTC UC3843B UTC UC3842B UTC UC3843B MIN TYP 0.8 3.0 1.0 70 -2 150 0.1 1.6 13.5 13.4 0.1 50 50 MAX 1.1 3.15 1.1 -10 300 0.4 2.2 UNIT V V/V V dB μA ns V V V V V ns ns V V V V % % mA mA V 2.85 0.9 13 12 Output Voltage with UVLO VOL (UVLO) Activated Output Voltage Rise Time tR Output Voltage Fall Time tF UNDER-VOLTAGE LOCKOUT SECTION Startup Threshold Min. Operating Voltage After Turn-on(Vcc) PWM SECTION MAX Duty Cycle MIN Total DEVICE Power Startup Supply Current VTHR VCC(MIN) 1.1 150 150 17.5 9 11.5 8.2 14.5 7.8 8.5 7.0 94 16 8.4 10 7.6 96 DC 0 0.3 30 12 36 0.5 17 VCC=6.5V for UC3843B VCC=14V for UC3842B Power Operating Supply Current ICC+IC Note2 Power Supply Zener Voltage VZ ICC=25mA Note: 1. Maximum Package power dissipation limits must be observed. 2. Adject VCC above the Startup threshold before setting to 15V. 3. This parameter is measured at the latch trip point with VFB=0V. ΔV Output Compensation 4. Comparator gain is defined as : GV ΔV Current Sense Input ICC+IC UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 5 of 11 QW-R103-012.D UC3842B/3843B TYPICAL APPLICATION CIRCUIT LINEAR INTEGRATED CIRCUIT Open Loop Test Circuit All of the parameters are not all tested in production, although been guaranteed. The timing and bypass capacitors must be connected to pin 5 in a single point ground very closely. To sample the oscillator waveform, the transistor and 5kΩ potentiometer are used, and also can apply an adjustable ramp to ISENSE pin. 2N 2222 UTC UC3842B/3843B 1 COMP 2 VFB 3 ISENSE 5K CT 4 RT/CT VREF 8 VC 7 OUTPUT 6 VREF RT 100K 4.7K E/A ADJUST 4.7K 1K ISENSE ADJUST A V1 OUTPUT 0.1 GND 5 0.1 1K/1W Under Voltage Lockout Under-Voltage Lock-Out: the output driver is biased to a high impedance state. To prevent activating the power switch with output leakage current, pin 6 should be shunted to ground with a bleeder resistor. Error Amp Configuration UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 6 of 11 QW-R103-012.D UC3842B/3843B APPLICATION INFORMATION(Cont.) Current Sense Circuit LINEAR INTEGRATED CIRCUIT Peak current (IS) is equaled: IS(MAX)=1.0V/RS There should be a small RC filter to suppress switch transients. Oscillator Waveforms and Maximum Duty Cycle VREF RT/RC 8 RT 4 CT LARGE RT SMALL CT V4 INTERINAL CLOCK SMALL CT LARGE RT GND 5 V4 INTERINAL CLOCK CT (Oscillator timing capacitor) can be charged by VREF through RT and discharged by an internal current source. At discharge time, the internal clock signal blanks the output to the low. Both oscillator frequency and maximum duty cycle can be determined by Selection of RT and CT. All charge and discharge times can be calculated by the next formulas: tC=0.55 RT CT ⎛ 0.0063R T − 2.7 ⎞ ⎟ tD=RTCTIn ⎜ ⎜ 0.0063R − 4 ⎟ T ⎝ ⎠ UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 7 of 11 QW-R103-012.D UC3842B/3843B APPLICATION INFORMATION(Cont.) Shutdown Techniques LINEAR INTEGRATED CIRCUIT The UTC UC3842B’s shutdown can be accomplished by two ways: raise pin 3 above 1V; or pull pin 1 below a voltage two diode drops above ground. Either method can cause the PWM comparator’s output to be high. Because the PWM latch is reset dominant, the output will remain low until the next clock cycle after the shutdown condition at pins 1 and/or 3 is removed. Slope Compensation UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 8 of 11 QW-R103-012.D UC3842B/3843B TYPICAL CHARACTERISTICS LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 20mV/DIV Maximum Output Duty Cycle, Dmax (%) Discharge Current, Idischg (mA) Percent Output Deadtime, %DT. Timing Resistor, RT (KΩ) 0 =2 CT F 0p nF .0 =5 CT F 0n =1 CT nF .0 =1 CT 9 of 11 QW-R103-012.D UC3842B/3843B TYPICAL CHARACTERISTICS(Cont.) LINEAR INTEGRATED CIRCUIT UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 10 of 11 QW-R103-012.D UC3842B/3843B TYPICAL CHARACTERISTICS(Cont.) LINEAR INTEGRATED CIRCUIT Output Saturation Voltage, Vsat (V) Output Voltage, Vo Supply Current, Icc Supply Current, Icc (mA) 20V/DIV UC3843B UTC assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all UTC products described or contained herein. UTC products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. UNISONIC TECHNOLOGIES CO., LTD www.unisonic.com.tw 100mA/DIV UC3842B 11 of 11 QW-R103-012.D