SI4567DY

SPICE Device Model Si4567DY Vishay Siliconix Dual N- and P-Channel 40-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74147 S-60243Rev. A, 20-Feb-06 www.vishay.com 1 SPICE Device Model Si4567DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA VDS = VGS, ID = −250 µA VDS = 5 V, VGS = 10 V VDS = −5 V, VGS = −10 V VGS = 10 V, ID = 4.1 A Drain-Source On-State Resistancea rDS(on) VGS = −10 V, ID = −3.6 A VGS = 4.5 V, ID = 3.8 A VGS = −4.5 V, ID = −2.9 A Forward Transconductancea gfs VDS = 15 V, ID = 4.1 A VDS = −15 V, ID = −3.6 A IS = 1.5 A, VGS = 0 V IS = −1.6 A, VGS = 0 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 1.4 1.9 97 67 0.049 0.056 0.056 0.097 9 6.3 0.72 0.80 0.048 0.058 0.056 0.097 15 7 0.80 −0.80 S Ω V Symbol Test Condition Simulated Data Measured Data Unit On-State Drain Currenta ID(on) A Diode Forward Voltagea VSD V Dynamicb Input Capacitance CISS N-Channel VDS = 20 V, VGS = 0 V, f = 1 MHz P-Channel VDS = − 20 V, VGS = 0 V, f = 1 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-CH VDS = 20 V, VGS = 10 V, ID = 5 A Total Gate Charge Qg VDS = − 20 V, VGS = −10 V, ID = − 5 A N-Ch P-Ch N-Ch N-Channel VDS = 20 V, VGS = 4.5 V, ID = 5 A P-Channel VDS = − 20 V, VGS = −4.5 V, ID = − 5 A P-Ch N-Ch P-Ch N-Ch P-Ch 471 567 53 76 25 57 6.5 10.5 3.3 5.7 1.1 1.5 1.4 2.7 355 480 50 80 29 56 8 12 3.7 6 1.1 1.5 1.4 2.7 nC pF Output Capacitance COSS Reverse Transfer Capacitance CRSS Gate-Source Charge Qgs Gate-Source Charge Qgs Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74147 S-60243Rev. A, 20-Feb-06 SPICE Device Model Si4567DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 74147 S-60243Rev. A, 20-Feb-06 www.vishay.com 3 SPICE Device Model Si4567DY Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 74147 S-60243Rev. A, 20-Feb-06