SI4910DY

SPICE Device Model Si4910DY Vishay Siliconix N-Channel 40-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74168 S-60411Rev. A, 20-Mar-06 www.vishay.com 1 SPICE Device Model Si4910DY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.2 224 0.021 0.026 17 0.83 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 6 A VGS = 4.5 V, ID = 4.8 A VDS = 15 V, ID = 6 A IS = 1.5 A V A 0.022 0.026 20 0.73 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Forward Voltagea Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 20 V, VGS = 10 V, ID = 5 A VDS = 20 V, VGS = 0 V, f = 1 MHz 1085 111 58 17 9 VDS = 20 V, VGS = 4.5 V, ID = 5 A 2.3 3.2 855 105 65 21 9.6 2.3 3.2 nC pF Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74168 S-60411Rev. A, 20-Mar-06 SPICE Device Model Si4910DY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74168 S-60411Rev. A, 20-Mar-06 www.vishay.com 3