SUD19P06-60L

SPICE Device Model SUD19P06-60L Vishay Siliconix P-Channel 60-V (D-S) 175°C MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73154 29-Sep-04 www.vishay.com 1 SPICE Device Model SUD19P06-60L Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 2 104 0.047 0.083 0.102 0.060 20 − 0.87 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −10 V VGS = −10 V, ID = −10 A V A 0.047 Ω 0.061 22 −1 S V Drain-Source On-State Resistance a rDS(on) VGS = −10 V, ID = −10 A, TJ = 125°C VGS = −10 V, ID = −10 A, TJ = 175°C VGS = −4.5 V, ID = −5 A Forward Transconductance Diode Forward Voltage a a gfs VSD VDS = −15 V, ID = −10 A IS = −10 A, VGS = 0 V Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge c c Ciss Coss Crss Qg Qgs Qgd VDS = −30 V, VGS = −10 V, ID = −10 A VGS = 0 V, VDS = −25 V, f = 1 MHz 1430 130 84 25 4.5 7 1140 130 90 26 4.5 7 nC pF Gate-Source Charge Gate-Drain Charge c Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature. www.vishay.com 2 Document Number: 73154 29-Sep-04 SPICE Device Model SUD19P06-60L Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73154 29-Sep-04 www.vishay.com 3