COG-VL248160-02

VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 2 OF 12 DOCUMENT REVISION HISTORY 1: DOCUMENT REVISION FROM TO A DATE 2008.11.19 DESCRIPTION First Release. (Based on LCD counter drawing: COG-DEMO1003 (Rev.0)) CHANGED BY PHILIP CHENG CHECKED BY TIM WONG VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 3 OF 12 CONTENTS Page No. 1. 2. 3. 4. 4.1 4.2 5. 5.1 5.2 5.3 5.4 6. 7. GENERAL DESCRIPTION MECHANICAL SPECIFICATIONS INTERFACE SIGNALS ABSOLUTE MAXIMUM RATINGS ELECTRICAL MAXIMUM RATINGS - FOR IC ONLY ENVIRONMENTAL CONDITION ELECTRICAL SPECIFICATIONS TYPICAL ELECTRICAL CHARACTERISTICS TIMING SPECIFICATIONS POWER-UP SEQUENCE POWER-DOWN SEQUENCE LCD COSMETIC CONDITIONS REMARK 4 4 7 8 8 8 9 9 10 11 11 12 12 VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 4 OF 12 VARITRONIX LIMITED Preliminary Specification of LCD Module Type Model No.: COG-VL248160-02 1. General Description • • • • • • • 248x160 dots, FSTN, black & white, positive, transflective, LCD graphic module. Viewing angle: 12 o’clock. Driving scheme: 1/160 duty, 1/12 bias. ‘ULTRA CHIP’ UC1698u (COG) LCD controller-driver. 8-bit parallel bus (8080). Logic voltage: +3V. White LED02 backlight. 2. Mechanical Specifications The mechanical detail is shown in Fig. 1 and summarized in Table 1 below. Table 1 Parameter Outline dimensions Viewing area Active area Display format Dot size Dot spacing Dot pitch Weight Specifications 63.0(W) x 66.7(H) x 8.3(D) 57.0(W) x 41.0(H) 53.31(W) x 35.19(H) 248(Horizontal) x 160(Vertical) 0.205(W) x 0.21(H) 0.01(W) x 0.01(H) 0.215(W) x 0.22(H) Approx. TBD Unit mm mm mm dots mm mm mm grams VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 5 OF 12 Figure 1: Outline Drawing. VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 6 OF 12 COG-VL248160-02 80 LCD GRAPHIC DISPLAY 248 x 160 DOTS 80 VSS VDD TST4 CS RST RS WR RD D7 ~ D0 8 'ULTRA CHIP' UC1698u (COG) LCD CONTROLLERDRIVER A K WHITE LED02 BACKLIGHT Figure 2: Block diagram 248 VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 7 OF 12 3. Interface signals Table 2 Symbol NC NC VSS VDD Description No connection. Ground. Power supply. Test control. This pin has on-chip pull-up resistor. Leave it open during normal operation. TST4 is also used as one of the high voltage power supply for MTP programming operation. For COG designs, please wire out TST4 with trace resistance between 30~50 Ω. No connection. ______ Pin No. 1 2 3 4 5 TST4 6 7 NC ______ CS CS (CS0). Chip Select. Chip is selected when CS = “L”. When the chip is not selected, D[7:0] will be high impedance. RST (RST). When RST =”L”, all control registers are re-initialized by their default states. Since UC1698u has built-in Power-ON reset and software reset commands, RST pin is not required for proper chip operation. ________ ________ ______ ________ 8 ________ RST An RC Filter has been included on-chip. There is no need for external RC 9 10 11 12 13 14 15 16 17 18 19 20 RS _______ noise filter. When RST is not used, connect the pin to VDD. RS(CD). Select Control data or Display data for read/write operation. ”L”: Control data ”H”: Display data ________ _______ _______ ________ WR RD RD ,WR (WR[1:0]) controls the read/write operation of the host interface. RD (WR1):read. ________ WR (WR0):write. ________ D7 D6 D5 D4 D3 D2 D1 D0 VSS A K Bi-directional bus for parallel host interface. Ground. Anode of LED backlight. Cathode of LED backlight. VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 8 OF 12 4. 4.1 Absolute Maximum Ratings Electrical Maximum Ratings - for IC Only Table 3 Parameter Symbol Min. Max. Unit Supply voltage VDD - VSS -0.3 +4.0 V VLCD -0.3 +19.8 V LCD driving voltage(-25°C to +75°C) Digital input voltage Vin -0.4 VDD+0.5 V Note: 1.) The modules may be destroyed if they are used beyond the absolute maximum ratings. 2.) VDD is based on VSS = 0V. 4.2 Environmental Condition Table 4 Operating temperature (Topr) Storage temperature Item (Tstg) Remark (Note 1) Min. Max. Min. Max. Ambient temperature Dry -10°C +70°C -40°C +80°C No 90% max. RH for Ta ≤ 40°C Humidity (Note 1) condensation < 50% RH for 40°C < Ta ≤ Maximum operating temperature Vibration (IEC 68-2-6) Frequency: 10 ∼ 55 Hz cells must be mounted 3 directions Amplitude: 0.75 mm on a suitable connector Duration: 20 cycles in each direction. Pulse duration: 11 ms Shock (IEC 68-2-27) 3 directions Peak acceleration: 981 m/s2 = 100g Half-sine pulse shape Number of shocks: 3 shocks in 3 mutually perpendicular axes. Note 1: Product cannot sustain at extreme storage conditions for long time. VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 9 OF 12 5. Electrical Specifications 5.1 Typical Electrical Characteristics At Ta = 25 °C, VDD=3V±5% , VSS=0V. Table 5 Parameter Symbol Conditions Min. Typ. Max. Unit Supply voltage VDD-VSS 2.85 3 3.15 V (Logic) Ta = -10 °C, TBD V VDD=3V, Note 1 LCD driving voltage Ta = +25°C, VLCD TBD V (built-in) VDD=3V, Note 1 Ta = +70°C, TBD V VDD=3V, Note 1 0.8 VDD Input logic HIGH VIH V 0.2VDD Input logic LOW VIL V Supply Current Character mode TBD mA IDD (Logic & LCD) Checker board mode TBD mA Supply voltage of Forward current VLED 5 V white LED02 backlight =TBDmA Number of LED chips Luminance(on the TBD cd/m2 =TBD backlight surface) Note 1 : There is tolerance in optimum LCD driving voltage during production and it will be within the specified range. VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 10 OF 12 5.2 Timing Specifications 5.2.1 Reset Characteristics At Ta = -10°C to +70°C, VDD=3V±5%, VSS = 0V Refer to Fig. 3, the reset characteristics. Table 6 Figure 3: Reset characteristics. 5.2.2 Parallel Bus Timing Characteristics (for 8080 MCU) At Ta = -10°C to +70°C , VDD=3V±5%, VSS = 0V Refer to Fig. 4, Parallel Bus Timing Characteristics (for 8080 MCU) Table 7 Figure 4: Parallel Bus Timing Characteristics (for 8080 MCU) VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 11 OF 12 5.3 Power-Up Sequence UC1698u power-up sequence is simplified by builtin “Power Ready” flags and the automatic invocation of System-Reset command after Power-ON-Reset. System programmers are only required to wait 150 ms before the CPU starting to issue commands to UC1698u. No additional time sequences are required between enabling the charge pump, turning on the display drivers, writing to RAM or any other commands. However, while turning on VDD, VDD2/3 should be started not later than VDD. Delay allowance between VDD and VDD2/3 is illustrated as Figure 7. Figure 5: Reference Power-Up Sequence 5.4 Power-Down Sequence To prevent the charge stored in capacitors CBX+, CBX–, and CL from damaging the LCD, when VDD is switched off, use Reset mode to enable the built-in draining circuit and discharge these capacitors. The draining resistor is 10KΩ for both VLCD and VB+. It is recommended to wait 3 x RC for VLCD and 1.5 x RC for VB+. For example, if CL is 0.1uF, then the draining time required for VLCD is ~3mS. When internal VLCD is not used, UC1698u will NOT drain VLCD during RESET. System designers need to make sure external VLCD source is properly drained off before turning off VDD. Figure 6:Reference Power-Down Sequence Figure 7: Delay allowance between VDD and VDD2/3 VL-PS-COG-VL248160-02 REV.A (COG-VL248160) NOV/2008 PAGE 12 OF 12 6. LCD Cosmetic Conditions Refer to the document: TBD. Note: LCD size of the product is TBD. Remark 7. “Varitronix Limited reserves the right to change this specification.” Tel:(852) 2197-6000. Fax:(852) 2343-9555. - END - URL:http://www.varitronix.com