FX-700
Low Jitter Frequency Translator
FX-700
Description
The FX-700 is a crystal-based frequency translator used in communications applications where low jitter is paramount. Performance advantages include superior jitter performance, high output frequencies and small package size. Advanced custom ASIC technology results in a highly robust, reliable and predictable device. The device is packaged in a 16 pad ceramic package with a hermetic seam welded lid.
Features
• • • • • • • • • • 5.0 x 7.5 mm, Hermetically sealed SMD package Frequency Translation to 77.760 MHz 3.3 Volt or 5.0 Volt Supply Tri-State Output allows board test Lock Detect Commercial or Industrial Temp. Range CMOS Output Absolute Pull Range Performance to +/-100 ppm Capable of locking to an 8 kHz pulse/BITS clock Product is free of lead and compliant to EC RoHS Directive • • • • •
Applications
Frequency Translation, Clock Smoothing Telecom - SONET/SDH/ATM Datacom – DSLAM, DSLAR, Access Nodes Base Station – GSM, CDMA Cable Modem Head End
Block Diagram
LD (8) Phase Detector & LD C1 Charge Pump Out (5) Charge Pump VCOUT (3) VCIN (16)
FIN (6)
÷
(1-64)
VCXO VCXOOUT (13)
÷
(1-16384)
FOUT (10)
VDD (1)
VDB (11)
VDA (2)
VDO (14)
VCXOIN (12)
TRI-STATE (4)
GND (7, 9)
Figure 1. Functional block diagram
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Rev: 31Mar2009
Performance Specifications
Table 1. Electrical Performance Parameter
Frequency Input Frequency Output Frequency Capture Range (ordering option) Supply Voltage 1 ( VDD, VDB, VDA, VDO) Current 5 Input Input High Voltage Input Low Voltage Output Output High Voltage Outpuit Low Voltage Output Rise Time 2 Fall Time 2 Duty Cycle 3 Jitter Generation - 80.0MHz output Operating Temp (ordering option)
4
Symbol
FIN FOUT APR VDD VDD IDD VIH VIL VOH VOL tR tF SYM ΦJ TOP
Min
0.001 0.1
Typical
Maximum
77.76 80.0
Units
MHz MHz ppm
±50, ±80, or ±100 4.5 2.97 5.0 3.3 5.5 3.63 40
V V mA V V V V ns ns % ps-rms 0C
0.7*VDD 0.3*VDD 0.9*VDD 0.1*VDD 3.0 3.0 60
40
50 4.7 0/70, -40/85
1. A 0.01uF high frequency ceramic capacitor in parallel with a 0.1uF low frequency tantalum bypass capacitor is recommended 2. Figure 2 defines the waveform parameters. Figure 3 illustrates the standard test conditions under which these parameters are tested and specified. 3. Duty Cycle is defined as (on time/period) with Vs = Vdd/2 per Figure 2. Duty Cycle is measured with a 15pf load per Figure 3. 4. Other frequencies may be available, please contact factory. 5. Combined Current From VDD, VDO, VDA, and VDB
Figure 2. Output Waveform
Figure 3. Output Test Conditions (25°C ±5°C)
Absolute Maximum Ratings
Stresses in excess of the absolute maximum ratings can permanently damage the device. Functional operation is not implied at these or any other conditions in excess of conditions represented in the operational sections of this data sheet. Exposure to absolute maximum ratings for extended periods may adversely affect device reliability. Table 2. Absolute Maximum Ratings Parameter
Power Supply Storage Temperature
Symbol
VDD TSTR
Ratings
7 -55 to 125
Unit
V 0C
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Rev: 31Mar2009
Reliability
The FX-700 is capable of meeting the following qualification tests Table 3. Environmental Compliance Parameter
Mechanical Shock Mechanical Vibration Solderability Gross and Fine Leak Resistance to Solvents
Conditions
MIL-STD-883, Method 2002 MIL-STD-883, Method 2007 MIL-STD-883, Method 2003 MIL-STD-883, Method 1014 MIL-STD-883, Method 2016
Handling Precautions
Although ESD protection circuitry has been designed into the the FX-700, proper precautions should be taken when handling and mounting. VI employs a human body model and a charged-device model (CDM) for ESD susceptibility testing and design protection evaluation. ESD thresholds are dependent on the circuit parameters used to define the model. Although no industry wide standard has been adopted for the CDM, a standard HBM of resistance=1.5Kohms and capacitance = 100pF is widely used and therefore can be used for comparison purposes Table 4. Predicted ESD Ratings Model
Human Body Model Charged Device Model
Minimum
1500 V 1000 V
Conditions
MIL-STD 883, Method 3015 JEDEC, JESD22-C101
Solder Reflow Profile
Table 5. Reflow Profile (IPC/JEDEC J-STD-020C) Parameter
PreHeat Time Ramp Up Time Above 217 0C Time To Peak Temperature Time At 260 0C Ramp Down
Symbol
tS RUP tL tAMB-P tP RDN
Value
60 sec Min, 180 sec Max 3 0C/sec Max 60 sec Min, 150 sec Max 480 sec Max 20 sec Min, 40 sec Max 6 0C/sec Max
The device has been qualified to meet the JEDEC standard for Pb-Free assembly. The temperatures and time intervals listed are based on the PbFree small body requirements. The temperatures refer to the topside of the package, measured on the package body surface. The FX-700 device is hermetically sealed so an aqueous wash is not an issue.
Figure 3. Suggested IR Profile
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Outline Drawing
Dimensions in mm.
Suggested Pad Layout
Figure 5. Outline Diagram
Table 7. Pin Functions Pad #
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Symbol
VDD VDA VCOUT Tri-state C1 FIN GND LD
2 1
Function
Digital PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%) Analog PLL Supply (3.3 V +/- 10% or 5.0 V +/- 10%) Control Voltage Logic Low = Output Disable / Logic High = Output Enabled Passive Loop Filter Node Input Frequency Cover and Electrical Ground Lock Detect Output Buffer Ground Output Frequency Output Buffer Supply (3.3 V +/- 10% or 5.0 V +/- 10%) VCXO Input VCXO Output VCXO Supply (3.3 V +/- 10% or 5.0 V +/- 10%) No Internal Connection Made VCXO Control Voltage Input
GNDB FOUT VDB VCXOIN VCXOOUT VDO N.C. VCIN
1 Tri-state must be driven to a logic high or a logic low, there is no internal pull up or pull down resistor (tie pin to VDD for PLL operation). 2 LD is an open collector output requiring a 30k ohm minimum pull-up resistor to VDD. LD output is logic high under locked condition, logic low for no input at FIN, and for “out-of-lock” condition LD transitions between logic low and high at the phase detector frequency.
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Tape and Reel
Table 6. Tape and Reel Information Tape Dimensions (mm)
A 16 B 7.5 C 1.5 D 4 E 8 F 1.5 G 20.2
Reel Dimensions (mm)
H 13 I 50 J 6 K 16.4 L 178 #/Reel 500
Figure 4. Tape and Reel
FX-700 Theory of Operation
The FX-700 includes an integrated phase detector, current mode charge pump, programmable frequency dividers and VCXO. The FX-700 will translate an input frequency such as 8 kHz, 1.544 MHz or 19.440 MHz to a specific output frequency which is an integer multiple (1-16384) of the input frequency and less than or equal to 77.760 MHz. For clock smoothing applications, the input frequency is typically internally divided down by a factor of 64 (2N where N = 6) by the input frequency divider and this frequency becomes an input to the phase detector. The integrated frequency dividers (factory programmed) and crystal based VCXO allows for a large range of possible frequency translations and clock smoothing applications. The FX-700’s PLL is a feedback system which forces the output frequency to lock in both phase and frequency to the input frequency. While there will be some phase error, theory states there is no frequency error. The loop filter design will dictate many key parameters such as jitter reduction, stability, lock range and acquisition time. The external second order passive loop filter is a complex impedance in parallel with the input capacitance of the VCXO. The loop filter converts the charge pump output into the VCXO’s control voltage. VI’s loop filter design methodology involves the calculation of the open loop gain bandwidth and corresponding phase margin to determine the optimal component values that ensure high loop stability and acceptable lock in time. As a rule of thumb, the VCXO gain is typically 100 ppm/volt and the charge pump current is typically 32 uA. VI’s Applications Engineering staff can provide the external loop filter component values required to meet specific system requirements and application.
Suggested FX-700 Circuit Configuration Drawing
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Rev: 31Mar2009
Table 7. Standard Frequencies
0.01000000 0.00200000 0.00320000 0.00400000 0.00800000 0.00819200 0.00946900 0.01000000 0.01562500 0.01573400 0.01575000 0.01600000 0.02400000 0.02500000 0.03200000 0.04000000 0.04410000 0.04800000 0.04807700 0.05000000 0.06400000 0.08000000 0.10000000 0.12800000 0.24300000 A1 AR AG A2 A3 BY AU A6 AL AD AC A4 BX BR BW AP AA AB AV BT A5 A9 AH AX A8 0.25600000 0.32000000 0.38400000 0.40000000 0.48000000 0.50000000 0.51200000 0.65545000 0.77200000 0.96000000 1.00000000 1.02400000 1.21500000 1.22880000 1.25000000 1.33330000 1.50000000 1.53600000 1.54400000 1.92000000 2.00000000 2.04800000 2.30400000 2.45760000 2.50000000 AM AW AY AF AK BP AJ AE AT A7 BB B2 BU BK BG BF BE BV B3 B1 B8 B4 BD BJ BM 2.55750000 3.08800000 3.24000000 3.25000000 3.37500000 3.84000000 4.00000000 4.09600000 4.19430400 5.00000000 5.12000000 6.14400000 6.29140000 6.29145600 6.31200000 6.48000000 6.75000000 7.68000000 7.77600000 8.19200000 9.21600000 9.72000000 9.75000000 9.83040000 10.0000000 B9 B6 BL BC BH B7 BN B5 CJ C6 CD CG CC CF C7 C2 CB C9 C5 C3 CH C8 CE C1 C4 10.2300000 10.2400000 10.4142850 10.4582260 10.4872000 10.9490000 10.9500000 11.1840000 12.2880000 12.3076860 12.3520000 12.8000000 13.0000000 13.5000000 14.8351600 15.0000000 15.0336000 15.3600000 16.0000000 16.3840000 17.1840000 18.4320000 18.5280000 18.7500000 19.2000000 DP DM DV DU DN DG DJ DF D8 DY D1 D2 D3 DT DL D4 DR DW D9 D5 DE D7 DC EE DD 19.3926580 19.4400000 19.5312500 19.6608000 19.6989680 19.7190000 19.9218750 20.0000000 20.1416000 20.4800000 20.5444340 20.7135000 20.8285720 20.8286000 20.9165460 21.0050840 22.0000000 22.1047720 22.2171000 22.5792000 24.0000000 24.5760000 24.7040000 25.0000000 25.1658000 DX D6 DZ DB DK DH ED E2 E3 E4 EF E1 EG EB EH EJ E9 EK E5 E8 EC E6 E7 F7 F8 25.6000000 25.9200000 26.0000000 27.0000000 27.6480000 28.7040000 29.4912000 29.5000000 30.0000000 30.7200000 30.8800000 31.2500000 32.0000000 32.7680000 33.0000000 33.3330000 34.3680000 34.5600000 36.8640000 37.0560000 37.1250000 37.5000000 38.8800000 39.0625000 39.3216000 F6 F2 F3 F4 FB F1 F5 F9 HE H1 HF H8 H2 H3 H7 HC H6 HB HG H4 H9 HK H5 HH HD 39.8437500 40.0000000 40.2830630 40.9600000 41.0888870 41.6571440 41.6600000 41.8329130 42.0000000 42.0101690 42.5000000 42.6600000 44.2095440 44.4343000 44.6218000 44.7360000 44.9280000 45.1584000 45.8240000 46.0379460 46.7200000 46.8750000 48.0000000 49.1520000 49.4080000 HJ JF KK J1 KM KP LM KT JB KV JC JZ KX LF JW J3 JE JG JM LG JK JY JV J7 J2 50.0000000 50.0480000 51.2000000 51.8400000 52.0000000 53.3300000 54.7460000 55.0000000 60.0000000 61.3800000 61.4400000 62.2080000 62.5000000 62.9145000 63.3600000 63.8976000 64.0000000 64.1520000 65.5360000 66.0000000 70.0000000 70.6560000 71.6100000 73.7280000 74.1250000 JD KD LL J4 JP JU JL JX JR KY J5 J8 J9 LE JJ JN JT JH J6 JA KB KC KF K8 K1 74.1758000 74.2500000 75.0000000 76.8000000 77.7600000 KA K7 KH K4 K2
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Rev: 31Mar2009
Ordering Information
F X - 7 0 0 - E A E - K N K N - XX - XX
Product Family FX: Frequency Translator Package 700: 5.0 x 7.5 x2.0mm Input D: 5.0 Vdc ±10% E: 3.3 Vdc ±10% Output A: CMOS Operating Temperature E: -40 to 85 °C T: 0 to 70 °C Absolute Pull Range K: ± 50 ppm P: ± 80 ppm S: ± 100 ppm Factory Use Output Frequency (See Above) Input Frequency (See Above)
Performance Options N: Standard A: Improved Phase Noise Loop Filter BW K: External Loop Filter
Note: Not all combinations will be availabe - check with the factory to determine the optimum configuration for your application
For Additional Information, Please Contact
USA:
Vectron International 267 Lowell Road Hudson, NH 03051 Tel: 1.888.328.7661 Fax: 1.888.329.8328
Europe:
Vectron International Landstrasse, D-74924 Neckarbischofsheim, Germany Tel: +49 (0) 3328.4784.17 Fax: +49 (0) 3328.4784.30
Asia:
Vectron International 1F-2F, No 8 Workshop, No 308 Fenju Road WaiGaoQiao Free Trade Zone Pudong, Shanghai, China 200131 Tel: 86.21.5048.0777 Fax: 86.21.5048.1881
Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application. No rights under any patent accompany the sale of any such product(s) or information.
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Rev: 31Mar2009