BCM® Bus Converter
BCM6135CD1E5165yzz
S
C
NRTL
US
Isolated Fixed-Ratio DC-DC Converter
Features & Benefits
Product Ratings
• Up to 65A continuous low-voltage-side current
• Up to 3.4kW/in3 power density
• 97.9% peak efficiency
VHI = 384V (260 – 410V)
ILO = up to 65A
VLO = 48V (32.5 – 51.3V)
(no load)
K = 1/8
• 4,242VDC isolation
• Parallel operation for multi-kW arrays
Product Description
• OV, OC, UV, short-circuit and thermal protection
The CM-ChiP BCM is a high‑efficiency Bus Converter, operating
from a 260 – 410VDC high‑voltage bus to create an isolated
ratiometric 32.5 – 51.3VDC low‑side bus. This ultra‑low‑profile
module is available in a chassis‑mount form factor, incorporates
a fixed‑ratio DC-DC converter and PMBus commands and
controls. The BCM provides low output impedance, low noise,
fast transient response, high efficiency and high power density.
A low‑voltage‑side‑referenced PMBus‑compatible telemetry and
control interface provides access to the BCM’s configuration, fault
monitoring and other telemetry functions.
• PMBus® management interface
Typical Applications
• 380VDC Power Distribution
• High-End Computing Systems
• High-Density Power Supplies
Owing to its megahertz bandwidth and low series impedance, the
BCM performs as an efficient capacitance multiplier, enabling bulk
capacitance across the 48V bus to be scaled down by a factor of
1/64 across the 384V bus. Capacitance multiplication cuts down
the size and number of capacitors required by 48V PoL regulators
while freeing up real estate at the point-of-load.
The CM-ChiP BCM module offers flexible thermal management
options, with very low top- and bottom‑side thermal impedances.
Thermally‑adept CM-ChiP‑based power components enable
customers to achieve low‑cost power system solutions
with previously unattainable system size, weight and
efficiency attributes.
Package Information
• Chassis-Mount CM-ChiP™ Package
2.415 x 1.392 x 0.292in
[61.33 x 35.35 x 7.42mm]
• Weight: 68g
Note: Product images may not highlight current product markings.
BCM® Bus Converter
Page 1 of 36
Rev 1.0
06/2021
BCM6135CD1E5165yzz
Typical Applications
DATA
CLK
SGND
VHI
GROUND
CLOCK
DATA
F1
CM-ChiP BCM
+IN
+OUT
DATA
CLK
SGND
ADDR
EN
EMI GND
–IN
–OUT
ISOLATION BOUNDARY
BCM6135CD1E5165yzz with PRM™ + VTM™ and MCD + MCM™
BCM® Bus Converter
Page 2 of 36
Rev 1.0
06/2021
RADDR
SW1
COUT_EXT
Host
PMBus®
PRM
VTM
Load1
MCD
MCM
Load2
BCM6135CD1E5165yzz
Pin Configuration
Top View
1
4
2
5
3
BCM6135 in a CM-ChiP Package
Chassis Mount
Pin Descriptions
Power Pins
Pin Number
Signal Name
Type
Function
1
+HI
HIGH SIDE POWER
2
EMI GND
EMI GROUND
3
–HI
HIGH SIDE
POWER RETURN
4
+LO
LOW SIDE POWER
Low-voltage-side positive power terminal
5
–LO
LOW SIDE
POWER RETURN
Low-voltage-side negative power terminal
High-voltage-side positive power terminal
EMI ground terminal
High-voltage-side negative power terminal
Signal Pins
Pin Number
Signal Name
Type
6
DATA
INPUT / OUTPUT
7
CLK
INPUT
8
SGND
SIGNAL GROUND
9
ADDR
INPUT
Address assignment, resistor based
10
EN
INPUT
Active-low enable pin, enables and disables the powertrain
BCM® Bus Converter
Page 3 of 36
Function
I2C™ data, PMBus® compatible
I2C clock, PMBus compatible
Signal ground
Rev 1.0
06/2021
6
7
8
9
10
BCM6135CD1E5165yzz
Part Ordering Information
Part Number
Package Type
Product Grade
Option Field
BCM6135CD1E5165T00
C = CM-ChiP Chassis-Mount
T = –40 to 125°C
00 = Step-Down
Storage and Handling Information
Attribute
Comments
Specification
Storage Temperature Range
T-Grade
–40 to 125°C
Operating Internal Temperature Range (TINT)
T-Grade
–40 to 125°C
Weight
68g
C145 Copper
Terminal Finish
Nickel
200µin
Palladium
30µin
Hard Gold
3 – 5µin
Package Plating
75µm copper with ENiG surface finish
Human Body Model
JEDEC JS-001-2017
ESD Rating
Class 2, 2000V to < 4000V
Charged Device Model
JS-002-2018
Class C2b, 750V to < 1000V
Reliability and Agency Approvals
Attribute
MTBF
Comments
Value
Telcordia Issue 2 - Method I Case III; 25°C Ground Benign, Controlled
19.8
MIL-HDBK-217Plus Parts Count - 25°C Ground Benign, Stationary,
Indoors / Computer
8.52
Unit
MHrs
cTÜVus, UL 62368-1, CAN/CSA No. C22.2 62368-1, EN 62368-1
Agency Approvals/Standards
cTÜVus, UL 60950-1, CAN/CSA No. C22.2 60950-1, EN 60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Max
Unit
960
V
480
V
–1
60
V
DATA to SGND
–0.3
5.5
V
CLK to SGND
–0.3
5.5
V
ADDR to SGND
–0.3
3.6
V
+HI to –HI
Comments
Powertrain disabled
–1
Powertrain enabled
+LO to –LO
Isolation Voltage / Dielectric Withstand
BCM® Bus Converter
Page 4 of 36
Min
Basic insulation (high-voltage side to case)
2250
Reinforced insulation (high-voltage side to low-voltage side)
4242
Basic insulation (low-voltage side to case)
707
Rev 1.0
06/2021
VDC
BCM6135CD1E5165yzz
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain Specification – Forward-Direction Operation (High-Voltage Side to Low-Voltage Side)
HI-Side Voltage Range, Continuous
VHI_DC
260
HI-Side Voltage Range, Transient
VIN_TRANS
260
HI-Side Voltage
Initialization Threshold
VμC_ACTIVE
HI-Side Quiescent Current
No-Load Power Dissipation
Transformation Ratio
LO-Side Current, Continuous
LO-Side Current, Pulsed
LO-Side Peak Overload Current
IHI_Q
PHI-NL
K
HI-side voltage where internal bias and controller are
initialized (powertrain inactive)
384
ILO_OUT_OVLD
Disabled, EN inactive state, VHI_DC = 384V
2
VHI_DC = 384V
14
VHI_DC = 260 – 410V
LO-Side Output Resistance
Switching Frequency
ηAMB
RLO_AMB
FSW
410
V
V
mA
42
62
High voltage to low voltage
K = VLO_DC / VHI_DC, at no load
1/8
20ms pulse, 25% duty cycle
65
A
78
A
97.5
1ms
104
500μs
W
V/V
5ms
110.5
200μs
Efficiency, Ambient
V
150
ILO_OUT_DC
ILO_OUT_PULSE
410
A
123.5
VHI_DC = 384V, ILO_OUT_DC = 65A
96.1
97.1
%
VHI_DC = 260 – 410V, ILO_OUT_DC = 65A
95.0
VHI_DC = 384V, ILO_OUT_DC = 32.5A
96.8
97.8
VHI_DC = 384V, ILO_OUT_DC = 65A
9.8
16.5
22.2
VHI_DC = 384V, ILO_OUT_DC = 65A
1.1
1.2
1.3
Over rated line, continuous load range, temperature
1.1
%
%
1.5
mΩ
MHz
VLO_OUT_PP
CLO_EXT = 0μF, ILO_OUT_DC = 65A,
VHI_DC = 384V, 20MHz BW
425
mV
Effective HI-Side Capacitance
CHI_INT
Effective value at VHI_DC = 384V
0.188
μF
Effective LO-Side Capacitance
CLO_INT
Effective value at VLO_DC = 48V
37.7
μF
CLO_OUT
Rated LO-side connected capacitance at start up,
ILO_OUT_DC = 0A. Excessive capacitance may prevent
module start up.
LO-Side Voltage Ripple
Rated LO-Side Capacitance (External)
Rated LO-Side Capacitance
(External), Parallel Array Operation
BCM® Bus Converter
Page 5 of 36
CLO_OUT_AEXT
CLO_EXT Max = N • 0.5 • CLO_EXT MAX,
where N = number of units in parallel
Rev 1.0
06/2021
100
μF
BCM6135CD1E5165yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Protection Specification – Forward-Direction Operation (High-Voltage Side to Low-Voltage Side)
Auto Restart Time
tAUTO_RESTART
Start up into a persistent fault condition.
Non-latching fault detection given VHI_DC > VHI_UVLO+
2000
ms
190
V
HI-Side Undervoltage
Lockout Threshold
VHI_UVLO–
HI-Side Undervoltage
Recovery Threshold
VHI_UVLO+
230
HI-Side Undervoltage
Lockout Hysteresis
VHI_UVLO_HYST
10
V
tHI_UVLO
200
µs
HI-Side Overvoltage
Lockout Threshold
VHI_OVLO+
435
HI-Side Overvoltage
Recovery Threshold
VHI_OVLO–
HI-Side Overvoltage
Lockout Hysteresis
HI-Side Undervoltage
Lockout Response Time
HI-Side Overvoltage
Lockout Response Time
HI-Side Undervoltage/Overvoltage
Retry Time
160
445
V
V
425
V
VHI_OVLO_HYST
10
V
tHI_OVLO
200
µs
Start up into persistent fault condition;
Non-latching fault detection given: VHI_DC > VμC_ACTIVE
350
ms
tUVLO_OVLO_RETRY
410
260
HI-Side Undervoltage Start-Up Delay
tHI_UVLO+_DELAY
From VHI_DC = VHI_UVLO+ to powertrain active,
EN held in active state, (i.e., one-time start-up delay
from application of VHI_DC to VLO_DC)
440
ms
LO-Side Soft-Start Time
tLO_SOFT_START
From powertrain active, no load; fast current limit
protection disabled during soft-start
300
µs
LO-Side Output Overcurrent
Trip Threshold
ILO_OUT_OCP
LO-Side Output Overcurrent
Response Time
tLO_OUT_OCP
8
ms
LO-Side Output Short-Circuit
Protection Trip Threshold
ILO_OUT_SCP
145
A
LO-Side Output Short-Circuit
Protection Response Time
tLO_OUT_SCP
1
µs
79
Overtemperature
Shut-Down Threshold
TOTP+
Temperature sensor located inside controller IC
Overtemperature
Recovery Threshold
TOTP–
Temperature sensor located inside controller IC
BCM® Bus Converter
Page 6 of 36
Rev 1.0
06/2021
94
100
100
A
°C
90
°C
BCM6135CD1E5165yzz
90
70
TTOP Case Temperature (°C)
Low-Side Output Current (A)
Operating Area
60
50
40
30
20
10
0
0
10
20
30
40
60
50
70
80
80
70
60
50
40
30
20
10
0
90 100 110 120 130
0
Case Temperature (°C)
5
10
15
20
25
30
35
40
45
50
TBOTTOM Package Temperature (°C)
TTOP / TBOTTOM at temperature
ILO_OUT_DC = 65A
(a)
(b)
4500
Low-Side Output Current (A)
Low-Side Output Power (W)
Figure 1 — Specified thermal operating area: (a) equal top and bottom surface temperatures;
(b) unequal top and bottom package surface temperatures.
4000
3500
3000
2500
2000
1500
1000
500
0
260
275
290
305
320
335
350
365
380
395
410
High-Side Input Voltage (V)
PLO_OUT_DC
80
70
60
50
40
30
20
10
0
260
275
290
305
320
335
350
365
High-Side Input Voltage (V)
PLO_OUT_PULSE
ILO_OUT_DC
Figure 2 — Specified electrical operating area using rated RLO_ AMB
BCM® Bus Converter
Page 7 of 36
90
Rev 1.0
06/2021
ILO_OUT_PULSE
380
395
410
BCM6135CD1E5165yzz
PMBus® Reported Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Monitored Telemetry
PMBus Read Command
Accuracy
(Rated Range)
Functional
Reporting Range
Update
Rate
Reported Units
HI-Side Voltage
(88h) READ_VIN
±2% (Powertrain Enabled)
160 – 480V
100µs
VACTUAL = VREPORTED x 10–1
LO-Side Voltage
(8Bh) READ_VOUT
±1%
0 – 60V
100µs
VACTUAL = VREPORTED x 10–1
LO-Side Current
(8Ch) READ_IOUT
–5%, +10%
0 – 95A
100µs
IACTUAL = IREPORTED x 10–2
(8Dh) READ_TEMPERATURE_1
±7°C (Full Range)
–55 to 130ºC
100ms
TACTUAL = TREPORTED
Attribute
Temperature
Variable Parameters
• Variables can be written only when module is disabled with VHI or VHI_DC < VHI_UVLO–.
• Module must remain in a disabled mode for 3ms after any changes to the variables below to allow sufficient time to commit changes to EEPROM.
Attribute
PMBus Command
Conditions / Notes
Accuracy
(Rated Range)
Functional
Reporting
Range
Default
Value
(60h) TON_DELAY
Additional time delay to the
undervoltage start-up delay
±50µs
0 – 100ms
0ms
Overtemperature
Protection Limit
(4Fh) OT_FAULT_LIMIT
Internal temperature monitor
±7°C (Full Range)
0 – 100°C
100%
Overtemperature
Warning Limit
(51h) OT_WARN_LIMIT
Internal temperature monitor
±7°C (Full Range)
0 – 100°C
100%
Turn-On Delay
BCM® Bus Converter
Page 8 of 36
Rev 1.0
06/2021
BCM6135CD1E5165yzz
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Please note: For chassis mount model, Vicor part number 48705-3001R7 or equivalent will be needed for applications requiring the use of the signal pins.
To avoid unnecessary stress on the connector, the cable should be appropriately strain relieved.
Enable (EN) Pin
• The EN pin is a standard analog I/O configured as an input to an internal μC.
• It is internally pulled high to 3.3V.
• When pulled high, the BCM internal bias will be disabled and the powertrain will be inactive.
• In an array of BCMs, EN pins should be interconnected to synchronize start up.
• PMBus® ON/OFF command has no effect if the BCM EN pin is not in the active state. This BCM has active low EN pin logic.
Signal Type
State
Attribute
Symbol
Conditions / Notes
Start Up
EN to Powertrain Active Time
tEN_START
VHI_DC > VHI_UVLO+, EN active,
both conditions satisfied for
t > tHI_UVLO+DELAY
EN Voltage Threshold
VENABLE
EN Resistance (Internal)
REN_INT
Input
Regular
Operation
EN Disable Threshold
Min
Typ
Max
2
ms
1
Internal pull-up resistor
10
V
kΩ
2.3
VEN_DISABLE_TH
Unit
V
SGND Pin
• All PMBus interface signals (CLK, DATA, ADDR, EN) are referenced to SGND pin.
• SGND pin and low-voltage‑side power‑return terminal (–LO) are common.
To avoid noise interference, keep SGND signal separated from –LO in electrical design.
Address (ADDR) Pin
• This pin programs the address using a resistor between ADDR pin and signal ground.
• The address is sampled during start up and is stored until power is reset. This pin programs only a fixed and persistent address.
• This pin has an internal 10kΩ pullup resistor to 3.3V.
• 16 addresses are available. The range of each address is 206.25mV (total range for all 16 addresses is 0 – 3.3V).
Signal Type
Multi‑Level
Input
State
Regular
Operation
Start Up
BCM® Bus Converter
Page 9 of 36
Attribute
Symbol
Conditions / Notes
ADDR Input Voltage
VSADDR
See address section
ADDR Leakage Current
ISADDR
Leakage current
ADDR Registration Time
tSADDR
From VVDDB_MIN
Rev 1.0
06/2021
Min
Typ
0
1
Max
Unit
3.3
V
1
µA
ms
BCM6135CD1E5165yzz
Signal Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade). All other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Please note: For chassis mount model, Vicor part number 48705-3001R7 or equivalent will be needed for applications requiring the use of the signal pins.
To avoid unnecessary stress on the connector, the cable should be appropriately strain relieved.
Serial Clock input (CLK) and Serial Data (DATA) Pins
• High-power SMBus specification and SMBus physical layer compatible. Note that optional SMBALERT# is not supported.
• PMBus® command compatible.
Signal Type
State
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Electrical Parameters
VIH
Input Voltage Threshold
2.1
VIL
0.8
VOH
Output Voltage Threshold
3
VOL
Leakage Current
ILEAK_PIN
Signal Sink Current
ILOAD
Unpowered device
VOL = 0.4V
CI
Signal Noise Immunity
VNOISE_PP
0.4
V
10
µA
mA
10
10 – 100MHz
300
Idle state = 0Hz
10
V
V
4
Total capacitive load of
one device pin
Signal Capacitive Load
V
pF
mV
Timing Parameters
Digital
Input / Output
Regular
Operation
Operating Frequency
FSMB
Free Time Between
Stop and Start Condition
tBUF
Hold Time After Start or
Repeated Start Condition
tHD:STA
Repeat Start Condition
Set-Up Time
µs
0.6
µs
tSU:STA
0.6
µs
Stop Condition Set-Up Time
tSU:STO
0.6
µs
Data Hold Time
tHD:DAT
300
ns
Data Set-Up Time
tSU:DAT
100
ns
Clock Low Time Out
tTIMEOUT
25
Clock Low Period
tLOW
1.3
Clock High Period
tHIGH
0.6
Cumulative Clock Low
Extend Time
tLOW:SEXT
Clock or Data Fall Time
tF
Clock or Data Rise Time
tR
tLOW tR
First clock is generated
after this hold time
tF
VIH
VIL
tHD,STA
SDA
P
kHz
1.3
SCL
VIH
VIL
400
tBUF
tHD,DAT
tHIGH
tSU,DAT
S
BCM® Bus Converter
Rev 1.0
Page 10 of 36 06/2021
tSU,STA
tSU,STO
S
P
35
ms
µs
50
µs
25
ms
20
300
ns
20
300
ns
BCM6135CD1E5165yzz
Application Characteristics
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (high side to low side). See associated figures for general trend data.
120
99
Power Dissipation (W)
Efficiency (%)
98
100
97
96
95
94
93
92
80
60
40
20
0
0
6.5
13
19.5
26
32.5
39
45.5
52
58.5
65
0
6.5
13
Low-Side Output Current (A)
VHI:
260V
384V
410V
VHI:
Figure 3 — Efficiency at T TOP, TBOTTOM = –40°C
32.5
39
45.5
52
58.5
65
260V
384V
58.5
65
58.5
65
410V
120
Power Dissipation (W)
98
Efficiency (%)
26
Figure 4 — Power dissipation at T TOP, TBOTTOM = –40°C
99
100
97
96
95
94
93
92
80
60
40
20
0
0
6.5
13
19.5
26
32.5
39
45.5
52
58.5
65
0
6.5
13
Low-Side Output Current (A)
VHI:
260V
384V
19.5
26
32.5
39
45.5
52
Low-Side Output Current (A)
410V
VHI:
Figure 5 — Efficiency at T TOP, TBOTTOM = 25°C
260V
384V
410V
Figure 6 — Power dissipation at T TOP, TBOTTOM = 25°C
120
99
Power Dissipation (W)
98
Efficiency (%)
19.5
Low-Side Output Current (A)
100
97
96
95
94
93
92
80
60
40
20
0
0
6.5
13
19.5
26
32.5
39
45.5
52
58.5
65
0
6.5
13
Low-Side Output Current (A)
VHI:
260V
384V
410V
Figure 7 — Efficiency at T TOP = 85°C, TBOTTOM = 45°C
19.5
26
32.5
39
45.5
52
Low-Side Output Current (A)
VHI:
260V
384V
410V
Figure 8 — Power dissipation at T TOP = 85°C, TBOTTOM = 45°C
BCM® Bus Converter
Rev 1.0
Page 11 of 36 06/2021
BCM6135CD1E5165yzz
Application Characteristics (Cont.)
25
Low-Side Output Voltage
Ripple (mVP-P)
No-Load Power Dissipation (W)
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (primary side to secondary side). See associated figures for general trend data.
20
15
10
5
0
260
275
290
305
320
335
350
365
380
395
275
250
225
200
175
150
125
100
75
0
410
6.5
13
19.5
26
32.5
39
45.5
52
58.5
Low-Side Output Current (A)
High-Side Input Voltage (V)
TTOP, TBOTTOM = –40°C
350
325
300
VHI:
TTOP, TBOTTOM = 25°C
384V
TTOP = 85°C, TBOTTOM = 45°C
Figure 9 — No-load power dissipation vs. VHI_DC
Figure 10 — VLO_OUT_PP vs. ILO_DC ; no external CLO_OUT_EXT;
board-mounted module, scope setting:
20MHz analog BW
CH2
CH1
CH1 VLO: 100mV/div
CH2 IHI: 100mA/div
Timebase: 500ns/div
Figure 11 — Full-load low-side voltage and high-side current ripple;
no external CLO_OUT_EXT
BCM® Bus Converter
Rev 1.0
Page 12 of 36 06/2021
65
BCM6135CD1E5165yzz
Application Characteristics (Cont.)
Temperature controlled via top-side cold plate, unless otherwise noted. All data presented in this section are collected from units processing power in the
forward direction (primary side to secondary side). See associated figures for general trend data.
CH1
CH1
CH2
CH2
CH1 VLO: 2V/div
CH2 ILO: 20A/div
Timebase: 5µs/div
Figure 12 — 0 – 65A transient response, VHI = 384V,
CLO_OUT_EXT = 0µF
CH1 VLO: 2V/div
CH2 ILO: 20A/div
Timebase: 5µs/div
Figure 13 — 65 – 0A transient response, VHI = 384V,
CLO_OUT_EXT = 0µF
CH1
CH1
CH2
CH2
CH3
CH3
CH4
CH1 VHI: 200V/div
CH2 VLO: 20V/div
CH4
CH3 EN: 5V/div
CH4 IHI: 2A/div
Timebase: 100ms/div
Figure 14 — Start up from application of VHI = 384V,
0% ILO_OUT_DC, 100% CLO_OUT_EXT
CH1 VHI: 200V/div
CH2 VLO: 20V/div
CH3 EN: 5V/div
CH4 IHI: 2A/div
Timebase: 500µs/div
Figure 15 — Start up from application of EN with pre-applied
VHI = 384V, 0% ILO_OUT_DC, 100% CLO_OUT_EXT
BCM® Bus Converter
Rev 1.0
Page 13 of 36 06/2021
BCM6135CD1E5165yzz
BCM in a CM-ChiP™
ILO
IHI
RLO
+
+
K • ILO
VHI
+
IHI_Q
–
V•I
K
+
K • VHI
VLO
–
–
–
Figure 16 — BCM DC model
The BCM uses a high-frequency resonant tank to move energy
from the high-voltage side to low-voltage side and vice versa.
The resonant LC tank, operated at high frequency, is amplitude
modulated as a function of the high-side voltage and the low-side
current. A small amount of capacitance embedded in the highvoltage-side and low-voltage stages of the module is sufficient for
full functionality and is key to achieving high power density.
The effective DC voltage transformer action provides additional
interesting attributes. Assuming that RLO = 0Ω and
IHI_Q = 0A, Equation 3 now becomes Equation 1 and is essentially
load independent, resistor R is now placed in series with VHI.
The BCM6135CD1E5165Yzz can be simplified into the model
shown in Figure 16.
R
At no load:
VHI
VLO = VHI • K
VLO
The relationship between VHI and VLO becomes:
VLO = (VHI – IHI • R) • K
In the presence of a load, VLO is represented by:
VLO = VHI • K – ILO • RLO
(3)
IHI – IHI_Q
K
VLO = VHI • K – ILO • R • K 2
(4)
RLO represents the impedance of the BCM, and is a function of the
RDS_ON of the high-voltage-side and low-voltage-side MOSFETs and
the winding resistance of the power transformer. IHI_Q represents
the quiescent current of the BCM controller, gate drive circuitry
and core losses.
(5)
Substituting the simplified version of Equation 4
(IHI_Q is assumed = 0A) into Equation 5 yields:
and ILO is represented by:
ILO =
VLO
Figure 17 — K = 1/8 BCM with series high-voltage-side resistor
(2)
VHI
BCM
K = 1/8
(1)
K represents the “turns ratio” of the BCM.
Rearranging Equation 1:
K =
+
–
(6)
This is similar in form to Equation 3, where RLO is used to represent
the characteristic impedance of the BCM. However, in this case a
real resistor, R on the high-voltage side of the BCM is effectively
scaled by K 2 with respect to the low-voltage side.
Assuming that R = 1Ω, the effective R as seen from the low-voltage
side is 16mΩ, with K = 1/8.
BCM® Bus Converter
Rev 1.0
Page 14 of 36 06/2021
BCM6135CD1E5165yzz
A similar exercise can be performed with the additon of a
capacitor or shunt impedance at the high-voltage side of the
BCM. A switch in series with VHI is added to the circuit. This is
depicted in Figure 18.
S
VHI
+
–
BCM
K = 1/8
C
VLO
Low impedance is a key requirement for powering a high‑current,
low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a BCM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, these benefits are
not achieved if the series impedance of the BCM is too high. The
impedance of the BCM must be low, i.e., well beyond the crossover
frequency of the system.
A solution for keeping the impedance of the BCM low involves
switching at a high frequency. This enables the use of small
magnetic components because magnetizing currents remain low.
Small magnetics mean small path lengths for turns. Use of low-loss
core material at high frequencies also reduces core losses.
Figure 18 — BCM with high-voltage-side capacitor
The two main terms of power loss in the BCM are:
A change in VHI with the switch closed would result in a change in
capacitor current according to the following equation:
dVHI
IC (t) = C
(7)
dt
(8)
C
K
2
•
dVLO
dt
(10)
Therefore,
substituting Equation 1 and 8 into Equation 7 reveals:
ILO(t) =
n
Resistive loss (PRLO): refers to the power loss across
the BCM modeled as pure resistive impedance.
PDISSIPATED = PHI_NL + PRLO
Assume that with the capacitor charged to VHI, the switch is
opened and the capacitor is discharged through the idealized
BCM. In this case,
IC = ILO • K
n
No load power dissipation (PHI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
PLO_OUT = PHI_IN – PDISSIPATED = PHI_IN – PHI_NL – PRLO
(11)
The above relations can be combined to calculate the overall
module efficiency:
(9)
The equation in terms of the low-voltage side has yielded a K 2
scaling factor for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the low-voltage side when expressed in terms of the
high‑voltage side. With K = 1/8 as shown in Figure 18, C = 1µF
would appear as C = 64µF when viewed from the low-voltage side.
η=
=
PLO_OUT
PHI_IN
PHI_IN – PHI_NL – PRLO
PHI_IN
VHI • IHI – PHI_NL – (ILO)2 • RLO
= 1 –
BCM® Bus Converter
Rev 1.0
Page 15 of 36 06/2021
=
VHI • IHI
(
)
PHI_NL + (ILO)2 • RLO
VHI • IHI
(12)
BCM® Bus Converter
Rev 1.0
Page 16 of 36 06/2021
OUTPUT
INPUT
+VLO
+VHI
VµC_ACTIVE
VHI_OVLO+
VNOM
STARTUP
tHI_UVLO+_DELAY
VHI_UVLO+
VHI_UVLO-
VHI_OVLO-
OVERVOLTAGE
T
NI
E
IA N
LT
VO
I NO
R
N
R R
E
R
LE TU
OV
TU
E
E
RO IDE
T
D
D
N S
SI
SI
HI
CO LO
HI
ON
LIZ
E
AG
A
OPERATION
COMMAND
CONTROL
M
F
ON
T
OR
SH
D
AN
OF
OVERCURRENT
tAUTO_RESTART
> tHI_UVLO+_DELAY tLO_OUT_SCP
M M
C O CO
N
N
O
RE
T I ATIO
A
DE
I
S
E R ER
HI
O P OP
RT
A
ST
M
ND
C
CU
IR
DE
SI
I
H
T
RN
TU
SHUTDOWN
IT
EN
EV
OF
F
BCM6135CD1E5165yzz
Timing Diagram (Forward Direction)
BCM6135CD1E5165yzz
Input and Output Filter Design
Current Sharing
A major advantage of BCM systems versus conventional PWM
converters is that the transformer based BCM does not require
external filtering to function properly. The resonant LC tank,
operated at extreme high frequency, is amplitude modulated as a
function of high-voltage-side voltage and low-voltage-side current
and efficiently transfers charge through the isolation transformer.
A small amount of capacitance embedded in the high-voltage‑side
and low-voltage‑side stages of the module is sufficient for full
functionality and is key to achieving power density.
The performance of the BCM topology is based on efficient
transfer of energy through a transformer without the need of
closed loop control. For this reason, the transfer characteristic
can be approximated by an ideal transformer with a positive
temperature coefficient series resistance.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
When multiple BCMs of a given part number are connected in an
array, they will inherently share the load current according to the
equivalent impedance divider that the system implements from the
power source to the point of load. Ensuring equal current sharing
among modules requires that BCM array impedances be matched.
n
Guarantee low source impedance:
To take full advantage of the BCM’s dynamic response, the
impedance presented to its high-voltage-side terminals must be
low from DC to approximately 5MHz. The connection of the bus
converter module to its power source should be implemented
with minimal distribution inductance. If the interconnect
inductance exceeds 100nH, the input should be bypassed with a
RC damper to retain low source impedance and stable operation.
With an interconnect inductance of 200nH, the RC damper
may be as high as 1µF in series with 0.3Ω. A single electrolytic
or equivalent low-Q capacitor may be used in place of the
series RC bypass.
n
Further reduce high-voltage-side and/or low-voltage-side
voltage ripple without sacrificing dynamic response:
This type of characteristic is close to the impedance characteristic
of a DC power distribution system both in dynamic (AC) behavior
and for steady state (DC) operation.
Some general recommendations to achieve matched array
impedances include:
n
Dedicate common copper planes within the PCB to deliver and
return the current to the modules.
n
Provide as symmetric a PCB layout as possible among modules
n
A dedicated input filter for each BCM in an array is required to
prevent circulating currents.
For further details see:
AN:016 Using BCM Bus Converters in High Power Arrays.
Given the wide bandwidth of the module, the source response
is generally the limiting factor in the overall system response.
Anomalies in the response of the high-voltage-side source
will appear at the low-voltage side of the module multiplied
by its K factor.
VPRI
n
Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
CHI
K2
ZOUT_EQ1
BCM®2
VSEC
ZOUT_EQ2
R0_2
+ DC
Load
ZIN_EQn
BCM®n
R0_n
Figure 19 — BCM parallel array
Within this frequency range, capacitance at the high-voltage side
appears as effective capacitance on the low-voltage side per the
relationship defined in Equation 13.
CLO =
BCM®1
R0_1
ZIN_EQ2
The module high- and low-voltage-side voltage ranges shall not
be exceeded. An internal overvoltage lockout function prevents
operation outside of the normal operating high-voltage-side
range. Even when disabled, the powertrain is exposed to the
applied voltage and the power MOSFETs must withstand it.
Total load capacitance at the low-voltage side of the BCM
shall not exceed the specified maximum. Owing to the wide
bandwidth and minimal low-voltage-side impedance of the
module, low‑frequency bypass capacitance and significant energy
storage may be more densely and efficiently provided by adding
capacitance at the high‑voltage side of the module. At frequencies
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