BCM48BH120M120A00

BCM48BH120T120A00 BCM48BH120M120A00 (Formerly VIB0101THJ) BCM Bus Converter TM C S NRTL US FEATURES • 48 Vdc – 12 Vdc 120 W Bus Converter • High efficiency (>95%) reduces system power consumption • High power density (801 W/in3) reduces power system footprint by >50% • “Half Chip” V•I Chip package enables surface mount, low impedance interconnect to system board • Contains built-in protection features: undervoltage, overvoltage lockout, over current protection, short circuit protection, overtemperature protection. DESCRIPTION The V•I ChipTM Bus Converter is a high efficiency (>95%) Sine Amplitude ConverterTM (SACTM) operating from a 38 to 55 Vdc primary bus to deliver an isolated 12 V nominal, unregulated secondary. The SAC offers a low AC impedance beyond the bandwidth of most downstream regulators, meaning that input capacitance normally located at the input of a 12 V regulator can be located at the input to the SAC. Since the K factor of the BCM48BH120T120A00 is 1/4, that capacitance value can be reduced by a factor of 16x, resulting in savings of board area, materials and total system cost. The BCM48BH120T120A00 is provided in a V•I Chip package compatible with standard pick-and-place and surface mount assembly processes. The V•I Chip package provides flexible thermal management through its low junction-to-case and junction-to-board thermal resistance. With high conversion efficiency the BCM48BH120T120A00 increases overall system efficiency and lowers operating costs compared to conventional approaches. • Provides enable/disable control, internal temperature monitoring • ZVS/ZCS Resonant Sine Amplitude Converter topology • Less than 50°C temperature rise at full load in typical applications TYPICAL APPLICATION VIN = 38 – 55 V VOUT = 9.5 – 13.75 V (NO LOAD) POUT = 120 W(NOM) K = 1/4 • High End Computing Systems • Automated Test Equipment • Telecom Base Stations • High Density Power Supplies • Communication Systems TYPICAL APPLICATION PART NUMBER BCM48BH120T120A00 DESCRIPTION -40°C – 125°C TJ, J lead enable / disable switch SW1 F1 POL TM PC POL +In VIN 3.15 A C1 10 µF -In BCM +Out VOUT -Out POL POL V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 1 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET ABSOLUTE MAXIMUM RATINGS +IN to –IN . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc – +60 Vdc PC to –IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +20 Vdc TM to –IN . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +7.0 Vdc +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 2250 V (Hi Pot) +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . . 60 V (working) +OUT to –OUT . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc - +16 Vdc Temperature during reflow . . . . . . . . . . . . . . . . 245°C (MSL 6) PACKAGE ORDERING INFORMATION 4 A 3 2 1 CONTROL PIN SPECIFICATIONS See section 5.0 for further application details and guidelines. PC (V•I Chip BCM Primary Control) The PC pin can enable and disable the BCM. When held below VPC-DIS the BCM shall be disabled. When allowed to float with an impedance to –IN of greater than 60 kΩ the module will start. When connected to another BCM PC pin (either directly, or isolated through a diode), the BCMs will start simultaneously when enabled. The PC pin is capable of being either driven high by an external logic signal or internal pull up to 5 V (operating). TM (V•I Chip BCM Temperature Monitor) The TM pin monitors the internal temperature of the BCM within an accuracy of +5/-5 °C. It has a room temperature setpoint of ~3.0 V and an approximate gain of 10 mV/°C. It can source up to 100 uA and may also be used as a “Power Good” flag to verify that the BCM is operating. +In +Out B C D J K E F G H -Out L M NC TM NC PC -In Bottom View Signal Name +In –In NC TM NC PC +Out –Out Designation A1-B1, A2-B2 L1-M1, L2-M2 E1 F2 G1 H2 A3-D3, A4-D4 J3-M3, J4-M4 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 2 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 1.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25º unless otherwise noted ATTRIBUTE Voltage range dV/dt Quiescent power No load power dissipation Inrush current peak DC input current K factor SYMBOL VIN dVIN /dt PQ PNL IINR-P IIN-DC K POUT POUT-P VOUT IOUT η η η ROUT ROUT ROUT COUT FSW FSW-RP VOUT-PP TON1 VIN = 38 – 55 Vdc; See Figure 14 VIN = 46 – 55 Vdc; See Figure 14 VIN = 46 – 55 Vdc Average POUT < = 120 W, Tpeak < 10 ms Section 3.0 Pout < =120 W VIN = 48 V, POUT = 120 W VIN = 38 V to 55 V, POUT = 100 W VIN = 48 V, TJ = 100°C, POUT = 120 W 24 W < POUT < POUT Max TJ = 25°C TJ = 125°C TJ = -40°C 8.5 93 90.5 92.6 89 35.4 46.1 27.2 1.60 3.20 COUT = 0 µF, IOUT = 10.55 A, VIN = 48 V, Section 8.0 VIN = 48 V, CPC = 0; See Figure 16 44.1 56.1 35.0 1.75 3.50 140 570 55.8 69.1 45.7 500 1.90 3.80 355 800 94.6 93.7 1/4 97 120 150 14 11.3 W W V A % % % mΩ mΩ mΩ uF MHz MHz mV ms CONDITIONS / NOTES MIN 38 PC connected to -IN VIN = 48 V VIN = 38 to 55 V VIN = 48 V COUT = 500 µF, IOUT = 10.55 A TYP 48 68 1.7 5.5 MAX 55 1 150 3.0 3.5 12 3.5 UNIT Vdc V/µs mW W A A () VOUT VIN Output power (average) Output power (peak) Output voltage Output current (average) Efficiency (ambient) Efficiency (hot) Minimum efficiency (over load range) Output resistance (ambient) Output resistance (hot) Output resistance (cold) Load capacitance Switching frequency Ripple frequency Output voltage ripple VIN to VOUT (application of VIN) PC PC voltage (operating) PC voltage (enable) PC voltage (disable) PC source current (startup) PC source current (operating) PC internal resistance PC capacitance (internal) PC capacitance (external) External PC resistance PC external toggle rate PC to VOUT with PC released PC to VOUT, disable PC VPC VPC-EN VPC-DIS IPC-EN IPC-OP RPC-SNK CPC_INT CPC_EXT RPC FPC-TOG Ton2 TPC-DIS 4.7 2.0 50 Internal pull down resistor Section 5.0 External capacitance delays PC enable time Connected to –VIN VIN = 48 V, Pre-applied; See Figure 16 VIN = 48 V, Pre-applied; See Figure 16 50 5.0 2.5 100 150 5.3 3.0 1.95 300 2 400 588 1000 1 100 10 60 60 4 V V V uA mA kΩ pF pF kΩ Hz µs µs V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 3 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET 1.0 ELECTRICAL CHARACTERISTICS (CONT.) Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25º unless otherwise noted ATTRIBUTE TM TM accuracy TM gain TM source current TM internal resistance External TM capacitance TM voltage ripple PROTECTION Negative going OVLO Positive going OVLO Negative going UVLO Positive going UVLO Output overcurrent trip Short circuit protection trip current Short circuit protection response time Thermal shutdown junction setpoint GENERAL SPECIFICATION Isolation voltage (Hi-Pot) Working voltage (IN – OUT) Isolation vapacitance Isolation resistance MTBF Agency approvals / standards SYMBOL CONDITIONS / NOTES MIN TYP MAX UNIT Actm ATM ITM RTM-SNK CTM VTM-PP -5 10 25 CTM = 0 uF, VIN = 55 V, POUT = 120 W 75 40 180 +5 100 50 50 250 ºC mV/°C uA kΩ pF mV VIN OVLOVIN OVLO+ VIN UVLOVIN UVLO+ IOCP ISSP TSSP TJ-OTP VIN = 48 V, 25°C 55.1 55.5 29.1 30.7 12 15 0.8 125 57.8 58.1 30.8 32.6 20 59.4 59.4 35.4 37.3 25 40 V V V V A A us °C 1.0 130 1.2 135 VHIPOT Vworking CIN-OUT RIN-OUT 2250 Unpowered unit MIL HDBK 217F, 25°C, GB cTUVus CE Mark ROHS 6 of 6 1350 10 1750 7.1 60 2150 V V pF MΩ Mhrs V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 4 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 1.1 APPLICATION CHARACTERISTICS All specifications are at TJ = 25ºC unless otherwise noted. See associated figures for general trend data. ATTRIBUTE No load power Inrush current peak Efficiency (ambient) Efficiency (hot – 100°C) Output resistance (-40°C) Output resistance (25°C) Output resistance (100°C) Output voltage ripple VOUT transient (positive) VOUT transient (negative) Undervoltage lockout response time Output Overcurrent Response Time Overvoltage Lockout Response Time SYMBOL PNL INR-P η η ROUT_C ROUT_R ROUT_H VOUT-PP VOUT-TRAN+ VOUT-TRANTUVLO TOCP TOVLO 12 < IOCP < 25 A CONDITIONS / NOTES VIN = 48 V, PC enabled; See Figure 1 COUT = 500 µF, POUT = 120 W VIN = 48 V, POUT = 120 W COUT = 500 µF VIN = 48 V, POUT = 120 W COUT = 500 µF VIN = 48 V VIN = 48 V VIN= 48 V COUT = 0uF, POUT = 120 W @ VIN = 48, VIN = 48 V IOUT_STEP = 0 TO 10.55 A, ISLEW >10 A/us; See Figure 12 IOUT_STEP = 10.55 A to 0 A, ISLEW > 10 A/us; See Figure 11 TYP 1.75 6 95 94 35 44 56 160 1.4 1.3 2.4 4.4 2.4 UNIT W A % % mΩ mΩ mΩ mV V V us ms µs V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 5 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET No Load Power Dissipation vs. Line No Load Power Dissipation (W) 3 96 95 Full Load Efficiency vs. Case Temperature Efficiency (%) 2.5 94 93 92 91 -40 -20 VIN : 0 38 V 20 40 48 V 60 55 V 80 100 2 1.5 1 38 40 TCASE: 42 44 -40ºC 46 47 25ºC 49 51 100ºC 53 55 Case Temperature (C) Input Voltage (V) Figure 1 – No load power dissipation vs. VIN; TCASE Figure 2 – Full load efficiency vs. temperature; VIN Efficiency & Power Dissipation -40°C Case 96 94 16 96 94 Efficiency & Power Dissipation 25°C Case 16 Power Dissipation (W) Efficiency (%) Efficiency (%) 92 90 88 86 84 82 80 0 VIN : 12 10 92 90 88 86 84 82 80 0 2 4 12 10 8 PD 8 6 4 2 0 PD 6 4 2 0 6 8 10 12 2 38 V 4 6 8 Output Load (A) 48 V 55 V 38 V 10 12 48 V 55 V Output Load (A) VIN: 38 V 48 V 55 V 38 V 48 V 55 V Figure 3 – Efficiency and power dissipation at -40°C (case); VIN Figure 4 – Efficiency and power dissipation at 25°C (case); VIN Efficiency & Power Dissipation 100°C Case 96 94 16 60 ROUT vs. CaseTemperature Power Dissipation (W) Efficiency (%) 92 90 88 86 84 82 80 0 2 4 η 14 12 10 8 55 50 ROUT (m ) 45 40 35 30 25 20 -40 -20 0 20 40 60 80 100 PD 6 4 2 0 6 8 10 12 Output Load (A) VIN : 38 V 48 V 55 V 38 V 48 V 55 V I OUT : Temperature (°C) 1.05 A 10.55 A Figure 5 – Efficiency and power dissipation at 100°C (case); VIN Figure 6 – ROUT vs. temperature vs. IOUT V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 6 of 16 Power Dissipation (W) 14 η 14 BCM48BH120T120A00 - BCM48BH120M120A00 Output Voltage Ripple 25°C vs. IOUT 180 160 140 Vripple (mV) 120 100 80 60 40 20 0 0 2 4 6 8 10 IOUT (A) Figure 7 – Vripple vs. IOUT ; 48 Vin, no external capacitance Figure 8 – PC to VOUT startup waveform Figure 9 – VIN to VOUT startup waveform Figure 10 – Output voltage and input current ripple, 48 Vin, 120 W no cOUT Figure 11 – Positive load transient (0 – 11.3 A) Figure 12 – Negative load transient (11.3 A – 0 A) V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 7 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET POUT (W) 120 97 VIN (VDC) 38 46 55 Figure 13 – PC disable waveform, 48 VIN, 500 µF COUT full load Figure 14 – POUT derating vs. VIN 2.0 PACKAGE/MECHANICAL SPECIFICATIONS All specifications are at TJ = 25ºC unless otherwise noted. See associated figures for general trend data. ATTRIBUTE Length Width Height Volume Footprint Power Density Weight Lead Finish Operating Temperature Storage Temperature Thermal Impedance Thermal Capacity Peak Compressive Force Applied to Case (Z-axis) ESD Rating Peak Temperature During Reflow Peak Time Above 183°C Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow [a] [b] SYMBOL L W H Vol F PD W CONDITIONS / NOTES MIN TYP MAX UNIT No Heatsink No Heatsink No Heatsink Nickel (0.51-2.03 µm) Palladium (0.02-0.15 µm) Gold (0.003-0.05 µm) 21.7 / 0.854 22.0 / 0.866 22.3 / 0.878 mm/in 16.37 / 0.644 16.50 / 0.650 16.63 / 0.655 mm/in 6.48 / 0.255 6.73 / 0.265 6.98 / 0.275 mm/in 2.44 / 0.150 cm3/in3 3.6 / 0.56 cm2/in2 801 W/in3 W/cm3 49 0.28/8 oz/g TJ TST ØJC -40 -40 Junction to Case 5 Supported by J-leads only 2.5 1500 400 125 125 2.7 3.0 °C °C °C/W Ws/°C lbs VDC VDC °C °C s °C/s °C/s ESDHBM ESDMM Human Body Model[a] Machine Model[b] MSL 5 MSL 6 1.5 1.5 225 245 150 3 6 JEDEC JESD 22-A114C.01 JEDED JESD 22-A115-A V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 8 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 2.1 MECHANICAL DRAWING TOP VIEW ( COMPONENT SIDE ) BOTTOM VIEW mm (inch) NOTES: mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com 2.2 RECOMMENDED LAND PATTERN 4 3 2 1 RECOMMENDED LAND PATTERN ( COMPONENT SIDE SH OWN ) +Out A B C D J K E F G H +In -Out L M NC TM NC PC -In Bottom View Signal Name +In –In NC TM NC PC +Out –Out Designation A1-B1, A2-B2 L1-M1, L2-M2 E1 F2 G1 H2 A3-D3, A4-D4 J3-M3, J4-M4 NOTES: 3. .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] mm 2. DIMENSIONS ARE inch . UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: 4. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com 2.3 RECOMMENDED LAND PATTERN FOR PUSH PIN HEATSINK Notes: 1. Maintain 3.50 (0.138) Dia. keep-out zone free of copper, all PCB layers. 2. (A) minimum recommended pitch is 24.00 (0.945) this provides 7.50 (0.295) component edge–to–edge spacing, and 0.50 (0.020) clearance between Vicor heat sinks. (B) Minimum recommended pith is 25.50 (1.004). This provides 9.00 (0.354) component edge–to–edge spacing, and 2.00 (0.079) clearance between Vicor heat sinks. 3. V•I Chip land pattern shown for reference only, actual land pattern may differ. Dimensions from edges of land pattern to push–pin holes will be the same for all half size V•I Chip Products. 4. RoHS compliant per CST–0001 latest revision. 5. Unless otherwise specified: Dimensions are mm (inches) tolerances are: x.x (x.xx) = ±0.3 (0.01) x.xx (x.xxx) = ±0.13 (0.005) 6. Plated through holes for grounding clips (33855) shown for reference, Heatsink orientation and device pitch will dictate final grounding solution. (NO GROUNDING CLIPS) (WITH GROUNDING CLIPS) V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 9 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET 3.0 POWER, VOLTAGE, EFFICIENCY RELATIONSHIPS Because of the high frequency, fully resonant SAC topology, power dissipation and overall conversion efficiency of BCM converters can be estimated as shown below. Key relationships to be considered are the following: 1. Transfer Function a. No load condition VOUT = VIN • K Eq. 1 Figure 15 – Power transfer diagram P R OUT P NL INPUT POWER OUTPUT POWER Where K (transformer turns ratio) is constant for each part number b. Loaded condition VOUT = Vin • K – IOUT • ROUT Eq. 2 2. Dissipated Power The two main terms of power losses in the BCM module are: - No load power dissipation (PNL) defined as the power used to power up the module with an enabled power train at no load. - Resistive loss (ROUT) refers to the power loss across the BCM modeled as pure resistive impedance. ~ PDISSIPATED ~ PNL + PROUT Eq. 3 Therefore, with reference to the diagram shown in Figure 15 POUT = PIN – PDISSIPATED = PIN – PNL – PROUT Eq. 4 Notice that ROUT is temperature and input voltage dependent and PNL is temperature dependent (See Figure 15). The above relations can be combined to calculate the overall module efficiency: η= POUT PIN = PIN – PNL – PROUT PIN = VIN • IIN – PNL – (IOUT)2 • ROUT VIN • IIN =1– ( PNL + (IOUT)2 • ROUT VIN • IIN ) Eq. 5 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 10 of 16 4.0 OPERATING VOVLO+ VOVLO– 1 2 3 5 4 6 Figure 16 – Timing diagram v i c o r p o w e r. c o m C B VIN NL VUVLO+ VUVLO– PC 5V 3V 3V 5V 2.5 V C 500mS before retrial Vout G D A E F LL • K IOUT ISSP IOCP H TM 3 V @ 27°C V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 0.4 V Notes: A: TON1 B: TOVLO* C: Max recovery time D:TUVLO E: TON2 F: TOCP G: TPC–DIS H: TSSP** 1: Controller start 2: Controller turn off 3: PC release 4: PC pulled low 5: PC released on output SC 6: SC removed – Timing and voltage is not to scale – Error pulse width is load dependent *Min value switching off **From detection of error to power train shutdown BCM48BH120T120A00 - BCM48BH120M120A00 Page 11 of 16 Rev. 2.0 12/10 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET 5.0 USING THE CONTROL SIGNALS TM AND PC The PC control pin can be used to accomplish the following functions: • Delayed start: At start-up, PC pin will source a constant 100 uA current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start. • Synchronized start up: In a parallel module array, PC pins shall be connected in order to ensure synchronous start of all the units. While every controller has a calibrated 2.5 V reference on PC comparator, many factors might cause different timing in turning on the 100 uA current source on each module, i.e.: – Different VIN slew rate – Statistical component value distribution By connecting all PC pins, the charging transient will be shared and all the modules will be enabled synchronously. • Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each BCM PC provides a regulated 5 V, 2 mA voltage source. • Output disable: PC pin can be actively pulled down in order to disable module operations. Pull down impedance shall be lower than 1 kΩ and toggle rate lower than 1 Hz. • Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and PC voltage is re-enabled. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of PC signal. It is important to notice that PC doesn’t have current sink capability (only 150 kΩ typical pull down is present), therefore, in an array, PC line will not be capable of disabling all the modules if a fault occurs on one of them. The temperature monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by x100. (i.e. 3.0 V = 300 K = 27ºC). It is important to remember that V•I chips are multi-chip modules, whose temperature distribution greatly vary for each part number as well with input/output conditions, thermal management and environmental conditions. Therefore, TM cannot be used to thermally protect the system. • Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and TM voltage is re-enabled. 6.0 FUSE SELECTION V•I Chips are not internally fused in order to provide flexibility in configuring power systems. Input line fusing of V•I Chips is recommended at system level, in order to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: • Current rating (usually greater than maximum BCM current) • Maximum voltage rating (usually greater than the maximum possible input voltage) • Ambient temperature • Nominal melting I2t • Recommended fuse: 3.15 A Little Fuse Nano2 Fuse V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 12 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 7.0 CURRENT SHARING The SAC topology bases its performance on efficient transfer of energy through a transformer, without the need of closed loop control. For this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. This type of characteristic is close to the impedance characteristic of a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic). When connected in an array (with same K factor), the BCM module will inherently share the load current with parallel units, according to the equivalent impedance divider that the system implements from the power source to the point of load. It is important to notice that, when successfully started, BCMs are capable of bidirectional operations (reverse power transfer is enabled if the BCM input falls within its operating range and the BCM is otherwise enabled). In parallel arrays, because of the resistive behavior, circulating currents are never experienced, because of energy conservation law. General recommendations to achieve matched array impedances are (see also AN016 for further details): • to dedicate common copper planes within the PCB to deliver and return the current to the modules • to make the PCB layout as symmetric as possible • to apply same input/output filters (if present) to each unit Figure 17 – BCM Array V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 2.0 12/10 Page 13 of 16 BCM48BH120T120A00 - BCM48BH120M120A00 PRELIMINARY DATASHEET 8.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of SAC systems versus conventional PWM converters is that the transformers do not require large functional filters. The resonant LC tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current, and efficiently transfers charge through the isolation transformer. A small amount of capacitance, embedded in the input and output stages of the module, is sufficient for full functionality and is key to achieve power density. This paradigm shift requires system design to carefully evaluate external filters in order to: 1. Guarantee low source impedance: To take full advantage of the BCM dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the V•I Chip to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nH, the RC damper may be as high as 47 µF in series with 0.3 Ω. A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass. 2. Further reduce input and/or output voltage ripple without sacrificing dynamic response: Given the wide bandwidth of the BCM, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the BCM multiplied by its K factor. This is illustrated in Figures 11 and 12. 3. Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures: The V•I Chip input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energy that the input or output switches can tolerate if avalanched. Total load capacitance at the output of the BCM shall not exceed the specified maximum. Owing to the wide bandwidth and low output impedance of the BCM, low frequency bypass capacitance and significant energy storage may be more densely and efficiently provided by adding capacitance at the input of the BCM. At frequencies