DCM™ DC-DC Converter
DCM2322x50T1360y6z
®
C
S
US
C
NRTL
US
Isolated, Regulated DC Converter
Features & Benefits
Product Ratings
• Isolated, regulated DC-DC converter
• Up to 60W, 5.00A continuous
• 89.7% peak efficiency
• 241W/in3 power density
POUT = 60W
VOUT = 12.0V
(7.2 – 13.2V Trim)
IOUT = 5.00A
Product Description
• Wide input range 9 – 50VDC
• Safety Extra Low Voltage (SELV) 12.0V nominal output
• 3000VDC isolation
• ZVS high-frequency switching
Enables low-profile, high-density filtering
• Dual modes of operation:
Array mode
– Up to 8 units – 480W
– No power de-rating needed
– Sharing strategy permits dissimilar line voltages
across an array
Enhanced VOUT regulation mode
– Standalone 60W
VIN = 9 – 50V
The DCM2322 is a lower-power, isolated and regulated DC‑DC
converter that operates from an unregulated, wide‑range input
to generate an isolated 12.0VDC output. With its high‑frequency
zero‑voltage switching (ZVS) topology, the DCM2322 converter
consistently delivers high efficiency across the input line range.
Modular DCM converters and downstream DC‑DC products
support efficient power distribution, providing superior power
system performance and connectivity from a variety of unregulated
power sources to the point‑of‑load.
Leveraging the thermal and density benefits of Vicor ChiP
packaging technology, the DCM2322 offers flexible thermal
management options with very low top- and bottom‑side thermal
impedances. Thermally‑adept ChiP-based power components
enable customers to quickly and predictably achieve cost‑effective
power‑system solutions.
• Fully operational current limit
• OV, OC, UV, short circuit and thermal shut down
Typical Applications
Package Information
• Through-hole ChiP™ package
0.978 x 0.898 x 0.284in
[24.84 x 22.80 x 7.21mm]
• Rail Transportation
Weight: 14.4g
[0.51oz]
• Defense / Aerospace
• Industrial
• Process Control
Note: Product images may not highlight current product markings and cosmetic features.
DCM™ DC-DC Converter
Page 1 of 33
Rev 1.2
11/2022
DCM2322x50T1360y6z
Typical Applications
Rb
Cb1
Cb2
DCM1
TR
EN
EMI_GND
F1_1
L1_1
VIN
CY
+IN
C1_1
Rd_1
Lb_1
Rdm_1
FT
CY
RCOUT-EXT_1
CIN
Cd_1
L2_1
+OUT
–IN
C2_1
COUT-EXT_1
–OUT
C3
CY
CY
Rb
Rb
Cb1
Cb2
Cb1
Cb2
DCM2
TR
EN
F1_2
L1_2
CY
+IN
C1_2
Rd_2
RCOUT-EXT_2
–IN
C2_2
COUT-EXT_2
–OUT
CY
CY
≈≈
L2_2
+OUT
CIN
Cd_2
Lb_2
Rdm_2
FT
CY
Rb
Rb
Cb1
Cb2
Cb1
Cb2
≈≈
DCM4
TR
EN
F1_4
L1_4
CY
+IN
C1_4
Rd_4
L2_4
+OUT
RCOUT-EXT_4
CIN
Cd_4
Lb_4
Rdm_4
FT
CY
–IN
COUT-EXT_4
–OUT
C2_4
CY
CY
Rb
Cb1
Cb2
Note: CIN, Rb, Cb1 and Cb2 are required components for proper operation of the DCM. See required components table below.
DCM2322x50T1360y6z in an array of four units; applicable when DCM is operating in Array Mode
Required Components
CIN
TDK C5750X7T2E225M250KA, 2.2µF, 250V
Rb
Generic 1Ω, 1/4W
Cb1 , Cb2
DCM™ DC-DC Converter
Page 2 of 33
KEMET C1812C103KGRACTU, 10,000pF, 2000V
Rev 1.2
11/2022
C4
Load
DCM2322x50T1360y6z
Typical Applications (Cont.)
Rb
Cb1
Cb2
DCM1
TR
EN
EMI_GND
FT
F1_1
T1_1
+IN
VIN
Rd_1
C1_1
Rdm_1
CY
CY
+OUT
RCOUT-EXT_1
CIN
Cd_1
–IN
Lb_1
L2_1
C2_1
COUT-EXT_1
–OUT
CY
C3
C4
Load
CY
Rb
Rb
Cb2
Cb2
Cb1
Cb2
DCM2
TR
EN
Rdm_2
FT
CY
F1_2
CY
T1_2
Rd_2
C1_2
+IN
+OUT
–IN
–OUT
L2_2
RCOUT-EXT_2
CIN
Cd_2
Lb_2
C2_2
COUT-EXT_2
CY
CY
≈≈
Rb
Rb
Cb1
Cb2
Cb1
Cb2
≈≈
DCM8
TR
EN
Rdm_8
FT
CY
F1_8
CY
T1_8
+IN
Rd_8
C1_8
+OUT
Lb_8
L2_8
RCOUT-EXT_8
CIN
C2_8
COUT-EXT_8
Cd_8
–IN
–OUT
CY
CY
Rb
Cb1
Cb2
Note: CIN, Rb, Cb1 and Cb2 are required components for proper operation of the DCM. See required components table on page 2.
Parallel operation of DCMs with common-mode chokes installed on the input side to suppress common-mode noise;
applicable when DCM is operating in Array Mode
Rb
Cb1
Cb2
DCM
TR
EN
EMI_GND
FT
F1
VIN
CY
L1
CY
+IN
C1
Rd
RCOUT-EXT
COUT-EXT
–OUT
–IN
CY
CY
Rb
Cb1
Load 1
Lb
L2
+OUT
CIN
Cd
Rdm
C2
Non-isolated
Point-of-Load
Regulator
Cb2
Note: CIN, Rb and Cb are required components for proper operation of the DCM. See required components table on page 2
Single DCM2322x50T1360y6z to a non-isolated regulator and direct-to-load
DCM™ DC-DC Converter
Page 3 of 33
Rev 1.2
11/2022
Load 2
DCM2322x50T1360y6z
Pin Configuration
TOP VIEW
1
2
+IN A
A’ +OUT
B’ –OUT
TR B
EN C
C’ +OUT
FT D
–IN E
D’ –OUT
DCM ChiP™
Pin Descriptions
Pin Number
Signal Name
Type
Function
A1
+IN
INPUT POWER
B1
TR
INPUT
Enables and disables trim functionality; adjusts output voltage when trim active
C1
EN
INPUT
Dual function:
1. Enables either Array or Enhanced VOUT Regulation Mode
2. Enables and disables power supply
D1
FT
OUTPUT
E1
–IN
INPUT
POWER RETURN
Negative input power terminal
A’2, C’2
+OUT
OUTPUT POWER
Positive output power terminal
–OUT
OUTPUT
POWER RETURN
Negative output power terminal
B’2, D’2
DCM™ DC-DC Converter
Page 4 of 33
Positive input power terminal
Fault monitoring
Rev 1.2
11/2022
DCM2322x50T1360y6z
Part Ordering Information
Part Number
Temperature Grade
DCM2322T50T1360C60
C = –20 to 125°C
DCM2322T50T1360T60
T = –40 to 125°C
DCM2322T50T1360M60
M = –55 to 125°C
Option
Tray Size
60 = Array and Enhanced VOUT
Regulation Modes / Analog control
Interface Version
24 parts per tray
Storage and Handling Information
Note: For compressive loading refer to Application Note AN:036, “Recommendations for Maximum Compressive Force of Heat Sinks.”
For handling and assembly processing refer to Application Note AN:031, “Through-Hole ChiP™ Package Soldering Guidelines.”
Parameter
Comments
Storage Temperature Range
Operating Internal Temperature Range (TINT)
Peak Temperature Top Case
(Soldering) [a]
Specification
C-Grade
–20 to 125°C
T-Grade
–40 to 125°C
M-Grade
–65 to 125°C
C-Grade
–20 to 125°C
T-Grade
–40 to 125°C
M-Grade
–55 to 125°C
For further information, please contact factory applications
135°C
Nickel
Lead Finish
0.51 – 2.03µm
Palladium
0.02 – 0.15µm
Gold
0.003 – 0.051µm
Weight
14.4g [0.51oz]
MSL Rating
Not applicable to through-hole ChiP products
ESD Rating
[a]
N/A
Method per Human Body Model (HBM) Test ESDA / JEDEC JDS-001-2012
Class 1C
Charged Device Model (CDM) JESD22-C101E
Class 2
Product is not intended for reflow solder attach.
Safety, Reliability and Agency Approvals
Parameter
Dielectric Withstand Test
Comments
Min
Typ
3000
VDC
IN to CASE
1500
VDC
OUT to CASE
1500
VDC
10
MΩ
IN to OUT, IN to CASE, OUT to CASE at 500VDC, 1 minute
MTBF
MIL-HDBK-217 FN2 Parts Count 25°C Ground Benign, Stationary,
Indoors / Computer
3.84
Telcordia Issue 2, Method I Case 3, 25°C, 100% D.C., GB, GC
8.95
cURus, UL 60950-1
cTÜVus, EN 62368-1
UKCA, electrical equipment (safety) regulations
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
DCM™ DC-DC Converter
Page 5 of 33
Unit
IN to OUT
Insulation Resistance
Agency Approvals/Standards
Max
Rev 1.2
11/2022
MHrs
DCM2322x50T1360y6z
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Electrical specifications do not apply when operating beyond rated operating conditions.
Parameter
Comments
Min
Max
-0.5
65.0
V
-1
1
V/µs
TR to –IN
-0.3
3.5
V
EN to –IN
-0.3
3.5
V
-0.3
3.5
V
5
mA
Output Voltage (+OUT to –OUT)
-0.5
15.8
V
Dielectric Withstand (Input to Output)
3000
Input Voltage (+IN to –IN)
Input Voltage Slew Rate
FT to –IN
Basic insulation
Average Output Current
DCM™ DC-DC Converter
Page 6 of 33
VDC
9.0
Rev 1.2
11/2022
Unit
A
DCM2322x50T1360y6z
Common Electrical Specifications for Array and Enhanced VOUT Regulation Operation
Specifications apply over all line, trim and load conditions, internal temperature TINT = 25°C, unless otherwise noted. Boldface specifications apply over the
temperature range of –20°C < TINT < 125°C for C-Grade, –40°C < TINT < 125°C for T-Grade and –55°C < TINT < 125°C for M-Grade.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
9
30
50
V
Power Input Specifications
Input Voltage Range
Inrush Current (Peak)
VIN
Continuous operation
IINRP
With maximum COUT-EXT, full resistive load
6.0
A
Input Capacitance (Internal)
CIN-INT
Effective value at nominal input voltage
37.6
µF
Input Capacitance (Internal) ESR
RCIN-INT
At 1MHz
0.41
mΩ
Input Inductance (External)
LIN
1
Differential mode, with no further line bypassing
µH
No-Load Specifications
Nominal line, see Figure 4; C-Grade
Input Power – Disabled
PQ
0.7
Nominal line, see Figure 4; T- and M-Grades
0.6
Nominal line, see Figure 5; C-Grade
PNL
0.8
W
1.2
Worst case line, see Figure 4; T- and M-Grades
Input Power – Enabled with No Load
1.0
1.4
Worst case line, see Figure 4; C-Grade
3.6
4.2
3.0
3.5
4.8
Worst case line, see Figure 5; C-Grade
Nominal line, see Figure 5; T- and M-Grades
W
4.0
Worst case line, see Figure 5; T- and M-Grades
Power Output Specifications
Output Voltage Set Point
Rated Output Voltage Trim Range
VOUT-NOM
VIN = 30V, nominal trim, at 100% load, TINT = 25°C
11.94
12.0
12.06
V
VOUT-TRIMMING
Specifies the low, nominal and high trim conditions
• Array Mode: trim range over temp at full load
• Enhanced VOUT Regulation Mode: trim range over
temp, with >10% rated load
7.2
12.0
13.2
V
Rated Output Power
POUT
Continuous, VOUT ≥ 12.0V
60
W
Rated Output Current
IOUT
Continuous, VOUT ≤ 12.0V
5.00
A
Output Current Limit
IOUT-LIM
Of rated IOUT max; fully operational current limit, for
nominal trim and below
100
Current Limit Delay
tIOUT-LIM
The module will power limit in a fast transient event
Full load, nominal line, nominal trim
Efficiency
Output Voltage Ripple
DCM™ DC-DC Converter
Page 7 of 33
η
VOUT-PP
Full load, over line and temperature, nominal trim;
C-Grade
50% load, over rated line, temperature and trim;
C-Grade
Full load, over line and temperature, nominal trim;
T- and M-Grades
50% load, over rated line, temperature and trim;
T- and M-Grades
20MHz bandwidth. At nominal trim,
minimum COUT-EXT and at least 10% rated load
Rev 1.2
11/2022
120
1
85.2
150
%
ms
89.7
78.4
73.5
%
80.0
75.0
312
mV
DCM2322x50T1360y6z
Common Electrical Specifications for Array and Enhanced VOUT Regulation Operation (Cont.)
Specifications apply over all line, trim and load conditions, internal temperature TINT = 25°C, unless otherwise noted. Boldface specifications apply over the
temperature range of –20°C < TINT < 125°C for C-Grade, –40°C < TINT < 125°C for T-Grade and –55°C < TINT < 125°C for M-Grade.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Power Output Specifications (Cont.)
Output Capacitance (Internal)
COUT-INT
Effective value at nominal output voltage
Output Capacitance (Internal) ESR
RCOUT-INT
At 1MHz
Minimum Transient Load
ITRAN_MIN
Excludes component temperature coefficient for
load transients that remain >10% rated load
Excludes component temperature coefficient for
load transients down to ITRAN_MIN rated load,
with static trim
Excludes component temperature coefficient for
load transients down to ITRAN_MIN rated load,
with dynamic trimming
Minimum required load for proper operation of
DCM during load transient conditions
Output Capacitance ESR (External)
RCOUT-EXT
At 10kHz, excludes component tolerances
COUT-EXT
Output Capacitance (External)
COUT-EXT-TRANS
COUT-EXT-TRANS-TRIM
170
µF
0.172
mΩ
1000
10000
1000
10000
4400
10000
0
%
10
mΩ
Initialization Delay
tINIT
See state diagram
25
Output Turn-On Delay
tON
From rising edge EN, with VIN pre-applied;
see timing diagram
200
Output Turn-Off Delay
tOFF
From falling edge EN; see timing diagram
Soft Start Ramp Time
tSS
Output Voltage Threshold
for Max Rated Load Current
VOUT-FL-THRESH
Output Current at Start Up
IOUT-START
Monotonic Soft-Start
Threshold Voltage
Minimum Required
Disabled Duration
Minimum Required
Disabled Duration
for Predictable Restart
Voltage Deviation (Transient)
Settling Time
DCM™ DC-DC Converter
Page 8 of 33
VOUT-MONOTONIC
tOFF-MIN
tOFF-MONOTONIC
%VOUT-TRANS
tSETTLE
At full rated resistive load;
Typical spec is 1-up with minimum COUT-EXT;
Max spec is for arrays with max COUT-EXT
During start up, VOUT must achieve this threshold
before output can support full rated current
Max load current at start up while VOUT
is below VOUT-FL_THRESH
Output voltage rise becomes monotonic
with 10% of preload once it crosses VOUT-MONOTONIC
This refers to the minimum time a module needs
to be in the disabled state before it will attempt to
start via EN
This refers to the minimum time a module needs to
be in the disabled state before it is guaranteed to
exhibit monotonic soft-start and have predictable
start‑up timing
Minimum COUT_EXT (10 ↔ 90% load step),
excluding load line
Rev 1.2
11/2022
µF
250
40
ms
µs
600
µs
500
ms
6.0
V
0.50
A
6.0
V
2
ms
100
ms
20% of full load and ambient temperature
• Full load and over temperature
C-Grade; all other conditions
(does not include light‑load regulation)
T- and M-Grades; at nominal line, nominal trim, full
load and ambient temperature
T- and M-Grades; at nominal line, nominal trim and:
• Load >20% of full load and ambient temperature
• Full load and over temperature
T- and M-Grades; all other conditions
(does not include light‑load regulation)
The total output voltage set-point accuracy from
the calculated VOUT based on load, temp and trim;
C-Grade; Excludes:
• ΔVOUT-LL
• %VOUT-REGULATION
The total output voltage set-point accuracy from the
calculated VOUT based on load, temp and trim; T- and
M-Grades; Excludes:
• ΔVOUT-LL
• %VOUT-REGULATION
0 – 10% load, additional VOUT, relative to VOUT
accuracy; see Design Guidelines section
DCM™ DC-DC Converter
Rev 1.2
Page 11 of 33 11/2022
-0.5
0.5
-1.0
1.0
-1.7
1.7
-0.5
0.5
-1.0
1.0
-1.5
1.5
-2.3
2.3
%
%
-2.0
2.0
-0.18
1.26
V
DCM2322x50T1360y6z
Specified Operating Area
Maximum Output Power (W)
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Electrical specifications do not apply when operating beyond rated operating conditions.
70
60
50
40
30
20
10
0
0
20
40
Top only at
temperature
60
80
Temperature (°C)
100
120
140
Top, leads and
bottom at
temperature
Top and leads only
at temperature
Figure 1 — Thermal specified operating area: max output power vs. case temperature, single unit at minimum full-load efficiency
14
14
Output Voltage (V)
Output Voltage (V)
16
12
10
8
7
0
1
2
3
4
Average Output Current (A)
Low Trim
Nom Trim
5
12
11
10
9
8
7
6
High Trim
Figure 2 — Electrical specified operating area: Array Mode
13
0
1
2
3
4
Average Output Current (A)
Low Trim
Nom Trim
5
6
High Trim
Figure 3 — Electrical specified operating area; Enhanced VOUT
Regulation Mode
DCM™ DC-DC Converter
Rev 1.2
Page 12 of 33 11/2022
DCM2322x50T1360y6z
High-Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
VIN
VIN > VIN-INIT
EN = False
tMIN-OFF delay
NON LATCHED
FAULT
tOFF
ult
Fa oved
m
Re
Powertrain: Stopped
FT = True
tINIT delay
Powertrain: Stopped
FT = True
EN = False
tOFF-MIN delay
STANDBY
Powertrain: Stopped
FT = True
EN = True and
No Faults
tON delay
EN = False
tOFF delay
or
LO
V
O VLO
ut
Inp put U
In
SOFT START
VOUT Ramp Up
tss delay
Powertrain: Active
FT = Unknown
REGULATION
MODE
SELECTION
tSS
Expiry
Latched
Ou
(based on EN voltage)
tpu
tO
VP
Only applies
after initialization
sequence
Powertrain: Stopped
FT = True
Fault Removed
Regulates VOUT
Powertrain: Active
FT = False
P
Output OV
or
mp
r-te
P
Ove put UV
Out
REINITIALIZATION
SEQUENCE
tINIT delay
RUNNING
Ov
e
Ou r-tem
tpu
p
t U or
VP
VIN ≥ VIN-UVLO+ and
not Over-temp
TR mode latched
Input OVLO or
Input UVLO
INITIALIZATION
SEQUENCE
NON LATCHED
FAULT
tFAULT
Powertrain: Stopped
FT = True
LATCHED
FAULT
EN = False
DCM™ DC-DC Converter
Rev 1.2
Page 13 of 33 11/2022
Powertrain: Stopped
FT = True
DCM™ DC-DC Converter
Rev 1.2
Page 14 of 33 11/2022
Output
Input
FT
ILOAD
IOUT
FULL LOAD
VOUT
VOUT-UVP
VOUT-NOM
FULL LOAD
TR
VTRIM-DIS-TH
EN
VREG-EN-TH
VARRAY-EN-TH
VIN
VIN-UVLO+/VIN-INIT
VIN-OVLO+/-
tINIT
tON
1
Input Power On
- Trim Inactive
tSS
tOFF
tMIN_OFF
4
EN
Latched
2
3
5
Ramp to TR
EN
Full Load Ignored
Low
tSS
tON
6
EN
High
tOFF
7
Input
OVLO
tSS
tOFF
8
Input
UVLO
tSS
tOFF
9
Input
returned
to zero
DCM2322x50T1360y6z
Timing Diagrams – Array Mode
Module inputs are shown in blue; module outputs are shown in brown.
DCM™ DC-DC Converter
Rev 1.2
Page 15 of 33 11/2022
Output
Input
FT
ILOAD
FULL LOAD
IOUT
VOUT
VOUT-UVP
VOUT-NOM
FULL LOAD
TR
VTR = nom
VTRIM-EN-TH
EN
VARRAY-EN-TH
VIN
VIN-UVLO+/VIN-INIT
VIN-OVLO+/-
tINIT
tON
10
Input Power On
- Trim Active
tSS
VOUT-OVP
11
Vout
based on
VTR
tOFF
12
Load dump
and reverse
current
tINIT
tON
tSS
13
Vout OVP
(primary
sensed)
14
Latched
fault cleared
RLOAD
tIOUT-LIM
15
Current Limit
with Resistive
Load
tFAULT
16
Resistive
Load with
decresing R
tINIT
17
Overload induced
Output UVP
tON
tSS
DCM2322x50T1360y6z
Timing Diagrams – Array Mode (Cont.)
Module inputs are shown in blue; module outputs are shown in brown.
DCM™ DC-DC Converter
Rev 1.2
Page 16 of 33 11/2022
Output
Input
FT
ILOAD
IOUT
FULL LOAD
VOUT
VOUT-UVP
VOUT-NOM
FULL LOAD
TR
VTR-DIS
EN
VREG-EN
VARRAY-EN
VIN
VIN-UVLO+/VIN-INIT
VIN-OVLO+/-
tINIT
tON
1
Input Power On
- Trim Inactive
tSS
2
3
Ramp to TR
Full Load Ignored
tOFF
tMIN_OFF
5
EN
Low
4
EN
Latched
tSS
tON
6
EN
High
tOFF
7
Input
OVLO
tSS
tOFF
8
Input
UVLO
tSS
tOFF
9
Input
returned
to zero
DCM2322x50T1360y6z
Timing Diagrams – Enhanced VOUT Regulation Mode
Module inputs are shown in blue; module outputs are shown in brown.
DCM™ DC-DC Converter
Rev 1.2
Page 17 of 33 11/2022
Output
Input
FT
ILOAD
FULL LOAD
IOUT
VOUT
VOUT-UVP
VOUT-NOM
FULL LOAD
TR
VTR = nom
VTRIM-EN-TH
EN
VIN
VIN-UVLO+/VIN-INIT
VIN-OVLO+/-
tINIT
tON
10
Input Power On
- Trim Active
tSS
OUT-OVP
11
Vout
based on
VTR
tOFF
12
Load dump
and reverse
current
tINIT
tON
tSS
13
Vout OVP
(primary
sensed)
14
Latched
fault cleared
RLOAD
tIOUT-LIM
15
Current Limit
with Resistive
Load
tFAULT
16
Resistive
Load with
decresing R
tINIT
17
Overload induced
Output UVP
tON
tSS
DCM2322x50T1360y6z
Timing Diagrams – Enhanced VOUT Regulation Mode (Cont.)
Module inputs are shown in blue; module outputs are shown in brown.
DCM2322x50T1360y6z
Common Typical Performance Characteristics for Array and Enhanced VOUT Regulation Operation
0.75
2.6
0.70
2.4
Power Dissipation (W)
Power Dissipation (W)
The following figures present typical performance at TC = 25°C, unless otherwise noted. See associated figures for general trend data.
0.65
0.60
0.55
0.50
0.45
0.40
0
10
20
30
40
Input Voltage (V)
-40°C
25°C
50
Efficiency (%)
Efficiency (%)
86
85
84
83
30
40
Input Voltage (V)
-40°C
25°C
50
60
90°C
Efficiency (%)
89.0
88.5
88.0
87.5
87.0
86.5
10
20
30
40
Input Voltage (V)
-40°C
25°C
20
30
40
Input Voltage (V)
25°C
50
60
90°C
89.5
89.0
88.5
88.0
87.5
87.0
86.5
86.0
85.5
0
10
20
30
40
Input Voltage (V)
25°C
50
90°C
Figure 7 — Full-load efficiency vs. VIN, at nominal trim
89.5
0
10
-40°C
Figure 6 — Full-load efficiency vs. VIN, at low trim
86.0
0
Figure 5 — No-load power dissipation vs. VIN, at nominal trim
87
20
1.6
-40°C
88
10
1.8
90°C
89
0
2.0
1.4
60
Figure 4 — Disabled power dissipation vs. VIN
82
2.2
50
60
90°C
Figure 8 — Full-load efficiency vs. VIN, at high trim
DCM™ DC-DC Converter
Rev 1.2
Page 18 of 33 11/2022
60
DCM2322x50T1360y6z
Common Typical Performance Characteristics for Array and Enhanced VOUT Regulation Operation (Cont.)
The following figures present typical performance at TC = 25°C, unless otherwise noted. See associated figures for general trend data.
95
9
Power Dissipation (W)
Efficiency (%)
90
85
80
75
70
65
60
55
1
2
3
4
Load Current (A)
9V Input
30V Input
5
6
5
4
6
0
50V Input
1
2
3
4
Load Current (A)
9V Input
Figure 9 — Efficiency vs. load at TCASE = -40°C, nominal trim
30V Input
5
6
50V Input
Figure 10 — Power dissipation vs. load at TCASE = -40°C,
nominal trim
9
Power Dissipation (W)
95
90
Efficiency (%)
7
3
0
85
80
75
70
65
60
8
7
6
5
4
3
0
1
2
3
4
Load Current (A)
9V Input
30V Input
5
6
0
50V Input
1
2
3
4
Load Current (A)
9V Input
Figure 11 — Efficiency vs. load at TCASE = 25°C, nominal trim
30V Input
5
6
50V Input
Figure 12 — Power dissipation vs. load at TCASE = 25°C,
nominal trim
10
Power Dissipation (W)
95
90
Efficiency (%)
8
85
80
75
70
65
60
9
8
7
6
5
4
3
2
0
1
9V Input
2
3
4
Load Current (A)
30V Input
5
6
0
50V Input
Figure 13 — Efficiency vs. load at TCASE = 90°C, nominal trim
1
9V Input
2
3
4
Load Current (A)
30V Input
5
50V Input
Figure 14 — Power dissipation vs. load at TCASE = 90°C,
nominal trim
DCM™ DC-DC Converter
Rev 1.2
Page 19 of 33 11/2022
6
DCM2322x50T1360y6z
Common Typical Performance Characteristics for Array and Enhanced VOUT Regulation Operation (Cont.)
The following figures present typical performance at TC = 25°C, unless otherwise noted. See associated figures for general trend data.
Switching Frequency (kHz)
Switching Frequency (kHz)
700
600
500
400
300
200
100
0
10
20
40
60
80
100
Load (%)
9V Input
30V Input
700
600
500
400
300
200
100
0
10
20
40
Low Trim
50V Input
Figure 15 — Nominal powertrain switching frequency vs. load
at nominal trim
60
Load (%)
Nom Trim
80
100
High Trim
Figure 16 — Nominal powertrain switching frequency vs. load
at nominal VIN
Input Capacitance (µF)
40
35
30
25
20
15
10
5
0
0
20
40
60
80
Input Voltage (V)
Figure 17 — Effective internal input capacitance vs. applied voltage
Figure 18 — Output voltage ripple, VIN = 30V, VOUT = 12.0V,
COUT_EXT = 1000µF, RLOAD = 2.400Ω
Figure 19 — Start up from EN, VIN = 30V, COUT_EXT = 10000µF,
RLOAD = 2.400Ω
DCM™ DC-DC Converter
Rev 1.2
Page 20 of 33 11/2022
DCM2322x50T1360y6z
Typical Performance Characteristics: Array Operation Only
16
16
14
14
Output Voltage (V)
Output Voltage (V)
The following figures present typical performance at TC = 25°C, unless otherwise noted. See associated figures for general trend data.
12
10
8
6
4
0
1
Min Trim
Low Trim
2
3
4
Output Current (A)
Nom Trim
High Trim
5
12
10
8
6
4
6
Max Trim
60
40
20
0
20
40
60
Case Temperature (°C)
Min Trim
Low Trim
Nom Trim
High Trim
80
100
Max Trim
Figure 20 — Ideal VOUT vs. load current, at 25°C case
Figure 21 — Ideal VOUT vs. case temperature, at full load
Figure 22 — 100 – 10% load transient response, VIN = 30V,
nominal trim, COUT_EXT = 1000µF
Figure 23 — 10 – 100% load transient response, VIN = 30V,
nominal trim, COUT_EXT = 1000µF
DCM™ DC-DC Converter
Rev 1.2
Page 21 of 33 11/2022
DCM2322x50T1360y6z
Typical Performance Characteristics: Enhanced VOUT Regulation Operation Only
The following figures present typical performance at TC = 25°C, unless otherwise noted. See associated figures for general trend data.
16
Output Voltage (V)
14
12
10
8
6
4
2
0
0
1
2
3
4
5
6
Output Current (A)
Min Trim
Low Trim
High Trim
Nom Trim
Max Trim
Figure 24 — Ideal VOUT vs. load current, at 25°C case, operating in
Enhanced VOUT Regulation Mode
DCM™ DC-DC Converter
Rev 1.2
Page 22 of 33 11/2022
DCM2322x50T1360y6z
Pin Functions
Selecting Array Mode or Enhanced VOUT Regulation Mode
Input power pins. –IN is the reference for all control pins,
and therefore a Kelvin connection for the control signals is
recommended as close as possible to the pin on the package, to
reduce effects of voltage drop due to –IN currents.
The EN pin can also be used to select Array mode operation or
Enhanced VOUT Regulation Mode operation. The DCM mode of
operation is dependent on the voltage seen by the DCM at its EN
pin at first start up following application of VIN. The DCM will latch
in selected mode of operation at the end of soft start and persist in
that same mode until loss of input voltage.
+OUT, –OUT
At the first start up after application of VIN, if EN is
allowed to float to:
+IN, –IN
Output power pins.
n
A value above VENABLE-EN-TH but below VREG-EN-TH, the DCM will
implement Enhanced VOUT Regulation Mode.
EN (Enable)
The EN pin provides two functionalities:
n
Enables and disables the DCM converter.
n
Selects Array mode or Enhanced VOUT Regulation Mode.
The EN pin is referenced to the –IN pin of the converter. It has an
internal pull-up to VCC through a 10kΩ resistor.
EN is an input only, it does not pull low in the event of a fault.
Enable/Disable Control
n
Output disable: when EN is pulled down externally below the
disable threshold (VENABLE-DIS-TH), the DCM converter will
be disabled.
n
Output enable: when EN is allowed to pull up above the enable
threshold (VENABLE-EN-TH) through the internal pull-up to VCC, the
DCM converter will be enabled.
n
A value above VARRAY-EN-TH and up to VCC, the DCM will
implement array mode operation.
Note that the selected mode of operation is not changed when
a DCM recovers from any fault condition, or after a disable
event through EN. The operation mode is reset only with cycling
of input power.
TR (Trim)
The TR pin is used to select the trim mode and to trim the output
voltage of the DCM converter. The TR pin has an internal pull-up to
VCC through a 10.0kΩ resistor.
The DCM will latch trim behavior at application of VIN (once VIN
exceeds VIN-UVLO+) and persist in that same behavior until loss
of input voltage
n
At application of VIN, if TR is sampled at above VTRIM-DIS-TH, the
module will latch in a non-trim mode, and will ignore the TR
input for as long as VIN is present.
Array Mode
n
At application of VIN, if TR is sampled at below VTRIM-EN-TH, the
TR will serve as an input to control the real time output voltage,
relative to full load, 25°C. It will persist in this behavior until VIN is
no longer present.
Enhanced VOUT Regulation Mode
If trim is active when the DCM is operating, the TR pin provides
dynamic trim control at a typical 30Hz of –3dB bandwidth over the
output voltage. TR also decreases the current limit threshold when
trimming above VOUT-NOM.
VCC
VARRAY-EN-TH
VREG-EN-TH
VENABLE-EN-TH
FT (Fault)
The FT pin provides a Fault signal.
VENABLE-DIS-TH
Disable
Figure 25 — EN pin voltage thresholds
Any time the module is enabled and has not recognized a fault,
the FT pin is inactive. FT has an internal 499kΩ pull-up to VCC,
therefore a shunt resistor, RSHUNT, of approximately 50kΩ can be
used to ensure the LED is completely off when there is no fault, per
the diagram below.
Whenever the powertrain stops (due to a fault protection or
disabling the module by pulling EN low), the FT pin becomes active
and provides current to drive an external circuit.
When active, FT pin drives to VCC, with up to 4mA of external
loading. Module may be damaged from an overcurrent FT drive,
thus a resistor in series for current limiting is recommended.
The FT pin becomes active momentarily when the
module starts up.
DCM™ DC-DC Converter
Rev 1.2
Page 23 of 33 11/2022
DCM2322x50T1360y6z
Typical External Circuits for Signal Pins (TR, EN, FT)
DCM
VCC
10kΩ
10kΩ
Output Voltage
Reference, Current
Limit Reference and
Soft Start control
Soft Start and
Fault Monitoring
TR
EN
RTRIM
499kΩ
Fault
Monitoring
FT
RSERIES
SW
RSHUNT
D
Kelvin –IN connection
Design Guidelines
Nominal Output Voltage Load Line
Building Blocks and System Design
DCM in Array Mode
The DCM converter input accepts the full 9 – 50V range, and it
generates an isolated trimmable 12.0VDC output. Multiple DCMs
may be paralleled for higher power capacity via wireless load
sharing, even when they are operating off of different input
voltage supplies.
Throughout this document, the programmed output voltage
(either the specified nominal output voltage if trim is inactive or
the trimmed output voltage if trim is active), is specified at full
load and at room temperature. The actual output voltage of the
DCM is given by the programmed trimmed output voltage, with
modification based on load and temperature. The nominal output
voltage is 12.0V, and the actual output voltage will match this at
full load and room temperature with trim inactive.
The DCM converter provides a regulated output voltage around
defined nominal load line and temperature coefficients. The load
line and temperature coefficients enable configuration of an array
of DCM converters which manage the output load with no share
bus among modules. Downstream regulators may be used to
provide tighter voltage regulation, if required.
The DCM2322x50T1360y6z may be used in standalone
applications where the output power requirements are up to 60W.
However, it is easily deployed as arrays of modules to increase
power handling capacity. Arrays of up to eight units have been
qualified for 480W capacity. Application of DCM converters in an
array requires no de‑rating of the maximum available power versus
what is specified for a single module.
Note: For more information on operation of single DCM, refer to “Single
DCM as an Isolated, Regulated DC-DC Converter” application note AN:029.
The largest modification to the actual output voltage compared
to the programmed output is due to the 5.263% VOUT-NOM load
line, which for this model corresponds to ΔVOUT-LOAD of 0.6316V.
As the load is reduced, the internal error amplifier reference,
and by extension the output voltage, rises in response. This load
line is the primary enabler of the wireless current sharing among
an array of DCMs.
The load line impact on the output voltage is absolute, and does
not scale with programmed trim voltage.
For a given programmed output voltage, the actual output voltage
versus load current at nominal trim and room temperature is given
by the following equation:
VOUT at 25°C = 12.0 + 0.6316 • (1 – IOUT / 5.00)
Soft Start
When the DCM starts, it will go through a soft start. The soft-start
routine ramps the output voltage by modulating the internal error
amplifier reference. This causes the output voltage to approximate
a piecewise linear ramp. The output ramp finishes when the
voltage reaches either the nominal output voltage, or the trimmed
output voltage in cases where trim mode is active.
DCM in Enhanced VOUT Regulation Mode
In Enhanced VOUT Regulation Mode, output voltage is not a
function of load line.
During soft start, the maximum load current capability is reduced.
Until VOUT achieves at least VOUT-FL-THRESH, the output current must
be less than IOUT-START in order to guarantee start up. Note that
this is current available to the load, above that which is required to
charge the output capacitor.
DCM™ DC-DC Converter
Rev 1.2
Page 24 of 33 11/2022
(1)
DCM2322x50T1360y6z
Nominal Output Voltage Temperature Coefficient
Overall Output Voltage Transfer Function
DCM in Array Mode
DCM in Array Mode
A second additive term to the programmed output voltage is based
on the temperature of the module. This term permits improved
thermal balancing among modules in an array, especially when
the factory nominal trim point is utilized (trim mode inactive).
This term is much smaller than the load line described above,
representing only a -1.60mV/°C change. Regulation coefficient is
relative to 25°C.
Taking load line (Equation 1), temperature coefficient
(Equation 2) and trim (Equation 3) into account, the general
equation relating the DC VOUT to programmed trim (when active),
load and temperature is given by:
For nominal trim and full load, the output voltage relates to the
temperature according to the following equation:
VOUT-FL = 12.0 -1.600 • 0.001 • (TINT – 25)
(2)
where TINT is in °C.
VOUT = 5.25 + (9.118 • VTR / VCC)
+ 0.6316 • (1 – IOUT / 5.00)
-1.600 • 0.001 • (TINT – 25) + ΔVOUT-LL (4)
DCM in Enhanced VOUT Regulation Mode
In Enhanced VOUT Regulation Mode, only trim (Equation 3)
is applicable. The general equation relating the DC VOUT to
programmed trim is given by:
The impact of temperature coefficient on the output voltage is
absolute and does not scale with trim or load.
DCM in Enhanced VOUT Regulation Mode
In Enhanced VOUT Regulation Mode, output voltage is not a
function of temperature coefficient.
Trim Mode and Output Trim Control
DCM in Array and Enhanced VOUT Regulation Modes
When the input voltage is initially applied to a DCM, and after
tINIT elapses, the trim pin voltage V TR is sampled. The TR pin has
an internal pull‑up resistor to VCC, so unless external circuitry pulls
the pin voltage lower, it will pull up to VCC. If the initially sampled
trim pin voltage is higher than V TRIM-DIS, then the DCM will disable
trimming as long as the VIN remains applied. In this case, for all
subsequent operation the output voltage will be programmed to
the nominal. This minimizes the support components required
for applications that only require the nominal rated VOUT, and
also provides the best output set‑point accuracy, as there are no
additional errors from external trim components.
If at initial application of VIN, the TR pin voltage is prevented from
exceeding V TRIM-EN, then the DCM will activate trim mode, and it
will remain active for as long as VIN is applied.
VOUT set point under full load and room temperature can be
calculated using the equation below:
VOUT-FL at 25°C = 5.25 + (9.118 • VTR / VCC) (3)
Note that the trim mode is not changed when a DCM recovers
from any fault condition or being disabled.
Module performance is guaranteed through output voltage trim
range VOUT-TRIMMING. If VOUT is trimmed above this range, then
certain combinations of line and load transient conditions may
trigger the output OVP.
VOUT = 5.25 + (9.118 • VTR / VCC) + ΔVOUT-LL (5)
Finally, note that when the load current is below 10% of the
rated capacity, there is an additional ΔV which may add to the
output voltage, depending on the line voltage which is related to
light‑load boosting. Please see the section on light‑load boosting
below for details.
Use 0V for ΔVOUT-LL when load is above 10% of rated load. See
section on light‑load boosting operation for light‑load effects on
output voltage.
Output Current Limit
The DCM features a fully operational current limit which effectively
keeps the module operating inside the Safe Operating Area (SOA)
for all valid trim and load profiles. The current limit approximates
a “brick wall” limit, where the output current is prevented from
exceeding the current limit threshold by reducing the output
voltage via the internal error amplifier reference. The current limit
threshold at nominal trim and below is typically 120% of rated
output current, but it can vary between 100% to 150%. In order
to preserve the SOA, when the converter is trimmed above the
nominal output voltage, the current limit threshold is automatically
reduced to limit the available output power.
When the output current exceeds the current limit threshold,
current limit action is held off by 1ms, which permits the DCM to
momentarily deliver higher peak output currents to the load. Peak
output power during this time is still constrained by the internal
Power Limit of the module. The fast Power Limit and relatively slow
Current Limit work together to keep the module inside the SOA.
Delaying entry into current limit also permits the DCM to minimize
droop voltage for load steps.
Sustained operation in current limit is permitted, and no de‑rating
of output power is required, even in an array configuration.
Some applications may benefit from well‑matched current
distribution, in which case fine tuning sharing via the trim pins
permits control over sharing. The DCM does not require this
for proper operation, due to the power limit and current limit
behaviors described here.
Current limit can reduce the output voltage to as little as the
UVP threshold (VOUT-UVP). Below this minimum output voltage
compliance level, further loading will cause the module to shut
down due to the output undervoltage fault protection.
DCM™ DC-DC Converter
Rev 1.2
Page 25 of 33 11/2022
DCM2322x50T1360y6z
Line Impedance, Input Slew Rate and Input
Stability Requirements
Fault Handling
Connect a high-quality, low-noise power supply to the +IN and –IN
terminals. Additional capacitance may have to be added between
+IN and –IN to make up for impedances in the interconnect cables
as well as deficiencies in the source.
The converter’s input voltage is monitored to detect an input
undervoltage condition. If the converter is not already running,
then it will ignore enable commands until the input voltage is
greater than VIN‑UVLO+. If the converter is running and the input
voltage falls below VIN‑UVLO–, the converter recognizes a fault
condition, the powertrain stops switching, and the output voltage
of the unit falls.
Excessive source impedance can bring about system stability issues
for a regulated DC-DC converter, and must either be avoided or
compensated by filtering components. A 1000µF input capacitor
is the minimum recommended in case the source impedance is
insufficient to satisfy stability requirements.
Additional information can be found in the filter design
application note AN:023.
Please refer to this input filter design tool to ensure input stability.
Ensure that the input voltage slew rate is less than 1V/µs,
otherwise a pre‑charge circuit is required for the DCM input to
control the input voltage slew rate and prevent overstress to input
stage components.
Input Fuse Selection
The DCM is not internally fused in order to provide flexibility in
configuring power systems. Input line fusing is recommended at
the system level, in order to provide thermal protection in case of
catastrophic failure. The fuse shall be selected by closely matching
system requirements with the following characteristics:
n
Current rating
(usually greater than the DCM converter’s maximum current)
n
Maximum voltage rating
(usually greater than the maximum possible input voltage)
n
Ambient temperature
n
Breaking capacity per application requirements
n
Nominal melting I2t
n
Recommended fuse:
See Safety Approvals for recommended fuse
Input Undervoltage Fault Protection (UVLO)
Input voltage transients which fall below UVLO for less than tUVLO
may not be detected by the fault proection logic, in which case
the converter will continue regular operation. No protection is
required in this case.
Once the UVLO fault is detected by the fault protection logic, the
converter shuts down and waits for the input voltage to rise above
VIN‑UVLO+. Provided the converter is still enabled, it will then restart.
Input Overvoltage Fault Protection (OVLO)
The converter’s input voltage is monitored to detect an input
overvoltage condition. When the input voltage is more than the
VIN‑OVLO+, a fault is detected, the powertrain stops switching, and
the output voltage of the converter falls.
After an OVLO fault occurs, the converter will wait for the input
voltage to fall below VIN‑OVLO–. Provided the converter is still
enabled, the powertrain will restart.
The powertrain controller itself also monitors the input voltage.
Transient OVLO events which have not yet been detected by the
fault sequence logic may first be detected by the controller if
the input slew rate is sufficiently large. In this case, powertrain
switching will immediately stop. If the input voltage falls back in
range before the fault sequence logic detects the out of range
condition, the powertrain will resume switching and the fault
logic will not interrupt operation. Regardless of whether the
powertrain is running at the time or not, if the input voltage does
not recover from OVLO before tOVLO, the converter fault logic will
detect the fault.
Output Undervoltage Fault Protection (UVP)
The converter determines that an output overload or short circuit
condition exists by measuring its primary sensed output voltage
and the output of the internal error amplifier. In general, whenever
the powertrain is switching and the primary-sensed output
voltage falls below VOUT‑UVP threshold, a short circuit fault will be
registered. Once an output undervoltage condition is detected,
the powertrain immediately stops switching, and the output
voltage of the converter falls. The converter remains disabled for
a time tFAULT. Once recovered and provided the converter is still
enabled, the powertrain will again enter the soft‑start sequence
after tINIT and tON.
DCM™ DC-DC Converter
Rev 1.2
Page 26 of 33 11/2022
DCM2322x50T1360y6z
Temperature Fault Protections (OTP)
External Output Capacitance
The fault logic monitors the internal temperature of the converter.
If the measured temperature exceeds TINT‑OTP, a temperature fault
is registered. As with the undervoltage fault protection, once
a temperature fault is registered, the powertrain immediately
stops switching, the output voltage of the converter falls, and
the converter remains disabled for at least time tFAULT. Then, the
converter waits for the internal temperature to return to below
TINT‑OTP before recovering. Provided the converter is still enabled,
the DCM will restart after tINIT and tON.
The DCM converter internal compensation requires a minimum
external output capacitor. An external capacitor in the range of
1000 – 10000µF with ESR of 10mΩ is required, per DCM for
control loop compensation purposes.
However some DCM models require an increase to the minimum
external output capacitor value in certain loading and trim
condition. In applications where the load can go below 10%
of rated load but the output trim is held constant, the range of
output capacitor required is given by COUT‑EXT‑TRANS in the Electrical
Specifications table. If the load can go below 10% of rated load
and the DCM output trim is also dynamically varied, the range
of output capacitor required is given by COUT‑EXT‑TRANS‑TRIM in the
Electrical Specifications table.
Output Overvoltage Fault Protection (OVP)
The converter monitors the output voltage during each switching
cycle by a corresponding voltage reflected to the primary side
control circuitry. If the primary sensed output voltage exceeds
VOUT‑OVP, the OVP fault protection is triggered. The control
logic disables the powertrain, and the output voltage of the
converter falls.
This type of fault is latched, and the converter will not start again
until the latch is cleared. Clearing the fault latch is achieved by
either disabling the converter via the EN pin, or else by removing
the input power such that the input voltage falls below VIN‑INIT.
Light-Load Boosting
Under light‑load conditions, the DCM converter may operate in
light‑load boosting depending on the line voltage. Light‑load
boosting occurs whenever the internal power consumption of the
converter combined with the external output load is less than the
minimum power transfer per switching cycle. In order to maintain
regulation, the error amplifier will switch the powertrain off and on
repeatedly, to effectively lower the average switching frequency,
and permit operation with no external load. During the time
when the powertrain is off, the module internal consumption is
significantly reduced, and so there is a notable reduction in no‑load
input power in light‑load boosting. When the load is less than 10%
of rated IOUT, the output voltage may rise by a maximum of 1.26V,
above the output voltage calculated from trim, temperature and
load line conditions.
DCM™ DC-DC Converter
Rev 1.2
Page 27 of 33 11/2022
DCM2322x50T1360y6z
Thermal Design
Based on the safe thermal operating area shown on page 6, the
full rated power of the DCM2322x50T1360y6z can be processed
provided that the top, bottom and leads are all held below
95°C. These curves highlight the benefits of dual sided thermal
management, but also demonstrate the flexibility of the Vicor
ChiP™ platform for customers who are limited to cooling only the
top or the bottom surface.
Where TINT represents the internal temperature and PD1, PD2, and
PD3 represent the heat flow through the top side, bottom side and
leads respectively.
The OTP sensor is located on the top side of the internal PCB
structure. Therefore in order to ensure effective overtemperature
fault protection, the case bottom temperature must be constrained
by the thermal solution such that it does not exceed the
temperature of the case top.
The ChiP package provides a high degree of flexibility in that it
presents three pathways to remove heat from internal power
dissipating components. Heat may be removed from the top
surface, the bottom surface and the leads. The extent to which
these three surfaces are cooled is a key component for determining
the maximum power that is available from a ChiP, as can be seen
from Figure 26.
Thermal Resistance Bottom
θINT-BOTTOM ºC / W
Thermal Resistance Bottom
θINT-BOTTOM ºC / W
Power Dissipation (W)
TCASE_BOTTOM(°C)
TLEADS(°C)
+
–
+
–
Figure 27 shows a scenario where there is no bottom-side cooling.
In this case, the heat flow path to the bottom is left open and the
equations now simplify to:
TINT – PD1 • θINT-TOP = TCASE_TOP
TINT – PD3 • θINT-LEADS = TLEADS
PDTOTAL = PD1+ PD3
Thermal Resistance Top
θINT-TOP ºC / W
Thermal Resistance Bottom
θINT-BOTTOM ºC / W
MAX INTERNAL TEMP
Thermal Resistance Leads
θINT-LEADS ºC / W
TCASE_BOTTOM(°C)
Power Dissipation (W)
TLEADS(°C)
TCASE_TOP(°C)
+
–
Figure 28 — One-side cooling thermal model
TCASE_TOP(°C)
+
–
PDTOTAL = PD1
Vicor provides a suite of online tools, including a simulator and
thermal estimator which greatly simplify the task of determining
whether or not a DCM thermal configuration is sufficient for a
given condition. These tools can be found at:
www.vicorpower.com/powerbench.
Alternatively, equations can be written around this circuit and
analyzed algebraically:
Symbol
Thermal Impedance
(°C/W)
θINT-TOP
6.7
to maximum-temperature internal
component from isothermal top
θINT-LEADS
14.9
to maximum-temperature internal
component from isothermal leads
θINT-BOTTOM
9.0
to maximum-temperature internal
component from isothermal bottom
TINT – PD1 • θINT-TOP = TCASE_TOP
TINT – PD2 • θINT-BOTTOM = TCASE_BOTTOM
PDTOTAL = PD1+ PD2+ PD3
TCASE_TOP(°C)
TINT – PD1 • θINT-TOP = TCASE_TOP
Figure 26 — Double-side cooling and leads thermal model
TINT – PD3 • θINT-LEADS = TLEADS
+
–
Figure 27 — One-side cooling and leads thermal model
Thermal Resistance Leads
θINT-LEADS ºC / W
+
–
TLEADS(°C)
Figure 28 shows a scenario where there is no bottom side and
leads cooling. In this case, the heat flow path to the bottom is left
open and the equations now simplify to:
MAX INTERNAL TEMP
Thermal Resistance Top
θINT-TOP ºC / W
Thermal Resistance Leads
θINT-LEADS ºC / W
TCASE_BOTTOM(°C)
Power Dissipation (W)
Since the ChiP has a maximum internal temperature rating, it is
necessary to estimate this internal temperature based on a real
thermal solution. Given that there are three pathways to remove
heat from the ChiP, it is helpful to simplify the thermal solution
into a roughly equivalent circuit where power dissipation is
modeled as a current source, isothermal surface temperatures are
represented as voltage sources and the thermal resistances are
represented as resistors. Figure 26 shows the “thermal circuit” for
a DCM2322 ChiP in an application where case top, case bottom
and leads are cooled. In this case, the DCM power dissipation is
PDTOTAL and the three surface temperatures are represented as
TCASE_TOP, TCASE_BOTTOM, and TLEADS. This thermal system can now
be very easily analyzed with simple resistors, voltage sources and a
current source.
This analysis provides an estimate of heat flow through the various
pathways as well as internal temperature.
MAX INTERNAL TEMP
Thermal Resistance Top
θINT-TOP ºC / W
Definition of Estimated
Thermal Resistance
Thermal Capacity
10.3Ws/°C
Table 1 — Thermal data
DCM™ DC-DC Converter
Rev 1.2
Page 28 of 33 11/2022
DCM2322x50T1360y6z
Array Operation
COUT-EXT-x:
electrolytic or tantalum capacitor with at least
10mΩ ESR, 1000µF ≤ COUT-EXT ≤ 10000µF;
additional ceramic /electrolytic capacitors, if needed
C3, C 4:
for output ripple filtering;
In order to help sensitive signal circuits reject potential noise,
additional components are recommended:
A decoupling network is needed to facilitate paralleling:
n
An output inductor should be added to each DCM, before the
outputs are bussed together to provide decoupling.
n
Each DCM needs a separate input filter, even if the multiple
DCMs share the same input voltage source. These filters limit
the ripple current reflected from each DCM, and also help
suppress generation of beat frequency currents that can result
when multiple powertrains input stages are permitted to
directly interact.
R2_x:
FB1_x, C5_x:
If signal pins (TR, EN, FT) are not used, they can be left floating,
and DCM will work in the nominal output condition.
301Ω, facilitate noise attenuation for TR pin;
FB1 is a ferrite bead with an impedance of at least
10Ω at 100MHz. C5_x can be a ceramic capacitor of
0.1µF. Facilitate noise attenuation for EN pin.
Note: Use an RCR filter network as suggested in the application
note AN:030 to reduce the noise on the signal pins.
When common‑mode noise in the input side is not a concern,
TR and EN can be driven and FT received using a single Kelvin
connection to the shared –IN as a reference.
Note: In case of the excessive line inductance, a properly
sized decoupling capacitor CDECOUPLE is required as shown in
Figure 29 and Figure 30.
Note: For more information on parallel operation of DCMs, refer to
“Parallel DCMs” application note AN:030.
When common‑mode noise rejection in the input side is needed,
common‑mode chokes can be added in the input side of each
DCM. An example of DCM paralleling circuit is shown in Figure 30.
An example of DCM paralleling circuit is shown in Figure 29.
Notice that each group of control pins need to be individually
driven and isolated from the other groups control pins. This is
because –IN of each DCM can be at a different voltage due to the
common mode chokes. Attempting to share control pin circuitry
could lead to incorrect behavior of the DCMs.
Filter components
Input filter: The choice of the input filter components varies up
on the low line and maximum output power of the
DCM. Refer to the Filtering Guidelines Introduction
section in the DCM Design Guide to design
an input filter.
Output filter:
Reference
Designator
Value
C2_x
80μF
L2_x
0.33μH
Mfg. Part Number & Count/DCM
GRM32EC72A106KE05L, #8
744309033, #1
Rdm_x
1.5Ω
Generic
Lb_x
72nH
IFLR2727EZER72NM01, #1
Rb
VTR
VEN
R2_1
EMI_GND
F1_1
VIN
CY
L1_1
C1_1
CDECOUPLE
Cb1
Cb2
DCM1
TR
EN
FB1_1
C5_1
CY
Rd_1
+IN
+OUT
–IN
–OUT
Rb
Rb
CY
C1_2
≈≈
FB1_8
C1_8
Rd_8
Cb2
Rdm_2
+IN
+OUT
–IN
–OUT
Lb_2
L2_2
RCOUT-EXT_2
C2_2
COUT-EXT_2
CY
≈
Rb
Cb1
Cb2
Cb1
Cb2
≈≈
DCM8
TR
EN
C5_8
Rdm_8
FT
R3
R4
D1
Cd_8
Shared –IN Kelvin
Cb1
CY
Rb
L1_8
Cb2
FT
R2_8
F1_8
Cb1
CIN
CY
Load
EN
Cd_2
CY
C4
TR
FB1_2
C5_2
Rd_2
≈≈
C3
DCM2
R2_2
L1_2
C2_1
COUT-EXT_1
CY
CY
F1_2
L2_1
RCOUT-EXT_1
CIN
Cd_1
Lb_1
Rdm_1
FT
CY
+IN
+OUT
–IN
–OUT
RCOUT-EXT_8
CIN
CY
Lb_8
L2_8
COUT-EXT_8
C2_8
CY
Rb
Cb1
Cb2
Note: CIN, Rb, Cb1 and Cb2 are required components for proper operation of the DCM. See required components table on page 2.
Figure 29 — DCM paralleling configuration circuit 1
DCM™ DC-DC Converter
Rev 1.2
Page 29 of 33 11/2022
DCM2322x50T1360y6z
Rb
F1_1
CY
T1_1
VIN
C1_1
Rd_1
TR
+
VTR1
+ FB1_1
C5_1
EN
VEN1
R3_1
_
R4_1
D1_1
_
Cd_1
Cb2
DCM1
R2_1
EMI_GND
Cb1
FT
CY
+IN
+OUT
–IN
–OUT
RCOUT-EXT_1
CIN
Rb
C1_2
Rd_2
VTR2
+ FB
1_2
C5_2
VEN2
_
_
Cb1
Cb2
Cb1
Cb2
TR
FT
R3_2
CY
+IN
+OUT
–IN
–OUT
Rb
+
VTR8
_
Cb2
Cb1
Cb2
≈≈
TR
EN
FB1_8
C5_8
VEN8
_
Cb1
DCM8
R2_8
+
Rd_8
Cd_8
C2_2
CY
Rb
C1_8
Lb_2
L1_2
COUT-EXT_2
CY
T1_8
Rdm_2
RCOUT-EXT_2
CIN
≈≈
F1_8
Load
EN
R4_2
D1_2
Cd_2
CY
C4
DCM2
R2_2
+
T1_2
C3
C2_1
COUT-EXT_1
CY
Rb
F1_2
Lb_1
L1_1
CY
CY
Rdm_1
FT
R3_8
R4_8
CY
+IN
+OUT
–IN
Lb_8
L1_8
RCOUT-EXT_8
CIN
D1_8
Rdm_8
COUT-EXT_8
–OUT
CY
C2_8
CY
Rb
Cb1
Cb2
Note: CIN, Rb, Cb1 and Cb2 are required components for proper operation of the DCM. See required components table on page 2.
Figure 30 — DCM paralleling configuration circuit 2
Maximum Power Dissipation (W)
Notice that each group of control pins needs to be individually
driven and isolated from the other groups control pins. This is
because –IN of each DCM can be at a different voltage due to the
common‑mode chokes. Attempting to share control pin circuitry
could lead to incorrect behavior of the DCMs.
An array of DCMs used at the full array-rated power may
generally have one or more DCMs operating at current limit, due
to sharing errors. Load sharing is functionally managed by the
load line. Thermal balancing is improved by the nominal effective
temperature coefficient of the output voltage set point.
DCMs in current limit will operate with higher output current or
power than the rated levels. Therefore the following Thermal Safe
Operating Area plot should be used for arrays or loads that drive
the DCM in to current limit for sustained operation.
14
12
10
8
6
4
2
0
0
20
Top only at
temperature
40
60
80
Temperature (°C)
Top and leads only
at temperature
100
120
Top, leads and
bottom at
temperature
Figure 31 — Thermal specified operating area: max power
dissipation vs. case temp for arrays or
current‑limited operation
DCM™ DC-DC Converter
Rev 1.2
Page 30 of 33 11/2022
DCM2322x50T1360y6z
DCM Module Product Outline Drawing Recommended PCB Footprint and Pinout
2322 THRU HOLE
(Reference DWG # 40292 Rev 5)
24.84±.38
.978±.015
11.43
.450
12.42
.489
0
1.52
.060
(2) PL.
11.40
.449
0
0
22.80±.13
.898±.005
1.02
.040
(3) PL.
0
1.52
.060
(4) PL.
TOP VIEW (COMPONENT SIDE)
.05 [.002]
SEATING
PLANE
7.21±.10
.284±.004
4.17
.164
(9) PL.
11.66
.459
0
11.66
.459
.41
.016
(9) PL.
8.25
.325
8.00
.315
2.75
.108
0
0
2.75
.108
1.38
.054
4.13
.162
1.38
.054
8.00
.315
0
8.25
.325
8.00±.08
.315±.003
4.13±.08
.162±.003
1.38±.08
.054±.003
0
2.03
.080
PLATED THRU
.25 [.010]
ANNULAR RING
(2) PL.
2.75±.08
.108±.003
-OUT
TR
0
EN
FT
8.00±.08
.315±.003
8.25±.08
.325±.003
+OUT
+IN
-IN
+OUT
2.75±.08
.108±.003
-OUT
8.25±.08
.325±.003
0
1.38±.08
.054±.003
0
11.66±.08
.459±.003
1.52
.060
PLATED THRU
.25 [.010]
ANNULAR RING
(3) PL.
11.66±.08
.459±.003
BOTTOM VIEW
RECOMMENDED HOLE PATTERN
(COMPONENT SIDE)
2.03
.080
PLATED THRU
.38 [.015]
ANNULAR RING
(4) PL.
NOTES:
1- UNLESS OTHERWISE SPECIFIED DIMENSIONS ARE MM [INCH]
2- TOLERANCES ARE:
DECIMALS
X.XX [X.XX] = ±0.25 [0.01]
X.XXX [X.XXX] = ±0.127 [0.005]
ANGLES = ±1°
DCM™ DC-DC Converter
Rev 1.2
Page 31 of 33 11/2022
DCM2322x50T1360y6z
Revision History
Revision
Date
1.0
08/27/19
Initial release
1.1
01/30/20
Output voltage regulation specification format change
11/04/22
Updated agency approvals
Corrected equation 1 notes
Revised array operation section
Added insulation resistance specification
Added C-grade part number and related specs
Updated format, pages added
1.2
Description
DCM™ DC-DC Converter
Rev 1.2
Page 32 of 33 11/2022
Page Number(s)
N/A
8
1, 5
24
29
5
5, 7, 8
ALL
DCM2322x50T1360y6z
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DCM™ DC-DC Converter
Rev 1.2
Page 33 of 33 11/2022
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