NBM™ Bus Converter
NBM6123x60E12A7yzz
®
C
S
US
C
NRTL
US
Non-Isolated, Fixed Ratio DC-DC Converter
Features & Benefits
Product Ratings
• Up to 170A continuous secondary current
• Up to 3000W/in3 power density
• 98% peak efficiency
• Parallel operation for multi-kW arrays
• OV, OC, UV, short circuit and thermal protection
• 6123 through-hole ChiP™ package
■■2.402 x 0.990 x 0.284in
(61.00 x 25.14 x 7.21mm)
• Bidirectional start up and steady state operation
Typical Applications
• DC Power Distribution
• High End Computing Systems
• Automated Test Equipment
• Industrial Systems
• High Density Power Supplies
• Communications Systems
• Transportation
VPRI = 54V (36 – 60V)
ISEC = up to 170A
VSEC = 10.8V (7.2 – 12.0V)
(no load)
K = 1/5
Product Description
The NBM6123x60E12A7yzz is a high efficiency Non Isolated Bus
Converter operating from a 36 – 60VDC primary bus to deliver a
non-isolated, ratiometric secondary voltage from 7.2 to 12.0VDC.
The NBM6123x60E12A7yzz offers low noise, fast transient
response, and industry leading efficiency and power density. In
addition, it provides an AC impedance beyond the bandwidth of
most downstream regulators, allowing input capacitance normally
located at the input of a PoL regulator to be located at the primary
side of the NBM. With a primary to secondary K factor of 1/5, that
capacitance value can be reduced by a factor of 25x, resulting in
savings of board area, material and total system cost.
Leveraging the thermal and density benefits of Vicor ChiP
packaging technology, the NBM offers flexible thermal
management options with very low top and bottom side thermal
impedances. Thermally-adept ChiP-based power components
enable customers to achieve low cost power system solutions
with previously unattainable system size, weight and efficiency
attributes quickly and predictably.
The NBM non-isolated topology allows start up and steady
state operation in forward and reverse directions and provides
bidirectional protections. However if the power train is disabled
by any protection and VSEC is present, then a voltage equal to VSEC
minus two diode drops will appear on the primary side.
NBM™ Bus Converter
Page 1 of 26
Rev 1.8
11/2017
NBM6123x60E12A7yzz
Typical Applications
NBM
TM
EN
enable/disable
switch
VAUX
FUSE
+VSEC
+VPRI
SGND
VPRI
PGND
PRIMARY
SECONDARY
CI_NBM_ELEC
POL
SOURCE_RTN
NBM6123x60E12A7yzz + Point of Load
NBM™ Bus Converter
Page 2 of 26
Rev 1.8
11/2017
NBM6123x60E12A7yzz
Pin Configuration
1
TOP VIEW
2
+VSEC
A
A’ +VSEC
PGND1
B
B’ PGND2
PGND1
C
C’ PGND2
+VSEC
D
D’ +VSEC
+VSEC
E
E’
+VSEC
PGND1
F
F’
PGND2
PGND1
G
G’ PGND2
+VSEC
H
H’ +VSEC
+VPRI
I
I’
TM
+VPRI
J
J’
EN
+VPRI
K
K’ VAUX
+VPRI
L
L’
SGND
6123 ChiP Package
Pin Descriptions
Pin Number
Signal Name
Type
I1, J1, K1, L1
+VPRI
PRIMARY POWER
I’2
TM
OUTPUT
J’2
EN
INPUT
K’2
VAUX
OUTPUT
L’2
SGND
SIGNAL RETURN
Signal return terminal only. Do not connect to PGND
A1, D1, E1, H1, A’2,
D’2, E’2, H’2
+VSEC
SECONDARY
POWER
Positive secondary auto-transformer power terminal
B1, C1, F1, G1
B’2, C’2, F’2, G’2
PGND [a]
POWER RETURN
[a]
Function
Positive primary auto-transformer power terminal
Temperature Monitor; Primary side referenced signals
Enables and disables power supply; Primary side referenced signals
Auxiliary Voltage Source; Primary side referenced signals
Common negative primary and secondary auto-transformer power return terminal
For proper operation an external low impedance connection must be made between listed -PGND1 and PGND2 terminals.
NBM™ Bus Converter
Page 3 of 26
Rev 1.8
11/2017
NBM6123x60E12A7yzz
Part Ordering Information
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade
Option
NBM
6123
x
60
E
12
A7
y
zz
61 = L
23 = W
T = TH
00 = Analog Ctrl
Non-isolated
Bus Converter
Module
S = SMT
60V
12V
No Load
36 – 60V
170A
T = –40°C – 125°C
01 = PMBus Ctrl
M = –55°C – 125°C
0R = Reversible Analog Ctrl
0P = Reversible PMBus Ctrl
All products shipped in JEDEC standard high profile (0.400” thick) trays (JEDEC Publication 95, Design Guide 4.10).
Standard Models
Product
Function
Package
Size
Package
Mounting
Max Primary
Input Voltage
Range
Identifier
Max
Secondary
Voltage
Secondary
Output
Current
Temperature
Grade
Option
NBM
6123
T
60
E
12
A7
T
0R
Absolute Maximum Ratings
The absolute maximum ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to the device.
Parameter
Comments
+VPRI_DC to –VPRI_DC
Min
Max
Unit
–1
80
V
1
V/µs
16
V
4.6
V
5.5
V
4.6
V
VPRI_DC or VSEC_DC Slew Rate
(Operational)
+VSEC_DC to –VSEC_DC
–1
TM to –VPRI_DC
EN to –VPRI_DC
–0.3
VAUX to –VPRI_DC
NBM™ Bus Converter
Page 4 of 26
Rev 1.8
11/2017
NBM6123x60E12A7yzz
Electrical Specifications
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
60
V
15
V
General Powertrain PRIMARY to SECONDARY Specification (Forward Direction)
Primary Input Voltage Range
(Continuous)
VPRI µController
PRI to SEC Input Quiescent Current
36
VPRI_DC
VµC_ACTIVE
IPRI_Q
VPRI_DC voltage where µC is initialized,
(i.e., VAUX = low, powertrain inactive)
Disabled, EN low, VPRI_DC = 54V
7
TINTERNAL ≤ 100ºC
12
VPRI_DC = 54V, TINTERNAL = 25ºC
PRI to SEC No Load
Power Dissipation
PRI to SEC Inrush Current Peak
PPRI_NL
IPRI_INR_PK
10
8
VPRI_DC = 54V
19
14
VPRI_DC = 36 – 60V
22
15
TINTERNAL ≤ 100ºC
DC Primary Input Current
Transformation Ratio
Secondary Output Current
(Continuous)
Secondary Output Current (Pulsed)
PRI to SEC Efficiency (Ambient)
IPRI_IN_DC
K
ηAMB
A
At ISEC_OUT_DC = 170A, TINTERNAL ≤ 100ºC
34.4
Primary to secondary, K = VSEC_DC / VPRI_DC, at no load
1/5
10ms pulse, 25% duty cycle,
ISEC_OUT_AVG ≤ 50% rated ISEC_OUT_DC
VPRI_DC = 54V, ISEC_OUT_DC = 170A
96.5
VPRI_DC = 36 – 60 V, ISEC_OUT_DC = 170A
95.6
VPRI_DC = 54V, ISEC_OUT_DC = 85A
97.3
98
96.5
97.1
170
A
200
A
97.5
%
ηHOT
VPRI_DC = 54V, ISEC_OUT_DC = 170A
PRI to SEC Efficiency
(Over Load Range)
η20%
34A < ISEC_OUT_DC < 170A
90
RSEC_COLD
VPRI_DC = 54V, ISEC_OUT_DC = 170A, TINTERNAL = –40°C
0.5
0.8
1.1
RSEC_AMB
VPRI_DC = 54V, ISEC_OUT_DC = 170A
0.8
1.3
1.8
RSEC_HOT
VPRI_DC = 54V, ISEC_OUT_DC = 170A, TINTERNAL = 100°C
1.1
1.55
2.0
FSW
Frequency of the output voltage ripple = 2x FSW
1.02
1.07
1.12
VSEC_OUT_PP
CSEC_EXT = 0μF, ISEC_OUT_DC = 170A, VPRI_DC = 54V,
20MHz BW
Switching Frequency
Secondary Output Voltage Ripple
Secondary Output Leads Inductance
(Parasitic)
NBM™ Bus Converter
Page 5 of 26
%
%
125
TINTERNAL ≤ 100ºC
Primary Input Leads Inductance
(Parasitic)
A
V/V
PRI to SEC Efficiency (Hot)
PRI to SEC Output Resistance
W
50
ISEC_OUT_DC
ISEC_OUT_PULSE
12
VPRI_DC = 36 – 60V, TINTERNAL = 25 ºC
VPRI_DC = 60V, CSEC_EXT = 3000μF,
RLOAD_SEC = 20% of full load current
mA
mΩ
MHz
mV
400
LPRI_IN_LEADS
Frequency 2.5MHz (double switching frequency),
simulated lead model
3
nH
LSEC_OUT_LEADS
Frequency 2.5MHz (double switching frequency),
simulated lead model
0.64
nH
Rev 1.8
11/2017
NBM6123x60E12A7yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
General Powertrain PRIMARY to SECONDARY Specification (Forward Direction) Cont.
Effective Primary Capacitance
(Internal)
CPRI_INT
Effective value at 54VPRI_DC
Effective Secondary Capacitance
(Internal)
CSEC_INT
Effective value at 10.8VSEC_DC
Rated Secondary Output
Capacitance (External)
CSEC_OUT_EXT
Excessive capacitance may drive module
into short circuit protection
Rated Secondary Output
Capacitance (External),
Parallel Array Operation
CSEC_OUT_AEXT
CSEC_OUT_AEXT Max = N • 0.5 • CSEC_OUT_EXT MAX, where
N = the number of units in parallel
16.80
µF
140
µF
3000
µF
1010
ms
Protection PRIMARY to SECONDARY (Forward Direction)
Auto Restart Time
tAUTO_RESTART
Start up into a persistent fault condition. Non-latching
fault detection given VPRI_DC > VPRI_UVLO+
940
Primary Overvoltage
Lockout Threshold
VPRI_OVLO+
63
66
69
V
Primary Overvoltage
Recovery Threshold
VPRI_OVLO–
60
63
66
V
Primary Overvoltage
Lockout Hysteresis
VPRI_OVLO_HYST
3
V
Primary Overvoltage
Lockout Response Time
tPRI_OVLO
30
µs
Primary Undervoltage
Lockout Threshold
VPRI_UVLO–
28
30
32
V
Primary Undervoltage
Recovery Threshold
VPRI_UVLO+
32
34
36
V
Primary Undervoltage
Lockout Hysteresis
VPRI_UVLO_HYST
4
V
tPRI_UVLO
100
µs
30
ms
1
ms
Primary Undervoltage
Lockout Response Time
From VPRI_DC = VPRI_UVLO+ to powertrain active, EN
Primary Undervoltage Start Up Delay tPRI_UVLO+_DELAY floating (i.e., one time start up delay from application
of VPRI_DC to VSEC_DC)
Primary Soft Start Time
tPRI_SOFT_START
Secondary Output Overcurrent
Trip Threshold
ISEC_OUT_OCP
Secondary Output Overcurrent
Response Time Constant
tSEC_OUT_OCP
Secondary Output Short Circuit
Protection Trip Threshold
ISEC_OUT_SCP
Secondary Output Short Circuit
Protection Response Time
tSEC_OUT_SCP
Overtemperature
Shutdown Threshold
tOTP+
Overtemperature
Recovery Threshold
tOTP–
Undertemperature
Shutdown Threshold
tUTP
Undertemperature Restart Time
NBM™ Bus Converter
Page 6 of 26
tUTP_RESTART
From powertrain active. Fast current limit protection
disabled during soft start
201
Effective internal RC filter
220
320
4
ms
250
A
1
Temperature sensor located inside controller IC
°C
110
Temperature sensor located inside controller IC;
protection not available for M-Grade units.
Start up into a persistent fault condition. Non-latching
fault detection given VPRI_DC > VPRI_UVLO+
Rev 1.8
11/2017
µs
125
105
A
3
115
°C
–45
°C
s
NBM6123x60E12A7yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
12.0
V
General Powertrain SECONDARY to PRIMARY Specification (Reverse Direction)
Secondary Input Voltage Range
(Continuous)
7.2
VSEC_DC
VSEC_DC = 10.8V, TINTERNAL = 25ºC
SEC to PRI No Load
Power Dissipation
PSEC_NL
DC Secondary Input Current
ISEC_IN_DC
Primary Output Current (Continuous)
IPRI_OUT_DC
Primary Output Current (Pulsed)
SEC to PRI Efficiency (Ambient)
IPRI_OUT_PULSE
ηAMB
10
8.0
VSEC_DC = 10.8V
12
19
VSEC_DC = 7.2 – 12.0V, TINTERNAL = 25ºC
14
VSEC_DC = 7.2 – 12.0V
22
At IPRI_DC = 34A, TINTERNAL ≤ 100ºC
172
A
34
A
40.8
A
10ms pulse, 25% duty cycle,
IPRI_OUT_AVG ≤ 50% rated IPRI_OUT_DC
VSEC_DC = 10.8V, IPRI_OUT_DC = 34A
96.1
97.1
VSEC_DC = 7.2 – 12.0V, IPRI_OUT_DC = 34A
94.9
VSEC_DC = 10.8V, IPRI_OUT_DC = 17A
97.3
98
96.3
97
%
SEC to PRI Efficiency (Hot)
ηHOT
VSEC_DC = 10.8V, IPRI_OUT_DC = 34A
SEC to PRI Efficiency
(Over Load Range)
η20%
6.80A < IPRI_OUT_DC < 34A
90
RPRI_COLD
VSEC_DC = 10.8V, IPRI_OUT_DC = 34A, TINTERNAL = –40°C
22
30
38
RPRI_AMB
VSEC_DC = 10.8V, IPRI_OUT_DC = 34A
28
42
56
RPRI_HOT
VSEC_DC = 10.8V, IPRI_OUT_DC = 34A, TINTERNAL = 100°C
36
45
54
SEC to PRI Output Resistance
Primary Output Voltage Ripple
VPRI_OUT_PP
CPRI_OUT_EXT = 0μF, IPRI_OUT_DC = 34A,
VSEC_DC = 10.8V, 20MHz BW
%
%
625
Rev 1.8
11/2017
mΩ
mV
1500
TINTERNAL ≤ 100ºC
NBM™ Bus Converter
Page 7 of 26
W
NBM6123x60E12A7yzz
Electrical Specifications (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
100
µF
Protection SECONDARY to PRIMARY (Reverse Direction)
Excessive capacitance may drive module into short
circuit protection when starting from
Secondary to Primary
Effective Primary Output Capacitance
(External)
CPRI_OUT_EXT
Secondary Overvoltage
Lockout Threshold
VSEC_OVLO+
12.8
13.2
13.6
V
Secondary Overvoltage
Recovery Threshold
VPRI_OVLO–
12
12.6
13.2
V
Secondary Overvoltage
Lockout Response Time
tPRI_OVLO
Secondary Undervoltage
Lockout Threshold
VSEC_UVLO–
5.6
6
6.4
V
Secondary Undervoltage
Recovery Threshold
VPRI_UVLO+–
6.4
6.8
7.2
V
Secondary Undervoltage
Lockout Response Time
tSEC_UVLO
30
100
Primary Output Overcurrent
Trip Threshold
IPRI_OUT_OCP
Powertrain is stopped but current can flow from
Secondary to Primary through MOSFET body diodes
Primary Output Overcurrent
Response Time Constant
tPRI_OUT_OCP
Effective internal RC filter
Primary Short Circuit Protection
Trip Threshold
IPRI_SCP
Primary Short Circuit Protection
Response Time
tPRI_SCP
NBM™ Bus Converter
Page 8 of 26
µs
Powertrain is stopped but current can flow from
Secondary to Primary through MOSFET body diodes
40
44
4
50
64
A
ms
A
1
Rev 1.8
11/2017
µs
µs
NBM6123x60E12A7yzz
200
180
Secondary
Output Current (A)
160
140
120
100
80
60
40
20
0
25
50
75
100
125
Case Temperature (°C)
Top only at temperature
Top and leads at
temperature
Leads at temperature
Top, leads, & belly at
temperature
2500
Secondary Output Current (A)
Secondary Output Power (W)
Figure 1 — Specified thermal operating area
2250
2000
1750
1500
1250
1000
750
500
250
0
36
38
40
42
44
46
48
50
52
54
56
58
60
220
200
180
160
140
120
100
80
60
40
20
0
36
38
40
Primary Input Voltage (V)
PSEC_OUT_DC
42
44
ISEC_OUT_DC
PSEC_OUT_PULSE
Secondary Output Capacitance
(% Rated CSEC_EXT_MAX)
Figure 2 — Specified electrical operating area using rated RSEC_HOT
110
100
90
80
70
60
50
40
30
20
10
0
0
20
40
60
80
Secondary Output Current (% ISEC_OUT_DC)
Figure 3 — Specified primary start up into load current and external capacitance
NBM™ Bus Converter
Page 9 of 26
46
48
50
52
54
Primary Input Voltage (V)
Rev 1.8
11/2017
100
ISEC_OUT_PULSE
56
58
60
NBM6123x60E12A7yzz
Signal Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Temperature Monitor
• The TM pin is a standard analog I/O configured as an output from an internal µC.
• The TM pin monitors the internal temperature of the controller IC within an accuracy of ±5°C.
• µC 250kHz PWM output internally pulled high to 3.3V.
SIGNAL TYPE
STATE
Start Up
ATTRIBUTE
Powertrain Active
to TM Time
TM Duty Cycle
TM Current
SYMBOL
CONDITIONS / NOTES
MIN
TYP
MAX
100
tTM
18.18
TMPWM
ITM
UNIT
µs
68.18
%
4
mA
Recommended External filtering
DIGITAL
OUTPUT
Regular
Operation
TM Capacitance (External)
CTM_EXT
Recommended External filtering
0.01
µF
TM Resistance (External)
RTM_EXT
Recommended External filtering
1
kΩ
10
mV / °C
1.27
V
Specifications using recommended filter
TM Gain
TM Voltage Reference
TM Voltage Ripple
ATM
VTM_AMB
VTM_PP
Internal temperature = 27ºC
RTM_EXT = 1kΩ, CTM_EXT = 0.01µF,
VPRI_DC = 54V, ISEC_DC = 170A
28
TINTERNAL ≤ 100ºC
mV
40
Enable / Disable Control
• The EN pin is a standard analog I/O configured as an input to an internal µC.
• It is internally pulled high to 3.3V.
• When held low, the NBM internal bias will be disabled and the powertrain will be inactive.
• In an array of NBMs, EN pins should be interconnected to synchronize start up.
• Unit must not be disabled if a load is present on +VPRI while in reverse operation.
SIGNAL TYPE
STATE
Start Up
ANALOG
INPUT
ATTRIBUTE
EN to Powertrain active
time
EN Voltage Threshold
Regular
Operation
EN Resistance (Internal)
EN Disable Threshold
SYMBOL
tEN_START
CONDITIONS / NOTES
TYP
MAX
10
Internal pull up resistor
VEN_DISABLE_TH
NBM™ Bus Converter
Rev 1.8
Page 10 of 26 11/2017
UNIT
ms
2.3
VEN_TH
REN_INT
MIN
VPRI_DC > VPRI_UVLO+, EN held low both
conditions satisfied for T > tPRI_UVLO+_DELAY
V
1.5
kΩ
1
V
NBM6123x60E12A7yzz
Signal Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Auxiliary Voltage Source
• The VAUX pin is a standard analog I/O configured as an output from an internal µC.
• VAUX is internally connected to µC output and internally pulled high to a 3.3V regulator with 2% tolerance, a 1% resistor of 1.5kΩ.
• VAUX can be used as a “Ready to process full power” flag. This pin transitions VAUX voltage after a 2ms delay from the start of powertrain activating,
signaling the end of softstart.
• VAUX can be used as “Fault flag”. This pin is pulled low internally when a fault protection is detected.
SIGNAL TYPE
ANALOG
OUTPUT
STATE
ATTRIBUTE
SYMBOL
Start Up
Powertrain active to VAUX
time
tVAUX
VAUX Voltage
VVAUX
VAUX Available Current
IVAUX
Regular
Operation
Fault
VAUX Voltage Ripple
VVAUX_PP
VAUX Capacitance
(External)
CVAUX_EXT
VAUX Resistance (External)
RVAUX_EXT
VAUX Fault Response Time
tVAUX_FR
CONDITIONS / NOTES
MIN
TYP
MAX
2
Powertrain active to VAUX High
2.8
ms
3.3
V
4
mA
50
100
TINTERNAL ≤ 100ºC
0.01
VPRI_DC < VµC_ACTIVE
From fault to VVAUX = 2.8V, CVAUX = 0pF
Signal Ground
• Signal ground is internally connect to PGND through a zero ohm resistor.
• Internal SGND traces are not designed to support high current.
NBM™ Bus Converter
Rev 1.8
Page 11 of 26 11/2017
1.5
UNIT
mV
µF
kΩ
10
µs
NBM™ Bus Converter
Rev 1.8
Page 12 of 26 11/2017
VAUX
TM
OUTPUT
OUTPUT
OUTPUT
EN
+VPRI
+VSEC
BIDIR
INPUT
VµC_ACTIVE
STARTUP
tVAUX
VPRI_UVLO-
VPRI_OVLO-
OVERVOLTAGE
tPRI_UVLO+_DELAY
VPRI_UVLO+
VPRI_OVLO+
VNOM
E
>
tPRI_UVLO+_DELAY
tAUTO-RESTART
tSEC_OUT_SCP
SHUTDOWN
E
AG
T
T
H
L
W G
EN
VO
LO HI
S
EV
T
D
D
T
RE
I
E
U FF
E
LL ULL
CU
NP N-O
UT
I
U
R
P
P
P
Y R
CI
IN
E
E
A R TU
C
BL ABL
RT
_D
M
I
A
O
I
R
VP
EN EN
PR
SH
RT
TA
ENABLE CONTROL
OVERCURRENT
AG
up
LT
ll O
u
N
O P
RV
N- AL
UT
VE
R
P
N
O
TU TER
UT
UT
E YO N
U T IN
Z
I
NP
P
R
L
I
O
X
N
A
I U
Y
IA D N
C
IT
R
AR
VA
_D
IN CON TU
RI &
M
I
P
V N
µc SE
PR
E
NBM6123x60E12A7yzz
NBM Forward Direction Timing Diagram
VAUX
TM
OUTPUT
OUTPUT
OUTPUT
EN
+VSEC
+VPRI
BIDIR
INPUT
NBM™ Bus Converter
Rev 1.8
Page 13 of 26 11/2017
tVAUX
STARTUP
VPRI = +VSEC – (~1.4V)
tPRI_UVLO+_DELAY
VSEC_UVLO+
VµC_ACTIVE
VSEC_UVLO-
VSEC_OVLO-
OVERVOLTAGE
VSEC_OVLO+
VNOM
>
tPRI_UVLO+_DELAY
GH
HI
NOT SUPPORTED CONDITION,
PERMANENT DAMAGE MAY OCCUR
OVERCURRENT
tAUTO-RESTART
W
tPRI_OUT_OCP
LO
SHUTDOWN
RED LINE: LOAD MUST NOT BE PRESENT
TO PREVENT DAMAGE TO UNIT
T
EN
T FF
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PU
AR E T
P
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LE LE
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ER OR
_D
AB NAB
CO OLT
V
EC
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H
N
S
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S V
E
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V
RT
TA
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ENABLE CONTROL
p
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AG
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T
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P
-O A L
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RV
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RN RN
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T TE
TP
OV
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µ PR T
SE
NBM6123x60E12A7yzz
NBM Reverse Direction Timing Diagram
NBM6123x60E12A7yzz
High Level Functional State Diagram
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application
of input voltage to VPRI_DC
VµC_ACTIVE < VPRI_DC < VPRI_UVLO+
STANDBY SEQUENCE
Application
of input voltage to VSEC_DC
VµC_ACTIVE <
VSEC_DC
K
< VPRI_UVLO+
VPRI_DC > VPRI_UVLO+
or VSEC_DC > VSEC_UVLO+
STARTUP SEQUENCE
TM Low
TM Low
EN High
EN High
VAUX Low
VAUX Low
Powertrain Stopped
Powertrain Stopped
ENABLE falling edge,
or OTP detected
Fault
Autorecovery
FAULT
SEQUENCE
TM Low
EN High
VAUX Low
tPRI_UVLO+_DELAY
expired
ONE TIME DELAY
INITIAL STARTUP
Input OVLO or UVLO,
Output OCP,
UTP, OVLO or UVLO, or
Input OCP detected
ENABLE falling edge,
or OTP detected
Input OVLO or UVLO,
Output OCP,
UTP, OVLO or UVLO, or
Input OCP detected
Powertrain Stopped
Short Circuit detected
SUSTAINED
OPERATION
TM PWM
EN High
VAUX High
Powertrain Active
Note: During reverse direction operation a load must not be present if the powertrain is in any stopped state while the supply voltage is present on +VSEC.
NBM™ Bus Converter
Rev 1.8
Page 14 of 26 11/2017
NBM6123x60E12A7yzz
Application Characteristics
PRI to SEC, Full Load Efficiency (%)
PRI to SEC, Power Dissipation (W)
Temperature controlled via top side cold plate, unless otherwise noted. All data presented in this section are collected from primary sourced units processing
power in forward direction. See associated figures for general trend data.
18
16
14
12
10
8
6
4
36
38
40
42
44
46
48
50
52
54
56
58
60
98.5
98.0
97.5
97.0
96.5
96.0
95.5
-40
-20
0
Primary Input Voltage (V)
TTOP SURFACE CASE:
- 40°C
25°C
90°C
VPRI:
99
98
97
96
95
94
93
92
91
90
89
88
17
34
51
68
85
102
119
136
153
170
0
54V
0
17
34
51
68
85
17
34
36V
PRI to SEC, Efficiency (%)
Figure 8 — Efficiency at TCASE = 25°C
100
54V
60V
51
68
85
102
119
136
153
170
36V
54V
153
170
60V
Figure 7 — Power dissipation at TCASE = –40°C
102
119
136
153
170
88
80
72
64
56
48
40
32
24
16
8
0
0
17
Secondary Output Current (A)
VPRI :
36V
VPRI :
60V
Figure 6 — Efficiency at TCASE = –40°C
99
98
97
96
95
94
93
92
91
90
89
88
80
Secondary Output Current (A)
PRI to SEC, Power Dissipation
36V
60
88
80
72
64
56
48
40
32
24
16
8
0
Secondary Output Current (A)
VPRI :
40
Figure 5 — Full load efficiency vs. temperature; VPRI_DC
PRI to SEC, Power Dissipation
PRI to SEC, Efficiency (%)
Figure 4 — No load power dissipation vs. VPRI_DC
0
20
Case Temperature (ºC)
54V
34
51
68
85
102
119
136
Secondary Output Current (A)
60V
VPRI :
36V
54V
Figure 9 — Power dissipation at TCASE = 25°C
NBM™ Bus Converter
Rev 1.8
Page 15 of 26 11/2017
60V
99
98
97
96
95
94
93
92
91
90
89
88
0
17
34
51
68
85
102
119
136
153
PRI to SEC, Power Dissipation
PRI to SEC, Efficiency (%)
NBM6123x60E12A7yzz
170
88
80
72
64
56
48
40
32
24
16
8
0
0
17
Secondary Output Current (A)
36V
54V
VPRI:
PRI to SEC, Output Resistance (mΩ)
Figure 10 — Efficiency at TCASE = 90°C
1.5
1.0
0.5
0.0
-20
0
20
40
60
80
100
Case Temperature (°C)
ISEC_OUT:
68
85
102
119
136
153
170
36V
54V
153
170
60V
Figure 11 — Power dissipation at TCASE = 90°C
2.0
-40
51
Secondary Output Current (A)
60V
Secondary Output Voltage Ripple (mV)
VPRI:
34
175
150
125
100
75
50
25
0
0
17
34
51
68
85
102
119
136
Secondary Output Current (A)
VPRI:
180A
Figure 12 — RSEC vs. temperature; Nominal VPRI_DC
ISEC_DC = 100A at TCASE = 90°C
200
384V
Figure 13 — VSEC_OUT_PP vs. ISEC_DC ; No external CSEC_OUT_EXT.
Board mounted module, scope setting:
20MHz analog BW
NBM™ Bus Converter
Rev 1.8
Page 16 of 26 11/2017
NBM6123x60E12A7yzz
Figure 14 — Full load secondary voltage ripple, 270µF CPRI_IN_EXT;
No external CSEC_IN_EXT. Board mounted module,
scope setting: 20MHz analog BW
Figure 15 — 0 – 170A transient response:
CPRI_IN_EXT = 270µF, no external CSEC_OUT_EXT
Figure 16 — 170 – 0A transient response:
CPRI_IN_EXT = 270µF, no external CSEC_OUT_EXT
Figure 17 — Start up from application of VPRI_DC = 54V,
20% ISEC_OUT_DC, 100% CSEC_OUT_EXT
Figure 18 — Start up from application of EN with pre-applied
VPRI_DC = 54V, 20% ISEC_OUT_DC, 100% CSEC_OUT_EXT
NBM™ Bus Converter
Rev 1.8
Page 17 of 26 11/2017
NBM6123x60E12A7yzz
General Characteristics
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
Mechanical
Length
L
60.87 [2.396]
61.00 [2.402]
61.13 [2.407]
mm [in]
Width
W
24.76 [0.975]
25.14 [0.990]
25.52 [1.005]
mm [in]
Height
H
7.11 [0.280]
7.21 [0.284]
7.31 [0.288]
mm [in]
Volume
Vol
Weight
W
Lead Finish
Without heatsink
cm3 [in3]
11.06 [0.675]
41 [1.45]
g [oz]
Nickel
0.51
2.03
Palladium
0.02
0.15
Gold
0.003
0.051
–40
125
µm
Thermal
Operating Temperature
TINTERNAL
NBM6123T60E12A7T0R (T-Grade)
Thermal Resistance Top Side
θINT-TOP
Estimated thermal resistance to maximum
temperature internal component from
isothermal top
1.28
°C/W
Estimated thermal resistance to
maximum temperature internal
component from isothermal leads
1.24
°C/W
Estimated thermal resistance to
maximum temperature internal
component from isothermal bottom
1.18
°C/W
34
Ws/°C
Thermal Resistance Leads
Thermal Resistance Bottom Side
θINT-LEADS
θINT-BOTTOM
Thermal Capacity
°C
Assembly
Storage Temperature
ESD Withstand
NBM6123T60E12A7T0R (T-Grade)
–40
ESDHBM
Human Body Model, “ESDA / JEDEC JDS-001-2012” Class I-C (1kV to < 2kV)
ESDCDM
Charge Device Model, “JESD 22-C101-E” Class II (200V to < 500V)
NBM™ Bus Converter
Rev 1.8
Page 18 of 26 11/2017
125
°C
NBM6123x60E12A7yzz
General Characteristics (Cont.)
Specifications apply over all line and load conditions, unless otherwise noted; boldface specifications apply over the temperature range of
–40°C ≤ TINTERNAL ≤ 125°C (T-Grade); all other specifications are at TINTERNAL = 25ºC unless otherwise noted.
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
135
°C
Soldering [b]
Peak Temperature Top Case
Safety
Isolation voltage / Dielectric Test
VHIPOT
PRIMARY to SECONDARY
N/A
PRIMARY to CASE
2250
SECONDARY to CASE
2250
N/A
Isolation Capacitance
CPRI_SEC
Unpowered Unit
Insulation Resistance
RPRI_SEC
At 500VDC
MTBF
V
N/A
0
MIL-HDBK-217Plus Parts Count - 25°C
Ground Benign, Stationary, Indoors /
Computer
3.34
MHrs
Telcordia Issue 2 - Method I Case III; 25°C
Ground Benign, Controlled
5.26
MHrs
cURus UL 60950-1
CE Marked for Low Voltage Directive and RoHS Recast Directive, as applicable
[b]
pF
MΩ
cTÜVus EN 60950-1
Agency Approvals / Standards
N/A
Product is not intended for reflow solder attach.
NBM™ Bus Converter
Rev 1.8
Page 19 of 26 11/2017
NBM6123x60E12A7yzz
NBM in a ChiP
CPRI_INT
CPRI_INT_ESR
0.5mΩ
16.80µF
0.53nH
LPRI_IN_LEADS = 3nH
ISEC
RSEC
1.25mΩ
LSEC_OUT_LEADS = 0.64nH
+VSEC
+VPRI
1.25mΩ
V•I
IPRI_Q
174mA
1/5 • ISEC
+
+
–
K
1/5 • VPRI
CSEC_INT_ESR
60.4µΩ
–
CSEC_INT
140µF
–PGND
Figure 19 — NBM AC model
The NBM uses a high frequency resonant tank to move energy
from primary to secondary and vice versa. The resonant LC tank,
operated at high frequency, is amplitude modulated as a function
of the primary voltage and the secondary current. A small amount
of capacitance embedded in the primary and secondary stages of
the module is sufficient for full functionality and is key to achieving
high power density.
The effective DC voltage transformer action provides additional
interesting attributes. Assuming that RSEC = 0Ω and IPRI_Q = 0A,
Eq. (3) now becomes Eq. (1) and is essentially load independent,
resistor R is now placed in series with VPRI.
The NBM6123x60E12A7yzz can be simplified into the model
shown in Figure 19.
R
Vin
V
PRI
At no load:
VSEC = VPRI • K
VSEC
In the presence of a load, VSEC is represented by:
VSEC = VPRI • K – ISEC • RSEC
(3)
The relationship between VPRI and VSEC becomes:
VSEC = (VPRI – IPRI • R) • K
IPRI – IPRI_Q
VSEC = VPRI • K – ISEC • R • K2
K
(4)
RSEC represents the impedance of the NBM, and is a function of
the RDS_ON of the primary and secondary MOSFETs and the winding
resistance of the power transformer. IPRI_Q represents the quiescent
current of the NBM controller, gate drive circuitry and core losses.
(5)
Substituting the simplified version of Eq. (4)
(IPRI_Q is assumed = 0A) into Eq. (5) yields:
and ISEC is represented by:
ISEC =
VSEC
Vout
Figure 20 — K = 1/5 NBM with series primary resistor
(2)
VPRI
NBM
SAC
1/5
KK==1/32
(1)
K represents the “turns ratio” of the NBM.
Rearranging Eq (1):
K=
+
–
(6)
This is similar in form to Eq. (3), where RSEC is used to represent the
characteristic impedance of the NBM. However, in this case a real
resistor, R, on the primary side of the NBM is effectively scaled by
K 2 with respect to the secondary.
Assuming that R = 1Ω, the effective R as seen from the secondary
side is 40mΩ, with K = 1/5.
NBM™ Bus Converter
Rev 1.8
Page 20 of 26 11/2017
NBM6123x60E12A7yzz
A similar exercise can be performed with the additon of a capacitor
or shunt impedance at the primary of the NBM. A switch in series
with VPRI is added to the circuit. This is depicted in Figure 21.
S
VVin
PRI
+
–
NBM
SAC
K = 1/5
K = 1/32
C
VVout
SEC
A solution for keeping the impedance of the NBM low involves
switching at a high frequency. This enables the use of small
magnetic components because magnetizing currents remain low.
Small magnetics mean small path lengths for turns. Use of low loss
core material at high frequencies also reduces core losses.
Figure 21 — NBM with primary capacitor
A change in VPRI with the switch closed would result in a change in
capacitor current according to the following equation:
IC (t) = C
dVPRI
(7)
dt
Low impedance is a key requirement for powering a high‑current,
low-voltage load efficiently. A switching regulation stage
should have minimal impedance while simultaneously providing
appropriate filtering for any switched current. The use of a NBM
between the regulation stage and the point of load provides a
dual benefit of scaling down series impedance leading back to
the source and scaling up shunt capacitance or energy storage
as a function of its K factor squared. However, these benefits are
not achieved if the series impedance of the NBM is too high. The
impedance of the NBM must be low, i.e., well beyond the crossover
frequency of the system.
The two main terms of power loss in the NBM are:
nn
No load power dissipation (PPRI_NL): defined as the power
used to power up the module with an enabled powertrain
at no load.
nn
Resistive loss (PRSEC): refers to the power loss across the NBM
modeled as pure resistive impedance.
Assume that with the capacitor charged to VPRI, the switch is
opened and the capacitor is discharged through the idealized
NBM. In this case,
(8)
IC = ISEC • K
Therefore,
PSEC_OUT = PPRI_IN – PDISSIPATED = PPRI_IN – PPRI_NL – PRSEC (11)
substituting Eq. (1) and (8) into Eq. (7) reveals:
ISEC(t) =
C
K2
•
dVSEC
dt
(10)
PDISSIPATED = PPRI_NL + PRSEC
(9)
The above relations can be combined to calculate the overall
module efficiency:
The equation in terms of the secondary has yielded a K 2 scaling
factor for C, specified in the denominator of the equation.
A K factor less than unity results in an effectively larger capacitance
on the secondary when expressed in terms of the primary. With
K = 1/5 as shown in Figure 21, C = 1µF would appear as
C = 25µF when viewed from the secondary.
η=
=
PSEC_OUT
PPRI_IN
PPRI_IN – PPRI_NL – PRSEC
PPRI_IN
VPRI • IPRI – PPRI_NL – (ISEC)2 • RSEC
= 1–
NBM™ Bus Converter
Rev 1.8
Page 21 of 26 11/2017
=
VPRI • IPRI
(
)
PPRI_NL + (ISEC)2 • RSEC
VPRI • IPRI
(12)
NBM6123x60E12A7yzz
Input and Output Filter Design
Thermal Considerations
A major advantage of NBM systems versus conventional PWM
converters is that the auto-transformer based NBM does not
require external filtering to function properly. The resonant LC
tank, operated at extreme high frequency, is amplitude modulated
as a function of primary voltage and secondary current and
efficiently transfers charge through the auto-transformer. A small
amount of capacitance embedded in the primary and secondary
stages of the module is sufficient for full functionality and is key to
achieving power density.
The ChiP module provides a high degree of flexibility in that it
presents three pathways to remove heat from the internal power
dissipating components. Heat may be removed from the top
surface, the bottom surface and the leads. The extent to which
these three surfaces are cooled is a key component in determining
the maximum curent that is available from a ChiP, as can be
seen from Figure 1.
This paradigm shift requires system design to carefully evaluate
external filters in order to:
nn
Guarantee low source impedance:
To take full advantage of the NBM’s dynamic response, the
impedance presented to its primary terminals must be low from
DC to approximately 5MHz. The connection of the bus converter
module to its power source should be implemented with
minimal distribution inductance. If the interconnect inductance
exceeds 100nH, the primary should be bypassed with a RC
damper to retain low source impedance and stable operation.
With an interconnect inductance of 200nH, the RC damper
may be as high as 1µF in series with 0.3Ω. A single electrolytic
or equivalent low-Q capacitor may be used in place of the
series RC bypass.
Since the ChiP has a maximum internal temperature rating, it
is necessary to estimate this internal temperature based on a
system-level thermal solution. Given that there are three pathways
to remove heat from the ChiP, it is helpful to simplify the thermal
solution into a roughly equivalent circuit where power dissipation
is modeled as a current source, isothermal surface temperatures
are represented as voltage sources and the thermal resistances are
represented as resistors. Figure 22 shows the “thermal circuit” for a
6123 ChiP NBM in an application where the top, bottom, and leads
are cooled. In this case, the NBM power dissipation is PDTOTAL and
the three surface temperatures are represented as TCASE_TOP,
TCASE_BOTTOM, and TLEADS. This thermal system can now be very
easily analyzed using a SPICE simulator with simple resistors,
voltage sources, and a current source. The results of the simulation
provide an estimate of heat flow through the various dissipation
pathways as well as internal temperature.
nn
Further reduce primary and/or secondary voltage ripple
without sacrificing dynamic response:
Thermal Resistance Top
Given the wide bandwidth of the module, the source response
is generally the limiting factor in the overall system response.
Anomalies in the response of the primary source will appear at
the secondary of the module multiplied by its K factor.
nn
Protect the module from overvoltage transients imposed
by the system that would exceed maximum ratings and
induce stresses:
The module primary/secondary voltage ranges shall not be
exceeded. An internal overvoltage lockout function prevents
operation outside of the normal operating primary range. Even
when disabled, the powertrain is exposed to the applied voltage
and the power MOSFETs must withstand it.
Total load capacitance of the NBM module shall not exceed the
specified maximum. Owing to the wide bandwidth and low
secondary impedance of the module, low-frequency bypass
capacitance and significant energy storage may be more densely
and efficiently provided by adding capacitance at the primary of
the module. At frequencies
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