PI3302-03-LGIZ

ZVS Regulators PI3302-03-LGIZ 11 – 36VIN, 5VOUT, 15A ZVS Buck Regulator Product Description Features & Benefits The PI3302-03 is a high-efficiency, wide-input-range DC-DC ZVS Buck Regulator integrating controller, power switches and support components all within a high-density System‑in‑Package (SiP). The integration of a high-performance Zero-Voltage Switching (ZVS) topology, within the PI3302-03 model, increases point‑of‑load performance providing best‑in‑class power efficiency. The PI3302‑03 requires only an external inductor and minimal capacitors to form a complete DC-DC switching‑mode Buck Regulator. • High-Efficiency ZVS Buck Topology Device PI3302-03-LGIZ Output Voltage Set Range 5.0V 3.3 – 6.5V • Wide input voltage range of 11 – 36V • Output power up to 75W • Very fast transient response • High-accuracy pre-trimmed output voltage • User-adjustable soft start & tracking • Parallel capable with single-wire current sharing • Input Over/Undevoltage Lockout (OVLO/UVLO) IOUT Max • Output Overvoltage Protection (OVP) 15A • Overtemperature Protection (OTP) The ZVS architecture also enables high-frequency operation while minimizing switching losses and maximizing efficiency. The high switching frequency operation reduces the size of the external filtering components, improves power density and enables very fast dynamic response to line and load transients. • Fast and slow current limits • –40 to 125°C operating range (TJ) Applications • High-efficiency systems • Computing, Communications, Industrial, Automotive Equipment • High-voltage battery operation Package Information • 10 x 14 x 2.6mm (LGA SiP) ZVS Regulators Page 1 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ Contents Order Information 3 Application Description 11 Thermal, Storage and Handling Information 3 Output Voltage Trim 11 Absolute Maximum Ratings 3 Soft Start Adjust and Tracking 12 Functional Block Diagram 4 Inductor Pairing 12 Pin Description 5 Thermal De-rating 13 Package Pinout 5 Filter Considerations 13 Electrical Characteristics 6 Layout Guidelines 14 10 Recommended PCB Footprint and Stencil 15 ENABLE (EN) 10 Package Drawings 16 Remote Sensing 10 Revision History 17 Switching Frequency Synchronization 10 Product Warranty 18 Soft Start 10 Output Voltage Trim 10 Output Current Limit Protection 10 Input Undervoltage Lockout 10 Input Overvoltage Lockout 10 Output Overvoltage Protection 11 Overtemperature Protection 11 Pulse Skip Mode (PSM) 11 Variable Frequency Operation 11 Parallel Operation 11 Functional Description ZVS Regulators Page 2 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ Order Information Part Number PI3302-03-LGIZ Output Range Set Range 5.0V 3.3 – 6.5V IOUT Max Operating Range (TINT ) Package 15A –40 to 125ºC 10 x 14mm 123-pin LGA Transport Media TRAY Thermal, Storage and Handling Information Name Rating Storage Temperature –65 to 150°C Internal Operating Temperature –40 to 125°C Soldering Temperature for 20 seconds 245°C MSL Rating 3 ESD Rating 2kV HBM Absolute Maximum Ratings Name Rating VIN –0.7 to 36V VS1 –0.7 to 36V, –4V for 5ns SGND 100mA PGD, SYNCO, SYNCI, EN, EAO, ADJ, TRK, ADR1, ADR2, SCL, SDA, REM –0.3 to 5.5V / 5mA VOUT –1.5 to 21V Notes: At 25°C ambient temperature. Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted. Test conditions are per the specifications within the individual product electrical characteristics. ZVS Regulators Page 3 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ Functional Block Diagram VIN VS1 VIN Q2 Q1 VOUT R4 REM Power Control R1 VCC SYNCO SYNCI PGD EN PGND Memory 0Ω ADR1 SDA Rev 1.6 07/2022 ADR0 SCL SGND ZVS Regulators Page 4 of 18 + Interface Simplified block diagram ADJ - ZVS Control EAO 1V R2 TRK VOUT PI3302-03-LGIZ Pin Description Name Location I/O Description Signal ground: Internal logic ground for EA, TRK, SYNCI, SYNCO, ADJ and I2C (options) communication returns. SGND and PGND are star connected within the regulator package. SGND Block 1 I/O PGND Block 2 Power Power ground: VIN and VOUT power returns. VIN Block 3 Power Input voltage: and sense for UVLO, OVLO and feed forward ramp. VOUT Block 5 Power Output voltage: and sense for power switches and feed-forward ramp. VS1 Block 4 Power Switching node: and ZVS sense for power switches. PGD A1 O Power Good: High impedance when regulator is operating and VOUT is in regulation. May also be used as “Parallel Good” – see applications section. EAO A2 O Error amp output: External connection for additional compensation and current sharing. EN A3 I/O Enable Input: Regulator enable control. Asserted high or left floating – regulator enabled; Asserted low, regulator output disabled. Polarity is programmable via I2C interface. REM A5 I Remote Sense: High side connection. Connect to output regulation point. ADJ B1 I Adjust input: An external resistor may be connected between ADJ pin and SGND or VOUT to trim the output voltage up or down. TRK C1 I/O Soft start and track input: An external capacitor may be connected between TRK pin and SGND to decrease the rate of rise during soft start. NC A4, K3 Open SYNCO K4 O Synchronization output: Outputs a low signal for ½ of the minimum period for synchronization of other converters. SYNCI K5 I Synchronization input: Synchronize to the falling edge of external clock frequency. SYNCI is a high impedance digital input node and should always be connected to SGND when not in use. SDA D1 I/O Data Line: I2C serial data line. SCL E1 I/O Clock Line: I2C serial clock line. ADR1 H1 I Tri-state Address: Supports I2C addressing. ADR0 G1 I Tri-state Address: Supports I2C addressing. No Connect: Leave pins floating. SYNCI 2 SYNCO 1 NC Package Pinout 3 4 5 6 7 SGND K Block 1 J PGND Block 2 8 9 10 11 12 13 14 VIN Block 3 ADR1 H Pin Block Name Group of pins SGND B2-4, C2-4, D2-3, E2-3, F1-3, G2-3, H2-3, J1-3, K1-2 PGND A8-10, B8-10, C8-10, D8-10, E4-10, F4-10, G4-10, H4-10, J4-10, K6-10 VIN G12-14, H12-14, J12-14, K12-14 VS1 A12-14, B12-14, C12-14, D12-14, E12-14 VOUT A6-7, B6-7, C6-7, D6-7 ADR0 G SGND F SCL E SDA D TRK C VS1 Block 4 ADJ B PGD A REM NC EN EAO ZVS Regulators Page 5 of 18 VOUT Block 5 Rev 1.6 07/2022 PI3302-03-LGIZ Electrical Characteristics Specifications apply for the conditions –40°C < TINT < 125°C, VIN = 24V, L1 = 185nH [a] unless other conditons are noted. Parameter Symbol Conditions Min Typ Max 24 36 Unit Input Specifications Input Voltage VIN_DC [g] Input Current IIN_DC VIN = 24V, TC = 25°C, IOUT = 15A Input Current At Output Short (fault condition duty cycle) IIN_Short 11 3.31 [b] 20 Disabled 2.0 Enabled (no load) 2.5 Input Quiescent Current IQ_VIN Input Voltage Slew Rate VIN_SR [b] VOUT_DC [b] V A mA mA 1 V/µs 5.08 V 6.5 V Output Specifications Output Voltage Total Regulation 4.92 [c][g] Output Voltage Trim Range 5.00 3.3 Line Regulation ∆VOUT (∆VIN) @ 25°C, 11V < VIN < 36V 0.10 % Load Regulation ∆VOUT (∆IOUT) @ 25°C, 0.5A < IOUT < 15A 0.10 % 44 mVP-P Output Voltage Ripple VOUT_AC IOUT = 7.5A, COUT = 5 x 47µF 20MHz BW Continuous Output Current Range IOUT_DC [e] [g] Current Limit IOUT_CL [d] 15 18 A A Protection VIN UVLO Start Threshold VUVLO_START 9.6 VIN UVLO Stop Threshold VUVLO_STOP 9.3 VIN UVLO Hysteresis VUVLO_HYS 10.4 10.87 V 9.9 10.6 V 0.50 V VIN OVLO Start Threshold VOVLO_START 36.1 37.6 V VIN OVLO Stop Threshold VOVLO_STOP 37.0 38.4 V VIN OVLO Hysteresis VOVLO_HYS 0.8 V VIN UVLO/OVLO Response Time tf Output Overvoltage Protection VOVP Above VOUT Overtemperature Fault Threshold TOTP [b] Overtemperature Restart Hysteresis 130 TOTP_HYS 500 ns 20 % 135 140 °C 30 °C 0.800 MHz 36 ms Timing Switching Frequency Fault Restart Delay fS [f] tFR_DLY Sync In (SYNCI) Synchronization Frequency Range ∆fSYNCI SYNCI Threshold VSYNCI Relative to set switching frequency [c] 50 110 2.5 [a] All % V parameters reflect regulator and inductor system performance. Measurements were made using a standard PI3302-03 evaluation board with 3x4” dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. [c] Output current capability may be limited and other performance may vary from electrical characteristics when switching frequency or V OUT is modified. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves. [g] V – V IN OUT must be 5V or more to avoid a minimum load requirement of 3mA. Regulator must be disabled if VIN – VOUT is less than 1V. ZVS Regulators Page 6 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ Electrical Characteristics (Cont.) Specifications apply for the conditions –40°C < TINT < 125°C, VIN = 24V, L1 = 185nH [a] unless other conditons are noted. Parameter Symbol Conditions Min Typ Max Unit Sync Out (SYNCO) SYNCO High VSYNCO_HI Source 1mA SYNCO Low VSYNCO_LO Sink 1mA 4.5 V SYNCO Rise Time tSYNCO_RT 20pF load 10 SYNCO Fall Time tSYNCO_FT 20pF load 10 0.5 V ns ns Soft Start and Tracking TRK Active Input Range VTRK 0 VTRK_OV 20 ITRK –70 TRK Max Output Voltage TRK Disable Threshold Charge Current (Soft Start) Discharge Current (Fault) Soft-Start Time 1.04 V 40 62 mV –50 –25 1.2 ITRK_DIS tSS CTRK = 0µF V µA 6.8 mA 2.2 ms Enable High Threshold VEN_HI 0.9 1 1.1 V Low Threshold VEN_LO 0.7 0.8 0.9 V Threshold Hysteresis VEN_HYS 100 200 300 mV Enable Pull-Up Voltage (floating, unfaulted) VEN_PU 2 V Enable Pull-Down Voltage (floating, faulted) VEN_PD 0 V Source Current IEN_SO –50 µA Sink Current IEN_SK 50 µA PGD VPG_HI% [b] 79 85 PGD Falling Threshold VPG_LO% [b] 77 83 PGD Output Low VPG_SAT Sink = 4mA [b] IPG_SAT [b] PGD Rising Threshold PGD Sink Current 4 [a] All 91 % VOUT_DC 89 % VOUT_DC 0.4 V mA parameters reflect regulator and inductor system performance. Measurements were made using a standard PI3302-03 evaluation board with 3x4” dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value. [b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control. [c] Output current capability may be limited and other performance may vary from electrical characteristics when switching frequency or V OUT is modified. [d] Refer to Output Ripple plots. [e] Refer to Load Current vs. Ambient Temperature curves. [f] Refer to Switching Frequency vs. Load current curves. [g] V – V IN OUT must be 5V or more to avoid a minimum load requirement of 3mA. Regulator must be disabled if VIN – VOUT is less than 1V. ZVS Regulators Page 7 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ PI3302-03 (5.0VOUT) Electrical Characteristics Efficiency (%) 95 90 85 80 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 IOUT (A) 12VIN 18VIN 24VIN 36VIN Switching Frequency (kHz) Figure 1 — Efficiency at 25°C Figure 4 — Transient response: 3.75 – 11.25A, at 5A/µs 900 800 700 600 500 400 300 200 100 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 24VIN 36VIN IOUT (A) 12VIN 18VIN Figure 2 — Switching frequency vs. load current Figure 5 — Transient response: 0 – 15A, at 5A/µs Figure 3 — Short circuit test ZVS Regulators Page 8 of 18 Rev 1.6 07/2022 PI3302-03-LGIZ PI3302-03 (5.0VOUT) Electrical Characteristics (Cont.) Output Load Current (A) 16 14 12 10 8 6 4 2 0 50 75 100 125 Ambient Temperature (°C) 12VIN Figure 6 — Output ripple: 24VIN, 5.0VOUT at 7.5A 18VIN 24VIN 36VIN Figure 9 — Load current vs. ambient temperature, 200LFM Output Load Current (A) 16 14 12 10 8 6 4 2 0 50 75 100 125 Ambient Temperature (°C) 12VIN Figure 7 — Output ripple: 24VIN, 5.0VOUT at 15A Output Load Current (A) 14 12 10 8 6 4 2 0 75 100 125 Ambient Temperature (°C) 12VIN 18VIN 24VIN 36VIN Figure 8 — Load current vs. ambient temperature, 0LFM ZVS Regulators Page 9 of 18 24VIN 36VIN Figure 10 — Load current vs. ambient temperature, 400LFM 16 50 18VIN Rev 1.6 07/2022 PI3302-03-LGIZ Functional Description The PI3302-03 is a highly integrated ZVS Buck regulator. The PI3302-03 has a set output voltage that can be trimmed within a prescribed range shown on page 1. Performance and maximum output current are characterized with a specific external power inductor (see Table 4). L1 VIN VIN CIN PGND PI33xx VS1 VOUT VOUT COUT REM SYNCI TRK ADJ EN EAO SGND SYNCO When using the internal oscillator, the SYNCO pin provides a 5V clock that can be used to sync other regulators. Therefore, one PI3302-03 can act as the lead regulator and have one additional PI3302-03 running in parallel and interleaved. Soft Start The PI3302-03 includes an internal soft-start capacitor to control the rate of rise of the output voltage. See “Electrical Characteristics” for the default value. Connecting an external capacitor from the TRK pin to SGND will increase the start-up ramp period. See, “Soft Start Adjustment and Track,” in the Applications Description section for more details. Output Voltage Trim The PI3302-03 output voltage can be trimmed up from the preset output by connecting a resistor from ADJ pin to SGND and can be trimmed down by connecting a resistor from ADJ pin to VOUT. The Table 1 defines the voltage range for the PI3302-03. Device PI3302-03-LGIZ Output Voltage Set Range 5.0V 3.3 – 6.5V Figure 11 — ZVS Buck with required components Table 1 — PI3302-03 output adjustment range For basic operation, Figure 11 shows the connections and components required. No additional design or settings are required. Output Current Limit Protection ENABLE (EN) EN is the enable pin of the converter. The EN Pin is referenced to SGND and permits the user to turn the regulator on or off. The EN default polarity is a positive logic assertion. If the EN pin is left floating or asserted high, the converter output is enabled. Pulling EN pin below 0.8VDC with respect to SGND will disable the regulator output. Remote Sensing An internal 100Ω resistor is connected between REM pin and VOUT pin to provide regulation when the REM connection is broken. Referring to Figure 11, it is important to note that L1 and COUT are the output filter and the local sense point for the power supply output. As such, the REM pin should be connected at COUT as the default local sense connection unless remote sensing to compensate additional distribution losses in the system. The REM pin should not be left floating. Switching Frequency Synchronization The SYNCI input allows the user to synchronize the controller switching frequency by an external clock referenced to SGND. The external clock can synchronize the unit between 50% and 110% of the preset switching frequency (fS). The PI3302-03 default for SYNCI is to sync with respect to the falling edge of the applied clock providing 180° phase shift from SYNCO. This allows for the paralleling of two PI3302-03 devices without the need for further user programming or external sync clock circuitry. PI3302-03 has two methods implemented to protect from output short or over current condition. Slow Current Limit protection: prevents the output load from sourcing current higher than the regulator’s maximum rated current. If the output current exceeds the Current Limit (IOUT_CL) for 1024µs, a slow current-limit fault is initiated and the regulator is shut down which eliminates output current flow. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. Fast Current Limit protection: PI3302-03 monitors the regulator inductor current pulse-by-pulse to prevent the output from supplying very high current due to sudden low impedance short. If the regulator senses a high inductor current pulse, it will initiate a fault and stop switching until Fault Restart Delay ends and then initiate a soft-start cycle. Input Undervoltage Lockout If VIN falls below the input Undervoltage Lockout (UVLO) threshold, but remains high enough to power the internal bias supply, the PI3302-03 will complete the current cycle and stop switching. The system will restart once the input voltage is reestablished and after the Fault Restart Delay. Input Overvoltage Lockout If VIN exceeds the input Overvoltage Lockout (OVLO) threshold (VOVLO), while the controller is running, the PI3302-03 will complete the current cycle and stop switching. The system will resume operation after the Fault Restart Delay. ZVS Regulators Rev 1.6 Page 10 of 18 07/2022 PI3302-03-LGIZ Output Overvoltage Protection Parallel Operation The PI3302-03 is equipped with output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds 20% of its set regulated value, the regulator will complete the current cycle, stop switching and issue an OVP fault. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay. Paralleling modules can be used to increase the output current capability of a single power rail and reduce output voltage ripple. Overtemperature Protection The internal package temperature is monitored to prevent internal components from reaching their thermal maximum. If the Overtemperature Protection Threshold (OTP) is exceeded (TOTP), the regulator will complete the current switching cycle, enter a low‑power mode, set a fault flag, and will soft start when the internal temperature falls below Overtemperature Restart Hysteresis (TOTP_HYS). Pulse Skip Mode (PSM) PI3302-03 features a PSM to achieve high efficiency at light loads. The regulators are setup to skip pulses if EAO falls below a PSM threshold. Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light‑load efficiency. The regulator will leave PSM once the EAO rises above the Skip Mode threshold. Variable Frequency Operation Each PI3302-03 is preprogrammed to a base operating frequency, with respect to the power stage inductor (see Table 3), to operate at peak efficiency across line and load variations. At low‑line and high‑load applications, the base frequency will decrease to accommodate these extreme operating ranges. By stretching the frequency, the ZVS operation is preserved throughout the total input line voltage range therefore maintaining optimum efficiency. VIN VS1 VIN CIN SYNCO(#2) R1 SYNCI(#2) EN(#2) PGND PGD SYNCI L1 VOUT PI33xx (#1) The PI3302-03 default for SYNCI is to sync with respect to the falling edge of the applied clock providing 180° phase shift from SYNCO. By connecting the EAO pins and SGND pins of each module together the units will share the current equally. When the TRK pins of each unit are connected together, the units will track each other during soft-start and all unit EN pins have to be released to allow the units to start (See Figure 12). Also, any fault event in any regulator will disable the other regulators. The two regulators will be out of phase with each other reducing output ripple (refer to Switching Frequency Synchronization). To provide synchronization between regulators over the entire operational frequency range, the Power Good (PGD) pin must be connected to the lead regulator’s (#1) SYNCI pin and a 2.5kΩ Resistor, R1, must be placed between SYNCO (#2) return and the lead regulator’s SYNCI (#1) pin, as shown in Figure 12. In this configuration, at system soft-start, the PGD pin pulls SYNCI low forcing the lead regulator to initialize the open-loop startup synchronization. Once the regulators reach regulation, SYNCI is released and the system is now synchronized in a closed-loop configuration which allows the system to adjust on the fly when any of the individual regulators begin to enter variable frequency mode in the loop. Application Description Output Voltage Trim With a single resistor connected from the ADJ pin to SGND or REM, a device’s output can be varied above or below the nominal set voltage. The remote pin (REM) should always be connected to the VOUT pin, if not used, to prevent an output voltage offset. Figure 13 shows the internal feedback voltage divider network. VOUT COUT REM VOUT SYNCO R4 EN EAO(#2) EAO TRK(#2) TRK REM SGND R1 L1 VIN PGND PGD SYNCO(#1) SYNCI(#1) EN(#1) SYNCI – + VS1 VIN CIN VOUT PI33xx (#2) COUT 1.0VDC REM ADJ RHIGH R2 SGND SYNCO EN EAO(#1) EAO TRK(#1) TRK SGND Figure 13 — Internal resistor divider network Figure 12 — PI3302-03 parallel operation ZVS Regulators Rev 1.6 Page 11 of 18 07/2022 RLOW PI3302-03-LGIZ R1, R2, and R4 are all internal 1.0% resistors and RLOW and RHIGH are external resistors which the designer can add to modify VOUT to a desired output. The internal resistor value for each regulator is listed below in Table 2. Conditions R1 R2 R4 PI3302-03-LGIZ 4.53kΩ 1.13kΩ 100Ω VOUT 1 VOUT 2 (a) Table 2 — PI3302-03 internal divider values Master VOUT VOUT 2 By choosing an output voltage value within the ranges stated in Table 1, VOUT can simply be adjusted up or down by selecting the proper RHIGH or RLOW value, respectively. The following equations can be used to calculate RHIGH and RLOW values: RHIGH = RLOW = 1 (VOUT – 1) – 1 R1 R2 1 1 ( ) – 1 R1 R2(VOUT – 1) (b) + (1) Figure 14 — PI3302-03 tracking methods (2) Soft Start Adjust and Tracking For Direct Tracking, choose the PI3302-03 or power supply with the highest output voltage as the parent and connect the parent output voltage to the TRK pin of the other PI3302-03 regulator(s) through a divider (Figure 15) with the same ratio as the child’s feedback divider (see Table 2 for values). The TRK pin offers a means to increase the regulator’s soft-start time or to track with additional regulators. The soft-start slope is controlled by an internal capacitor and a fixed charge current to provide a Soft-Start Time tSS for all PI3302-03 regulators. By adding an additional external capacitor to the TRK pin, the soft-start time can beincreased further. The following equation can be used to calculate the proper capacitor for a desired soft-start times: CTRK = (tTRK • ITRK ) – 100 • 10 –9 Master VOUT TRK (3) Slave Where tTRK is the soft-start time and ITRK is a 50µA internal charge current (see Electrical Characteristics for limits). There is typically either proportional or direct tracking implemented within a design. For proportional tracking between several regulators at start up, simply connect all PI3302-03 device TRK pins together. This type of tracking will force all connected regulators to startup and reach regulation at the same time (see Figure 14). R1 PI33xx R2 SGND Figure 15 — Voltage divider connections for direct tracking All connected PI3302-03 regulator soft-start slopes will track with this method. Direct tracking timing is demonstrated in Figure 14b. All tracking regulators should have their Enable (EN) pins connected together to work properly. Inductor Pairing The PI3302-03 utilizes an external inductor. This inductor has been optimized for maximum efficiency performance. Table 3 details the specific inductor value and part number utilized for the PI3302-03 device and is available from Eaton Corp. Device Inductor (nH) Inductor Part Number Manufacturer PI3302-03 185 FP1507R1-R185-R Eaton Corp. Table 3 — PI3302-03 inductor pairing ZVS Regulators Rev 1.6 Page 12 of 18 07/2022 PI3302-03-LGIZ Thermal De-rating Filter Considerations Thermal de-rating curves are provided that are based on component temperature changes versus load current, input voltage and air flow. It is recommended to use these curves as a guideline for proper thermal de-rating. These curves represent the entire system and are inclusive to both the Vicor regulator and the external inductor. Maximum thermal operation is limited by either the MOSFETs or inductor depending upon line and load conditions. The PI3302-03 requires low impedance ceramic X5R input capacitors to ensure proper start up and high‑frequency decoupling for the power stage. The PI3302-03 will draw nearly all of the high‑frequency current from the low‑impedance ceramic capacitors when the main high‑side MOSFET is conducting. During the time the high‑side MOSFET is off, they are replenished from the source. If the source impedance is high at the switching frequency of the converter, a bulk capacitor may be necessary. This value has been chosen to be 100µF so that the PI3302‑03 can start up into a full resistive load and supply the output capacitive load with the default minimum soft‑start capacitor when the input source impedance is 50Ω at 1MHz. If it is used, it should be decoupled from the ceramic capacitors using a 200nH inductor rated for the maximum input current. A parallel damping resistor of 1Ω is also recommended. Table 4 shows the recommended input and output capacitors to be used for the PI3302-03 as well as expected transient response, RMS ripple currents per capacitor, and input and output ripple voltages. Table 5 includes the recommended input and output ceramic capacitors. Thermal measurements were made using a standard PI3302‑03 Evaluation board which is 3x4 inches in area and uses 4-layer, 2oz copper. Thermal measurements were made on the three main power devices, the two internal MOSFETs and the external inductor, with air flows of 0, 200 and 400LFM. Device VIN (V) ILOAD (A) CINPUT Ceramic X5R CINPUT Bulk Elec. COUTPUT Ceramic X5R CINPUT Ripple Current (IRMS) COUTPUT Ripple Current (IRMS) Input Ripple (mVpp) Output Ripple (mVpp) PI3302-03 24 15 4 x 10µF 50V 100µF 50V 6 x 47µF 1.2 1.5 220 60 Transient Recovery Deviation Time (mVpk) (µs) ±170 Load Step (A) (Slew/µs) 30 Table 4 — Recommended input and output capacitance Part Number Description Part Number Description GRM188R71C105KA12D - Murata 1µF 16V 0603 X7R C3216X5R1H106K160AB - TDK 10µF 50V 1206 X7R GRM319R71H104KA01D - Murata 0.1µF 50V 1206 X7R GRM31CR61A476ME15L - Murata 47µF 10V 1206 X5R Table 5 — Recommended capacitor types ZVS Regulators Rev 1.6 Page 13 of 18 07/2022 7.5 (5A/µs) PI3302-03-LGIZ Layout Guidelines To optimize maximum efficiency and low‑noise performance from a PI3302-03 design, layout considerations are necessary. Reducing trace resistance and minimizing high‑current loop returns along with proper component placement will contribute to optimized performance. A typical buck converter circuit is shown in Figure 16. The potential areas of high parasitic inductance and resistance are the circuit return paths, shown as LR below. When Q1 is on and Q2 is off, the majority of CIN’s current is used to satisfy the output load and to recharge the COUT capacitors. When Q1 is off and Q2 is on, the load current is supplied by the inductor and the COUT capacitor as shown in Figure 18. During this period CIN is also being recharged by the VIN. Minimizing CIN loop inductance is important to reduce peak voltage excursions when Q1 turns off. Also, the difference in area between the CIN loop and COUT loop is vital to minimize switching and GND noise. VIN VIN CIN COUT CIN COUT Figure 16 — Typical buck converter The path between the COUT and CIN capacitors is of particular importance since the AC currents are flowing through both of them when Q1 is turned on. Figure 17, schematically, shows the reduced trace length between input and output capacitors. The shorter path lessens the effects that copper trace parasitics can have on the PI3302-03 performance. Figure 18 — Current flow: Q2 closed The recommended component placement, shown in Figure 19, illustrates the tight path between CIN and COUT (and VIN and VOUT ) for the high AC return current. This optimized layout is used on the PI3302-03 evaluation board. VOUT VIN CIN COUT GND CIN COUT VIN VSW GND Figure 17 — Current flow: Q1 closed Figure 19 — Recommended component placement and metal routing ZVS Regulators Rev 1.6 Page 14 of 18 07/2022 PI3302-03-LGIZ Recommended PCB Footprint and Stencil Recommended receiving footprint for PI3302-03 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm, whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a 5 or 6mil stencil. ZVS Regulators Rev 1.6 Page 15 of 18 07/2022 PI3302-03-LGIZ Package Drawings DIMESIONAL REFERENCES REF. MIN NOM 2.50 2.56 A A1 A2 0.50 0.55 b L 0.50 0.55 14.00 BSC D 10.00 BSC E 13.00 BSC D1 9.00 BSC E1 e 1.00 BSC 0.10 0.15 L1 aaa bbb ccc ddd eee ZVS Regulators Rev 1.6 Page 16 of 18 07/2022 MAX 2.62 0.05 2.57 0.60 0.60 0.20 0.10 0.10 0.08 0.10 0.08 PI3302-03-LGIZ Revision History Revision Date Description 1.0 05/05/16 Initial release 1.1 05/13/16 Change PGD description 1.2 02/28/17 Figure 2 update Format update 7 all 1.3 08/07/20 Updated terminology 12 1.4 12/02/20 Revised values for ceramic capacitors CINPUT and COUTPUT 13 1.5 02/14/22 Revised TRK enable threshold, charge current (soft start) 1.6 07/06/22 I2C operation references removed Note: page added in Rev 1.3. ZVS Regulators Rev 1.6 Page 17 of 18 07/2022 Page Number(s) n/a 4 & 10 7 11, 13 PI3302-03-LGIZ Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. 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Contact Us: http://www.vicorpower.com/contact-us Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 www.vicorpower.com email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com ©2020 – 2022 Vicor Corporation. All rights reserved. The Vicor name is a registered trademark of Vicor Corporation. All other trademarks, product names, logos and brands are property of their respective owners. ZVS Regulators Rev 1.6 Page 18 of 18 07/2022