ZVS Regulators
PI34xx-00-LGIZ
8 – 18VIN, 15A ZVS Buck Regulator
Product Description
Features & Benefits
The PI34xx-00 is a family of high‑efficiency DC-DC ZVS Buck
regulators integrating the controller, power switches and support
components within a high-density System-in-Package (SiP).
• High-efficiency ZVS Buck topology
The PI34xx-00 is designed to achieve optimum efficiency at low
input voltage ranges (8 – 18V). The utilization of zero‑current soft
turn-on provided by the high‑performance ZVS topology within the
PI34xx-00 series increases point‑of‑load performance, providing
best in class power efficiency with high throughput power.
• Very fast transient response
The PI34xx-00 requires only an external inductor and minimal
capacitors to form a complete DC-DC switching‑mode
buck regulator.
• Parallel capable with single‑wire current sharing
Device
Output Voltage
• Input voltage range of 8 – 18V
• Power-up into pre-biased load
• High-accuracy pre-trimmed output voltage
• User adjustable soft start & tracking
• Input over/undervoltage lockout (OVLO/UVLO)
• Output overvoltage protection (OVP)
• Overtemperature Protection (OTP)
IOUT Max
Set
Range
PI3423-00-LGIZ
3.3V
2.3 – 4.1V
15A
PI3424-00-LGIZ
5.0V
3.3 – 6.5V
15A
• Fast and slow current limits
• –40 to 125°C operating range (TINT)
The ZVS architecture enables high‑frequency operation while
minimizing switching losses and maximizing efficiency. The
high‑switching‑frequency operation reduces the size of the external
filtering components, improves power density, and enables very
fast dynamic response to line and load transients.
The ZVS architecture enables operation up to 750kHz while
minimizing switching losses and the use of variable frequency
extends high efficiency over a very wide dynamic range. The
PI34xx-00 series has a minimum on time of 20ns which enables
large step‑down conversion ratios.
Applications
• High-Efficiency Systems
• Computing, Communications, Industrial,
Automotive Equipment
Package Information
• 10 x 14 x 2.6mm LGA SiP
Note: Product images may not highlight current product markings.
ZVS Regulators
Page 1 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Contents
Order Information
3
Application Description
15
Thermal, Storage and Handling Information
3
Output Voltage Trim
15
Absolute Maximum Ratings
3
Soft-Start Adjust and Tracking
16
Functional Block Diagram
4
Inductor Pairing
17
Pin Description
5
Thermal De-Rating
17
Package Pinout
6
Filter Considerations
17
PI3423-00-LGIZ (3.3VOUT ) Electrical Characteristics
7
PI3424-00-LGIZ (5.0VOUT ) Electrical Characteristics
Layout Guidelines
18
10
Recommended PCB Footprint and Stencil
19
Thermal De-Rating Curves
13
Package Drawings
20
Functional Description
14
Product Warranty
22
Enable (EN)
14
Remote Sensing
14
Switching Frequency Synchronization
14
Output Voltage Trim
14
Output Current Limit Protection
14
Input Undervoltage Lockout
14
Input Overvoltage Lockout
14
Output Overvoltage Protection
15
Overtemperature Protection
15
Parallel Operation
15
Pulse Skip Mode (PSM)
15
Variable-Frequency Operation
15
ZVS Regulators
Page 2 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Order Information
Product
Output Range
IOUT Max
Package
Transport Media
2.3 – 4.1V
15A
10 x 14mm 123-pin LGA
TRAY
3.3 – 6.5V
15A
10 x 14mm 123-pin LGA
TRAY
Set
Range
PI3423-00-LGIZ
3.3V
PI3424-00-LGIZ
5.0V
Thermal, Storage and Handling Information
Name
Rating
Storage Temperature
–65 to 150°C
Internal Operating Temperature
–40 to 125°C
Soldering Temperature for 20 seconds
245°C
MSL Rating
3
ESD Rating
2kV HBM; 1.0kV CDM
Absolute Maximum Ratings
Name
Rating
VIN
–0.7 to 22V
VS1
–0.7 to 22V, 25V for 5ns, –4V for 5ns
VOUT, REM
See relevant product section
SGND
100mA
PWRGD, SYNCO, SYNCI, EN, EAO, ADJ, TRK, ADR1, ADR2, SCL, SDA, VDR
–0.3 to 5.5V / 5mA
Notes: At 25°C ambient temperature. Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions
beyond those listed in the Electrical Characteristics is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted. Test conditions are
per the specifications within the individual product Electrical Characteristics.
ZVS Regulators
Page 3 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Functional Block Diagram
VIN
VS1
VIN
Q2
Q1
VOUT
R4
REM
Power
Control
R1
VCC
+
ZVS Control
SYNCO
SYNCI
PWRGD
EN
PGND
Memory
Interface
EAO
ADJ
1V R2
TRK
0Ω
ADR1
SDA
ADR0
SCL
SGND
Simplified block diagram (I2C™ pins SCL, SDA, ADR0, and ADR1 are for factory use only. Not for use in application.)
ZVS Regulators
Page 4 of 22
Rev 2.2
01/2022
VOUT
PI34xx-00-LGIZ
Pin Description
Name
Location
I/O
Description
SGND
Block 1
I/O
Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO and ADJ.
SGND and PGND are star‑connected within the regulator package.
PGND
Block 2
Power
Power Ground: VIN and VOUT power returns.
VIN
Block 3
Power
Input Voltage: and sense for UVLO, OVLO and feed‑forward ramp.
VOUT
Block 5
Power
Output Voltage: and sense for power switches and feed-forward ramp.
VS1
Block 4
Power
Switching Node: and ZVS sense for power switches.
PWRGD
A1
O
Power Good: High-impedance when regulator is operating and output voltage is within
approximately 80% of regulation set point; also can be used for parallel timing manangement
intended for lead regulator.
EAO
A2
O
Error Amp Output: External connection for additional compensation and current sharing.
EN
A3
I/O
Enable Input: Regulator enable control.
Asserted high or left floating: regulator enabled. Asserted low: regulator output disabled.
REM
A5
I
Remote Sense: High‑side connection. Connect to output regulation point.
ADJ
B1
I
Adjust Input: An external resistor may be connected between ADJ pin and SGND or VOUT to trim
the output voltage up or down.
TRK
C1
I/O
Soft-Start and Track Input: An external capacitor may be connected between TRK pin and SGND
to decrease the rate of rise during soft start.
NC
A4
Open
SYNCO
K4
O
Synchronization Output: Outputs a high signal for ½ of the minimum period for synchronization
of other regulators.
VDR
K3
O
Internally generated 5.1V for internal use. May be used externally provided it is impedance‑limited
to prevent current in excess of 2mA under any circumstances.
SYNCI
K5
I
Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a
high‑impedance digital input node and should always be connected to SGND when not in use.
SDA
D1
I/O
Data Line: Connect to SGND. Factory use only. Not for use in application.
SCL
E1
I/O
Clock Line: Connect to SGND. Factory use only. Not for use in application.
ADR1
H1
I
Tri-State Address: No connect. Factory use only. Not for use in application.
ADR0
G1
I
Tri-State Address: No connect. Factory use only. Not for use in application.
ZVS Regulators
Page 5 of 22
No Connect: Leave pins floating.
Rev 2.2
01/2022
PI34xx-00-LGIZ
Package Pinout
A
D
E
G
K
PGD/
PWRGD
ADJ
TRK
SDA
SCL
SGND
ADR0
ADR1
SGND
SGND
EAO
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
EN
SGND
SGND
SGND
SGND
SGND
SGND
SGND
SGND
VDR
NC
SGND
SGND
PGND
PGND
PGND
PGND
PGND
SYNCO
PGND
PGND
PGND
PGND
PGND
SYNCI
REM
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
VOUT
VOUT
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VS1
VS1
VS1
VS1
VS1
VIN
VIN
VIN
VIN
VS1
VS1
VS1
VS1
VS1
VIN
VIN
VIN
VIN
VS1
VS1
VS1
VS1
VS1
VIN
VIN
VIN
VIN
PI34xx-00
Pin Block Name
Group of pins
SGND
B2-4, C2-4, D2-3, E2-3, F1-3, G2-3, H2-3, J1-3, K1-2
PGND
A8-10, B8-10, C8-10, D8-10, E4-10, F4-10, G4-10, H4-10, J4-10, K6-10
VIN
G12-14, H12-14, J12-14, K12-14
VS1
A12-14, B12-14, C12-14, D12-14, E12-14
VOUT
A6-7, B6-7, C6-7, D6-7
ZVS Regulators
Page 6 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3423-00-LGIZ (3.3VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 125°C, VIN = 12V, L1 = 150nH [a] unless other conditions are noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
8
12
18
V
Input Specifications
Input Voltage
VIN_DC
[f]
Input Current
IIN_DC
VIN = 12V, TC = 25°C, IOUT = 15A
Input Current at Output Short
(Fault-Condition Duty Cycle)
IIN_Short
4.43
[b]
A
10
Disabled
2.6
Input Quiescent Current
IQ_VIN
Input Voltage Slew Rate
VIN_SR
[b]
VOUT_DC
[b]
3.24
VOUT_DC
[c]
2.3
Enabled (no load)
mA
mA
4
1
V/µs
3.30
3.36
V
3.3
4.1
V
Output Specifications
Output Voltage Total Regulation
Output Voltage Trim Range
Line Regulation
∆VOUT(∆VIN)
Load Regulation
∆VOUT(∆IOUT)
At 25°C, 8V < VIN < 18V
0.10
At 25°C, 0.5A < IOUT < 15A
0.10
%
17
mVP-P
Output Voltage Ripple
VOUT_AC
IOUT = 7.5A, COUT = 8 x 100μF, 20MHz BW [d]
Continuous Output Current Range
IOUT_DC
Refer to load current vs. ambient temperature curves
Current Limit
IOUT_CL
%
15
18
A
A
Protection
UVLO Start Threshold
VUVLO_START
UVLO Stop Hysteresis
VUVLO_HYS
OVLO Stop Threshold
VOVLO
OVLO Start Hysteresis
VOVLO_HYS
7.10
7.60
8.00
0.36
19.0
20.75
V
V
21.78
V
0.37
V
Number of the switching-frequency cycles
128
Cycles
tf
+1% overdrive
500
ns
Output Overvoltage Protection
VOVP
Above set VOUT
20
%
Overtemperature Fault Threshold
TOTP
UVLO/OVLO Fault Delay Time
UVLO/OVLO Response Time
Overtemperature Restart Hysteresis
tf_DLY
130
TOTP_HYS
135
30
[a]
140
ºC
ºC
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI34xx-00 evaluation board with 3 x 4in
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when switching frequency or
VOUT is modified.
[d] Refer to output ripple plots.
[e] Refer to switching frequency vs. load current curves.
[f] Minimum 5V between V – V
IN
OUT must be maintained or a minimum load of 1mA required.
ZVS Regulators
Page 7 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3423-00-LGIZ (3.3VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 125°C, VIN = 12V, L1 = 150nH [a] unless other conditions are noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Timing
Switching Frequency
Fault Restart Delay
fS
[e]
tFR_DLY
700
kHz
30
ms
Sync In (SYNCI)
Synchronization Frequency Range
∆fSYNCI
SYNCI Threshold
VSYNCI
2.5
V
SYNCI Input Impedance
ZSYNCI
100
kΩ
Relative to set switching frequency [c]
50
110
%
Sync Out (SYNCO)
SYNCO High
VSYNCO_HI
Source 1mA
SYNCO Low
VSYNCO_LO
Sink 1mA
SYNCO Rise Time
tSYNCO_RT
20pF load
10
ns
SYNCO Fall Time
tSYNCO_FT
20pF load
10
ns
4.5
V
0.5
V
Soft Start and Tracking
TRK Active Input Range
VTRK
Internal reference tracking range
0
1.2
V
TRK Max Output Voltage
VTRK_MAX
TRK Enable Threshold
VTRK_OV
20
40
62
mV
ITRK
–70
–50
–25
µA
Charge Current (Soft–Start)
Discharge Current (Fault)
Soft-Start Time
1.2
ITRK_DIS
tSS
CTRK = 0µF
TRK to EAIN Offset
V
6.8
mA
2.2
ms
34
100
mV
Enable
High Threshold
VEN_HI
0.9
1
1.1
V
Low Threshold
VEN_LO
0.7
0.8
0.9
V
Threshold Hysteresis
VEN_HYS
100
200
300
mV
Enable Pull-Up Voltage
(Floating, Unfaulted)
VEN_PU
With positive-logic EN polarity
2
V
Enable Pull-Down Voltage
(Floating, Faulted)
VEN_PD
With negative-logic EN polarity
0
V
Source Current
IEN_SO
With positive-logic EN polarity
–50
µA
Sink Current
IEN_SK
With negative-logic EN polarity
50
µA
[a]
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI34xx-00 evaluation board with 3 x 4in
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when switching frequency or
VOUT is modified.
[d] Refer to output ripple plots.
[e] Refer to switching frequency vs. load current curves.
[f] Minimum 5V between V – V
IN
OUT must be maintained or a minimum load of 1mA required.
ZVS Regulators
Page 8 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3423-00-LGIZ (3.3VOUT) Electrical Characteristics (Cont.)
100
95
Efficiency (%)
90
85
80
75
70
65
60
55
50
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Output Current (A)
VIN:
8V
12V
18V
Figure 1 — Efficiency at 25ºC
Figure 4 — Transient response: 7.5 – 15A, at 5A/µs
Figure 2 — Short circuit test
Figure 5 — Output ripple 12VIN 3.3VOUT at 15A; COUT = 8 x 100µF
Switching Frequency (kHz)
800
700
600
500
400
300
200
100
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Output Current (A)
VIN:
8V
12V
Figure 3 — Switching frequency vs. load current
ZVS Regulators
Page 9 of 22
18V
Figure 6 — Output ripple 12VIN 3.3VOUT at 7.0A;
COUT = 8 x 100µF
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3424-00-LGIZ (5.0VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 125°C, VIN = 12V, L1 = 150nH [a] unless other conditions are noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
8
12
18
V
Input Specifications
Input Voltage
VIN_DC
[f]
Input Current
IIN_DC
VIN = 12V, TC = 25°C, IOUT = 15A
Input Current at Output Short
(Fault-Condition Duty Cycle)
IIN_Short
6.57
[b]
A
10
Disabled
2.6
Input Quiescent Current
IQ_VIN
Input Voltage Slew Rate
VIN_SR
[b]
VOUT_DC
[b]
4.93
VOUT_DC
[c]
3.3
Enabled (no load)
mA
mA
4
1
V/µs
5.07
V
6.5
V
Output Specifications
Output Voltage Total Regulation
Output Voltage Trim Range
Line Regulation
∆VOUT(∆VIN)
Load Regulation
∆VOUT(∆IOUT)
At 25°C, 8V < VIN < 18V
5
0.10
%
At 25°C, 0.5A < IOUT < 15A
0.10
%
Output Voltage Ripple
VOUT_AC
IOUT = 7.5A, COUT = 8 x 100μF, 20MHz BW [d]
20.8
mVP-P
Continuous Output Current Range
IOUT_DC
Refer to load current vs. ambient temperature curves
Current Limit
IOUT_CL
15
18
A
A
Protection
UVLO Start Threshold
VUVLO_START
UVLO Stop Hysteresis
VUVLO_HYS
OVLO Stop Threshold
VOVLO
OVLO Start Hysteresis
VOVLO_HYS
7.10
7.60
8.00
0.36
19.0
20.75
V
V
21.78
V
0.37
V
Number of the switching-frequency cycles
128
Cycles
tf
+1% overdrive
500
ns
Output Overvoltage Protection
VOVP
Above set VOUT
20
%
Overtemperature Fault Threshold
TOTP
UVLO/OVLO Fault Delay Time
UVLO/OVLO Response Time
Overtemperature Restart Hysteresis
tf_DLY
130
TOTP_HYS
135
30
[a]
140
ºC
ºC
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI34xx-00 evaluation board with 3 x 4in
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when switching frequency or
VOUT is modified.
[d] Refer to output ripple plots.
[e] Refer to switching frequency vs. load current curves.
[f] Minimum 5V between V – V
IN
OUT must be maintained or a minimum load of 1mA required.
ZVS Regulators
Page 10 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3424-00-LGIZ (5.0VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 125°C, VIN = 12V, L1 = 150nH [a] unless other conditions are noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Timing
Switching Frequency
Fault Restart Delay
fS
[e]
tFR_DLY
750
kHz
30
ms
Sync In (SYNCI)
Synchronization Frequency Range
∆fSYNCI
SYNCI Threshold
VSYNCI
2.5
V
SYNCI Input Impedance
ZSYNCI
100
kΩ
Relative to set switching frequency [c]
50
110
%
Sync Out (SYNCO)
SYNCO High
VSYNCO_HI
Source 1mA
SYNCO Low
VSYNCO_LO
Sink 1mA
SYNCO Rise Time
tSYNCO_RT
20pF load
10
ns
SYNCO Fall Time
tSYNCO_FT
20pF load
10
ns
4.5
V
0.5
V
Soft Start and Tracking
TRK Active Input Range
VTRK
Internal reference tracking range
0
1.2
V
TRK Max Output Voltage
VTRK_MAX
TRK Enable Threshold
VTRK_OV
20
40
62
mV
ITRK
–70
–50
–25
µA
Charge Current (Soft–Start)
Discharge Current (Fault)
Soft-Start Time
1.2
ITRK_DIS
tSS
CTRK = 0µF
TRK to EAIN Offset
V
6.8
mA
2.2
ms
34
100
mV
Enable
High Threshold
VEN_HI
0.9
1
1.1
V
Low Threshold
VEN_LO
0.7
0.8
0.9
V
Threshold Hysteresis
VEN_HYS
100
200
300
mV
Enable Pull-Up Voltage
(Floating, Unfaulted)
VEN_PU
With positive-logic EN polarity
2
V
Enable Pull-Down Voltage
(Floating, Faulted)
VEN_PD
With negative-logic EN polarity
0
V
Source Current
IEN_SO
With positive-logic EN polarity
–50
µA
Sink Current
IEN_SK
With negative-logic EN polarity
50
µA
[a]
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI34xx-00 evaluation board with 3 x 4in
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when switching frequency or
VOUT is modified.
[d] Refer to output ripple plots.
[e] Refer to switching frequency vs. load current curves.
[f] Minimum 5V between V – V
IN
OUT must be maintained or a minimum load of 1mA required.
ZVS Regulators
Page 11 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
PI3424-00-LGIZ (5.0VOUT) Electrical Characteristics (Cont.)
100
95
Efficiency (%)
90
85
80
75
70
65
60
55
50
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Output Current (A)
VIN:
8V
12V
18V
Figure 7 — Efficiency at 25ºC
Figure 10 — Transient response: 7.5 – 15A, at 5A/µs
Figure 8 — Short circuit test
Figure 11 — Output ripple 12VIN 5.0VOUT at 15A; COUT = 8 x 47µF
Switching Frequency (kHz)
800
700
600
500
400
300
200
100
0
1
2
3
4
5
6
7
8
9
10
11 12 13 14 15
Output Current (A)
VIN:
8V
12V
Figure 9 — Switching frequency vs. load current
ZVS Regulators
Page 12 of 22
18V
Figure 12 — Output ripple 12VIN 5.0VOUT at 7.0A; COUT = 8 x 47µF
Rev 2.2
01/2022
PI34xx-00-LGIZ
16
16
14
14
12
12
Load Current (A)
Load Current (A)
Thermal De-Rating Curves
10
8
6
4
2
10
8
6
4
2
0
0
25
35
45
55
65
75
85
95
105
25
115
35
Ambient Temperature (ºC)
VIN:
8V
12V
55
65
75
85
95
105
115
Ambient Temperature (ºC)
18V
VIN:
Figure 13 — PI3423 – load current vs. ambient temperature, 0LFM
ZVS Regulators
Page 13 of 22
45
8V
12V
18V
Figure 14 — PI3424 – load current vs. ambient temperature, 0LFM
Rev 2.2
01/2022
PI34xx-00-LGIZ
Functional Description
Soft-Start
The PI34xx-00 is a family of highly integrated ZVS Buck regulators.
The PI34xx-00 has a set output voltage that is trimmable within
a prescribed range shown in Table 1. Performance and maximum
output current are characterized with a specific external power
inductor (see Table 4).
The PI34xx-00 includes an internal soft-start capacitor to ramp the
output voltage in 2ms from 0V to full output voltage. Connecting
an external capacitor from the TRK pin to SGND will increase the
start-up ramp period. See, “Soft Start Adjustment and Track,” in
the Applications Description section for more details.
Output Voltage Trim
The PI34xx-00 output voltage can be trimmed up from the preset
output by connecting a resistor from ADJ pin to SGND and can be
trimmed down by connecting a resistor from ADJ pin to VOUT. The
Table 1 defines the voltage ranges for the PI34xx-00 family.
L1
VIN
VIN
CIN
PGND
VS1
PI34xx
VOUT
VOUT
COUT
REM
TRK
SYNCO
ADJ
EN
EAO
SGND
SYNCI
Device
For basic operation, Figure 15 shows the connections and
components required. No additional design or settings are required.
Enable (EN)
EN is the enable pin of the regulator. The EN Pin is referenced to
SGND and permits the user to turn the regulator on or off. The EN
polarity is a positive logic assertion. If the EN pin is left floating or
asserted high, the regulator output is enabled. Pulling EN pin below
0.8VDC with respect to SGND will disable the regulator output.
Remote Sensing
An internal 100Ω resistor is connected between REM pin and
VOUT pin to provide regulation when the REM connection is
broken. Referring to Figure 15, it is important to note that L1 and
COUT are the output filter and the local sense point for the power
supply output. As such, the REM pin should be connected at COUT
as the default local sense connection unless remote sensing to
compensate additional distribution losses in the system. The REM
pin should not be left floating.
Switching Frequency Synchronization
The SYNCI input allows the user to synchronize the controller
switching frequency by an external clock referenced to SGND. The
external clock can synchronize the unit between 50 and 110% of
the preset switching frequency (fS).
ZVS Regulators
Page 14 of 22
Set
Range
PI3423-00-LGIZ
3.3V
2.3 – 4.1V
PI3424-00-LGIZ
5.0V
3.3 – 6.5V
Table 1 — PI34xx-00 family output voltage ranges
Figure 15 — ZVS Buck with required components
The PI34xx-00 syncs to the falling edge of the applied clock
providing 180° phase shift from SYNCO. This allows for the
paralleling of two PI34xx-00 devices. When using the internal
oscillator, the SYNCO pin provides a 5V clock that can be used
to sync other regulators. Therefore, one PI34xx-00 can act as the
lead regulator and have additional PI34xx-00s running in parallel
and interleaved.
Output Voltage
Output Current Limit Protection
PI34xx-00 has two methods implemented to protect from output
short or overcurrent condition.
Slow Current Limit protection: prevents the output load from
sourcing current higher than the regulator’s maximum rated
current. If the output current exceeds the Current Limit (IOUT_CL) for
1024µs, a slow current limit fault is initiated and the regulator is
shut down which eliminates output current flow. After Fault Restart
Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be
repeated indefinitely until the excessive load is removed.
Fast Current Limit protection: PI34xx-00 monitors the regulator
inductor current pulse-by-pulse to prevent the output from
supplying very high current due to sudden low impedance short
(50A typical). If the regulator senses a high inductor current pulse,
it will initiate a fault and stop switching until Fault Restart Delay
ends and then initiate a soft-start cycle.
Input Undervoltage Lockout
If VIN falls below the input Undervoltage Lockout (UVLO) threshold,
the regulator will enter a low‑power state and initiate a fault. The
system will restart once the input voltage is reestablished and after
the Fault Restart Delay.
Input Overvoltage Lockout
If VIN exceeds the input Overvoltage Lockout (OVLO) threshold
(VOVLO), while the regulator is running, the PI34xx-00 will complete
the current cycle and stop switching. The system will resume
operation after the Fault Restart Delay.
Rev 2.2
01/2022
PI34xx-00-LGIZ
Output Overvoltage Protection
The PI34xx-00 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage sensitive
devices. If the output voltage exceeds 20% of its set regulated
value, the regulator will complete the current cycle, stop switching
and issue an OVP fault. The system will resume operation once
the output voltage falls below the OVP threshold and after Fault
Restart Delay.
Overtemperature Protection
The internal package temperature is monitored to prevent
internal components from reaching their thermal maximum. If the
Overtemperature Protection Threshold (OTP) is exceeded (TOTP),
the regulator will complete the current switching cycle, enter a
low‑power mode, set a fault flag, and will soft start when the
internal temperature falls below Overtemperature Restart (TOTP_HYS).
Parallel Operation
Paralleling modules can be used to increase the output current
capability of a single power rail and reduce output voltage ripple.
VIN
VIN
CIN
SYNCO(#2)
R1
SYNCI(#2)
EN(#2)
VS1
PGND
SGND
L1
VS1
PGND
Each PI34xx-00 is preprogrammed to a base operating frequency,
with respect to the power stage inductor (see Table 4), to operate
at peak efficiency across line and load variations. At low‑line
and high‑load applications, the base frequency will decrease to
accommodate these extreme operating ranges. By stretching the
frequency, the ZVS operation is preserved throughout the total
input line voltage range therefore maintaining optimum efficiency.
The PI34xx-00 family of buck regulators provides five common
output voltages: 1.0, 1.8, 2.5, 3.3 and 5.0V. A post-package
trim step is implemented to offset any resistor divider network
errors ensuring maximum output accuracy. With a single resistor
connected from the ADJ pin to SGND or REM, each device’s
output can be varied above or below the nominal set voltage (the
PI3420‑00 can only be adjusted above the set voltage of 1V).
EN
VIN
Variable-Frequency Operation
Output Voltage Trim
SYNCO
TRK
PI34xx-00 features a PSM to achieve high efficiency at light loads.
The regulators are set up to skip pulses if EAO falls below a PSM
threshold. Depending on conditions and component values, this
may result in single pulses or several consecutive pulses followed
by skipped pulses. Skipping cycles significantly reduces gate drive
power and improves light load efficiency. The regulator will leave
PSM once the EAO rises above the Skip Mode threshold.
Application Description
SYNCI
TRK(#2)
Pulse Skip Mode (PSM)
VOUT
COUT
ZVS Buck
(#1) REM
EAO
CIN
VOUT
PWRGD
EAO(#2)
VIN
L1
synchronization. Once the regulators reach regulation, SYNCI is
released and the system is now synchronized in a closed-loop
configuration which allows the system to adjust on the fly, when
any of the individual regulators begin to enter variable frequency
mode in the loop.
VOUT
COUT
ZVS Buck
(#2) REM
PWRGD
SYNCO(#1)
SYNCI(#1)
EN(#1)
SYNCI
Device
SYNCO
Set
Range
PI3423-00-LGIZ
3.3V
2.3 – 4.1V
PI3424-00-LGIZ
5.0V
3.3 – 6.5V
EN
EAO(#1)
EAO
TRK(#1)
TRK
SGND
Output Voltage
Figure 16 — PI34xx-00 parallel operation
Table 2 — PI34xx-00 family output voltage ranges
By connecting the EAO pins and SGND pins of each module
together the units will share the current equally. When the TRK
pins of each unit are connected together, the units will track each
other during soft start and all unit EN pins have to be released to
allow the units to start (See Figure 16). Also, any fault event in any
regulator will disable the other regulators. The two regulators will
be out of phase with each other reducing output ripple (refer to
Switching Frequency Synchronization).
The remote pin (REM) should always be connected to the VOUT pin
to prevent an output voltage offset. Figure 17 shows the internal
feedback voltage‑divider network.
To provide synchronization between regulators over the entire
operational frequency range, the Power Good (PWRGD) pin must
be connected to the lead regulator’s (#1) SYNCI pin and a 2.5kΩ
Resistor, R1, must be placed between SYNCO (#2) return and
the lead regulator’s SYNCI (#1) pin, as shown in Figure 16. In this
configuration, at system soft start, the PWRGD pin pulls SYNCI
low forcing the lead regulator to initialize the open-loop start‑up
ZVS Regulators
Page 15 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Resistor RHIGH should be connected as shown in Figure 17 to
achieve the desired 4.0V regulator output. No external RLOW
resistor is need in this design example since the trim is above the
regulator set voltage.
VOUT
The PI3420 output voltage can only be trimmed higher than the
factory 1V setting. The following Equation 3 can be used calculate
RHIGH values for the PI3420 regulators.
R4
REM
R1
RLOW
ADJ
-
RHIGH(1V) =
+
RHIGH
R2
1.0VDC
SGND
The TRK pin offers a means to increase the regulator’s soft-start
time or to track with additional regulators. The soft‑start slope is
controlled by an internal capacitor and a fixed charge current to
provide a Soft-Start Time tSS for all for all PI34xx-00 regulators.
By adding an additional external capacitor to the TRK pin, the
soft‑start time can be increased further. The following equation
can be used to calculate the proper capacitor for a desired
soft-start times:
R1, R2, and R4 are all internal 1.0% resistors and RLOW and RHIGH
are external resistors for which the designer can add to modify
VOUT to a desired output. The internal resistor values for each
regulator are listed next in Table 3.
Device
R1
R2
R4
PI3423-00-LGIZ
2.61kΩ
1.13kΩ
100Ω
PI3424-00-LGIZ
4.53kΩ
1.13kΩ
100Ω
CTRK = (tTRK • ITRK) – 100 x 10–9,
where, tTRK is the soft-start time and ITRK is a 50µA internal charge
current (see Electrical Characteristics for limits).
Table 3 — PI34xx-00 internal divider values
There is typically either a proportional or direct tracking method
implemented within a tracking design. For proportional tracking
between several regulators at start up, simply connect all devices
TRK pins together. This type of tracking will force all connected
regulators to start up and reach regulation at the same time (see
Figure 18 (a)).
By choosing an output voltage value within the ranges stated in
Table 2, VOUT can simply be adjusted up or down by selecting the
proper RHIGH or RLOW value, respectively. The following equations
can be used to calculate RHIGH and RLOW values:
RLOW =
1
(VOUT – 1) – 1
R1
R2
1
1
R2(VOUT – 1)
–
For Direct Tracking, choose the regulator with the highest output
voltage as the parent and connect the parent TRK pin to the TRK
pin of the other regulators through a divider (Figure 19) with the
same ratio as the child’s feedback divider (see Table 3 for values).
(1)
( )
1
R1
(2)
VOUT 1
VOUT 2
If, for example, a 4.0V output is needed, the user should choose
the regulator with a trim range covering 4.0V from Table 2. For this
example, the PI3423 is selected (3.3V set voltage). First step would
be to use Equation 1 to calculate RHIGH since the required output
voltage is higher than the regulator set voltage. The resistor-divider
network values for the PI3423 can be found in Table 3 and are
(a)
Parent VOUT
VOUT 2
R1 = 2.61kΩ and R2 = 1.13kΩ. Inserting these values into
Equation 1, RHIGH is calculated as follows:
3.78k =
1
(4.0 – 1)
2.61k
– 1
1.13
(3)
Soft-Start Adjust and Tracking
Figure 17 — Internal resistor divider network
RHIGH =
1
V
( OUT – 1)
R1
(b)
t
Figure 18 — PI34xx-00 tracking methods
All connected regulators’ soft-start slopes will track with this
method. Direct tracking timing is demonstrated in Figure 18 (b).
ZVS Regulators
Page 16 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Thermal De-Rating
Thermal de-rating curves are provided that are based on
component temperature changes versus load current, input
voltage and air flow. It is recommended to use these curves as a
guideline for proper thermal de-rating. These curves represent the
entire system and are inclusive to both the Vicor regulator and the
external inductor. Maximum thermal operation is limited by either
the MOSFETs or inductor depending upon line and load conditions.
Parent VOUT
R1
PI34xx
TRK
Child
Thermal measurements were made using a standard PI34xx-00
evaluation board which is 3 x 4 inches in area and uses 4-layer,
2oz copper. Thermal measurements were made on the three
main power devices, the two internal MOSFETs and the
external inductor.
R2
SGND
Filter Considerations
Figure 19 — Voltage divider connections for direct tracking
All tracking regulators should have their Enable (EN) pins connected
together to work properly.
Inductor Pairing
The PI34xx-00 utilizes an external inductor from Eaton Corporation.
This inductor has been optimized for maximum efficiency
performance. Table 4 details the specific inductor value and part
number utilized for each PI34xx-00 device.
Data sheets are available at:
www.eaton.com.
Device
Inductor
(nH)
Inductor
Part Number
Manufacturer
PI3423-00
150
FPV1006-150-R
Eaton
PI3424-00
150
FPV1006-150-R
Eaton
Table 4 — PI34xx-00 inductor pairing
Device
VIN
(V)
PI3423
12
PI3424
12
ILOAD
(A)
15
7.5
15
7.5
The PI34xx-00 requires input bulk storage capacitance as well as
low‑impedance ceramic X5R input capacitors to ensure proper
start up and high-frequency decoupling for the power stage. The
PI34xx-00 will draw nearly all of the high‑frequency current from
the low‑impedance ceramic capacitors when the main high‑side
MOSFET is conducting. During the time the high-side MOSFET
is off, they are replenished from the bulk capacitor. If the input
impedance is high at the switching frequency of the regulator,
the bulk capacitor must supply all of the average current into the
regulator, including replenishing the ceramic capacitors. This value
has been chosen to be 100µF so that the PI34xx-00 can start up
into a full resistive load and supply the output capacitive load with
the default minimum soft‑start capacitor when the input source
impedance is 50Ω at 1MHz. The ESR for this capacitor should be
approximately 20mΩ. The RMS ripple current in this capacitor is
small, so it should not be a concern if the input recommended
ceramic capacitors are used. Table 5 shows the recommended
input and output capacitors to be used for the various models
as well as expected transient response, RMS ripple currents per
capacitor, and input and output ripple voltages. Table 6 includes
the recommended input and output ceramic capacitors.
CINPUT
Bulk
Electrolytic
CINPUT
Ceramic
X5R
COUTPUT
Ceramic
X5R
CINPUT
Ripple
Current
(IRMS)
COUTPUT
Ripple
Current
(IRMS)
100µF
50V
6 x 22µF
8 x 100µF
2 x 1µF
1 x 0.1µF
1.20
1.15
100µF
50V
6 x 22µF
8 x 100µF
2 x 1µF
1 x 0.1µF
1.29
1.13
Table 5 — Recommended input and output capacitance
ZVS Regulators
Page 17 of 22
Rev 2.2
01/2022
Input
Ripple
(mVP-P)
Output
Ripple
(mVP-P)
179
26
97
17
209
34
98
24.8
Output
Ripple
(mVPK)
Recovery Load Step
Time
(A)
(µs)
[Slew/µs]
±73
70
7.5
[5A/µs]
±98
60
7.5
[5A/µs]
PI34xx-00-LGIZ
Murata Part Number
Description
GRM188R71C105KA12D
1µF 16V 0603 X7R
GRM319R71H104KA01D
0.1µF 50V 1206 X7R
GRM31CR60J107ME39L
100µF 6.3V 1206 X5R
GRM31CR61A476ME15L
47µF 10V 1206 X5R
GRM31CR61E226KE15L
22µF 25V 1206 X5R
When Q1 is on and Q2 is off, the majority of CIN’s current is used
to satisfy the output load and to recharge the COUT capacitors.
When Q1 is off and Q2 is on, the load current is supplied by the
inductor and the COUT capacitor as shown in Figure 22. During this
period CIN is also being recharged by the VIN. Minimizing CIN loop
inductance is important to reduce peak voltage excursions when
Q1 turns off. Also, the difference in area between the CIN loop and
COUT loop is vital to minimize switching and GND noise.
Table 5 — Capacitor manufacturer part numbers
Layout Guidelines
To achieve maximum efficiency and low‑noise performance
from a PI34xx-00 design, layout considerations are necessary.
Reducing trace resistance and minimizing high‑current loop
returns along with proper component placement will contribute to
optimal performance.
VIN
A typical buck regulator circuit is shown in Figure 20. The potential
areas of high parasitic inductance and resistance are the circuit
return paths, shown as LR below.
CIN
COUT
Figure 22 — Current flow: Q2 closed
VIN
COUT
CIN
The recommended component placement, shown in Figure 23,
illustrates the tight path between CIN and COUT (and VIN and VOUT )
for the high AC return current. This optimized layout is used on the
PI34xx-00 evaluation board.
VOUT
COUT
Figure 20 — Typical buck regulator
GND
The path between the COUT and CIN capacitors is of particular
importance since the AC currents are flowing through both of
them when Q1 is turned on.
CIN
VIN
Figure 21, schematically, shows the reduced trace length
between input and output capacitors. The shorter path
lessens the effects that copper trace parasitics can have on the
PI34xx-00 performance.
VIN
CIN
GND
Figure 23 — Recommended component placement and
metal routing
COUT
Figure 21 — Current flow: Q1 closed
ZVS Regulators
Page 18 of 22
VSW
Rev 2.2
01/2022
PI34xx-00-LGIZ
Recommended PCB Footprint and Stencil
L
PI34xx-00
L
Recommended receiving footprint for PI34xx‑00 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm,
whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a
5 or 6mil stencil.
ZVS Regulators
Page 19 of 22
Rev 2.2
01/2022
PI34xx-00-LGIZ
Package Drawings
A
K
G
E D
A
D
B
E
DETAIL A
M
L
DETAIL B
A
SEATING PLANE
METALLIZED
PAD
M
M
A
M
SOLDER MASK
DETAIL A
A
L
D
E
AND POSITION
ZVS Regulators
Page 20 of 22
Rev 2.2
01/2022
A
PI34xx-00-LGIZ
Revision History
Revision
Date
1.0
02/13
1.1
08/03/15
Description
Last release in old format
n/a
Reformatted in new template
n/a
1.2
09/03/15
Inductor pairing table updates
1.3
12/21/15
Clarifications made in Enable Pin Conditions
02/03/20
Formatting changes
Changed PGD pin name to PWRGD
Removed continuous output current range min
Corrected UVLO stop hysteresis, OVLO stop threshold, OVLO start hysteresis
Updated sink current
Added TRK to EAIN offset spec,
revised soft-start charge current, TRK enable threshold
Updated input quiescent current enabled
Updated output voltage total regulation
Updated mechanical drawings
1.4
1.5
02/26/20
Added CDM ESD rating
1.6
05/14/20
Corrected REM absolute maximum rating
1.7
08/11/20
Updated terminology
1.8
12/31/20
Removed end-of-life part numbers
(for PI3420-00, PI3421-00 and PI3422-00 data, see separate document)
Revised PI3424-00 switching frequency vs. load current plot
1.9
01/04/21
Revised switching frequency typical specification
2.0
02/24/21
Revised UVLO start threshold
Added SYNCI input impedance specification
2.1
09/01/21
Corrected figure 1 plot
01/14/22
Corrections to figures 1, 2, 4, 7, 8, 10
removed irrelevant figures
2.2
6, 7 & 25
7, 8, 11, 14, 17 & 28
All
3, 4, 5,
7
7, 10, 13, 16, 19
8
8, 11, 14, 17, 20
10
10, 16
28, 29
3
3
25, 26
1–3
12
11
7, 10
8, 11
9
Note: page added in Rev 1.4, pages removed in Rev 1.8.
ZVS Regulators
Page 21 of 22
Page Number(s)
Rev 2.2
01/2022
9, 12
13
PI34xx-00-LGIZ
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and
accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom
power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor
makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves
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Testing and other quality controls are used to the extent Vicor deems necessary to support Vicor’s product warranty. Except where
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Specifications are subject to change without notice.
Visit http://www.vicorpower.com/dc-dc-converters-board-mount/cool-power-pi33xx-and-pi34xx for the latest product information.
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Tel: 800-735-6200
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ZVS Regulators
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Rev 2.2
01/2022
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