ZVS Regulators
PI352x-00
30 – 60VIN ZVS Buck Regulator
Product Description
Features & Benefits
The PI352x-00 is a family of high input voltage, wide‑input‑range
DC-DC ZVS Buck regulators integrating controller, power
switches and support components all within a high‑density
System‑in‑Package (SiP).
• High‑Efficiency HV ZVS Buck Topology
The integration of a high-performance Zero-Voltage Switching
(ZVS) topology, within the PI352x-00 series, increases
point‑of‑load performance providing best‑in‑class power
efficiency. The PI352x-00 requires only an external inductor,
two voltage selection resistors and minimal capacitors to form a
complete DC‑DC switch‑mode buck regulator.
• Parallel‑capable with single‑wire current sharing
• Wide input voltage range of 30 – 60V
• Power-up into pre-biased load ≤ 6.0V
• Input Over/Undervoltage Lockout (OVLO/UVLO)
• Output Overvoltage Protection (OVP)
• Overtemperature Protection (OTP)
• Fast and slow current limits
Device
Output Voltage
IOUT Max
Set
Range
PI3523-00
3.3V
2.2 – 4V
22A
PI3525-00
5.0V
4.0 – 6.5V
20A
PI3526-00
12V
6.5 – 14V
18A
• Differential amplifier for output remote sensing
• User adjustable soft start & tracking
• –40 to 120°C operating range (TINT)
Applications
• HV to PoL Buck Regulator Applications
• Computing, Communications, Industrial,
Automotive Equipment
Package Information
• 10 x 14 x 2.56mm LGA SiP
ZVS Regulators
Page 1 of 41
Rev 2.1
10/2021
PI352x-00
Contents
Thermal, Storage and Handling Information
3
SiP Power Dissipation as Percentage of Total System Losses
33
Absolute Maximum Ratings
3
Application Description
34
Functional Block Diagram
4
Output Voltage Set Point
34
Pin Description
5
Soft Start Adjust and Tracking
34
Package Pinout
6
Inductor Pairing
35
PI352x-00 Common Electrical Characteristics
7
Parallel Operation
35
PI3523-00 (3.3VOUT ) Electrical Characteristics
8
Filter Considerations
35
PI3525-00 (5.0VOUT ) Electrical Characteristics
15
VDR Bias Regulator
36
PI3526-00 (12VOUT ) Electrical Characteristics
22
Layout Guidelines
37
Functional Description
29
LGA Recommended PCB Footprint and Stencil
38
ENABLE (EN)
29
LGA Package Drawings
39
Remote Sensing
29
Revision History
40
Soft Start
29
Warranty 41
Output Voltage Selection
29
Output Current Limit Protection
29
Input Undervoltage Lockout
29
Input Overvoltage Lockout
30
Output Overvoltage Protection
30
Overtemperature Protection
30
Pulse Skip Mode (PSM)
30
Variable Frequency Operation
30
Thermal Characteristics
30
ZVS Regulators
Page 2 of 41
Rev 2.1
10/2021
PI352x-00
Order Information
Product
Nominal Output
Rated IOUT
Package
PI3523-00-LGIZ
3.3V
22A
10 x 14mm LGA
5.0V
20A
12V
18A
PI3525-00-LGIZ
PI3525-00-LGIG
PI3526-00-LGIZ
10 x 14mm LGA
10 x 14mm LGA halogen free
Transport Media
TRAY
10 x 14mm LGA
Thermal, Storage and Handling Information
Name
Rating
Storage Temperature
–65 to 150°C
Internal Operating Temperature
–40 to 120°C
Soldering Temperature for 20 seconds
245°C
MSL Rating
3
ESD Rating, JESD22-A114F, JS-002-2014
2kV HBM; 1kV CDM, respectively
Absolute Maximum Ratings
Name
Rating
VIN
–0.7 to 75V
VS1
–0.7VDC to 75V
VOUT
–0.5 to 25V
SGND
±100mA
TRK
–0.3 to 5.5V, ±30mA
VDR, SYNCI, SYNCO, PWRGD, EN, COMP,
EAO, EAIN, VDIFF, VSN, VSP, TESTx
–0.3 to 5.5V, ±5mA
Notes: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the
Electrical Specifications table is not guaranteed. All voltages are referenced to PGND unless otherwise noted.
ZVS Regulators
Page 3 of 41
Rev 2.1
10/2021
PI352x-00
Functional Block Diagram
VS1
VIN
Q2
Q1
VDR
Power
Control
SYNCO
SYNCI
PWRGD
EN
TESTx
VOUT
+
–
VSP
VSN
VDIFF
VCC
ZVS Control
–
+
EAIN
CEAIN-INT
VREF
EAO
Digital Parametric Trim
RZI
CHF
COMP
TRK
PGND
0Ω
SGND
Simplified block diagram
ZVS Regulators
Page 4 of 41
Rev 2.1
10/2021
PI352x-00
Pin Description
Name
Location
I/O
Description
VS1
Block 1
Power
Switching Node: and ZVS sense for power switches.
VIN
Block 3
Power
Input Voltage: and sense for UVLO, OVLO and feed forward ramp.
VDR
5K
I/O
Gate Driver VCC: Internally generated 5.1V. May be used as a bias supply for low power external
loads. See Application Description for important considerations.
SYNCI
4K
I
Synchronization Input: Synchronize to the falling edge of external clock frequency. SYNCI is a
high impedance digital input node and should always be connected to SGND when not in use. The
PI352x-00 family is not optimized for external synchronization functionality. Refer to Application
Description of Parallel Operation for details.
SYNCO
3K
O
Synchronization Output: Outputs a high signal at the start of each clock cycle for the longer of
½ of the minimum period or the on time of the high side power MOSFET.
TEST1
2K
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST2
1K
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST3
1J
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST4
1H
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
TEST5
1E
I/O
Test Connections: Use only with factory guidance. Connect to SGND for proper operation.
PWRGD
1G
O
Power Good: High impedance when regulator is operating and VOUT is in regulation.
Otherwise pulls to SGND.
EN
1F
I/O
Enable Input: Regulator enable control. When asserted active or left floating: regulator is enabled.
Otherwise regulator is disabled.
SGND
Block 5
TRK
1C
I
Soft-Start and Track Input: An external capacitor may be connected between TRK pin and SGND
to increase the rise time of the internal reference during soft start.
COMP
1B
O
Compensation Capacitor: Connect capacitor for control loop dominant pole. See Error Amplifier
section for details. A default CCOMP of 4.7nF is used in the example.
EAO
1A
O
Error amp output: External connection for additional compensation and current sharing.
EAIN
2A
I
Error Amp Inverting Input: Connection for the main VOUT feedback divider tap.
VDIFF
3A
O
Independent Amplifier Output: Active only when module is enabled.
VSN
4A
I
Independent Amplifier Inverting Input: If unused connect in unity gain.
VSP
5A
I
Independent Amplifier Non-Inverting Input: If unused connect to SGND.
VOUT
6A,B
Power
Direct VOUT Connect: for per-cycle internal clamp node and feed-forward ramp.
PGND
Block2
Power
Power Ground: VIN and VOUT power returns.
ZVS Regulators
Page 5 of 41
Signal Ground: Internal logic ground for EA, TRK, SYNCI, SYNCO communication returns. SGND
and PGND are star connected within the regulator package.
Rev 2.1
10/2021
PI352x-00
Package Pinout
1
EA0
COMP
TRK
SGND
TEST5
EN
PWRG0
TEST4
TEST3
TEST2
2
EAIN
SGND
SGND
SGND
SGND
PGND
PGND
PGND
PGND
TEST1
3
VDIFF
SGND
SGND
SGND
SGND
PGND
PGND
PGND
PGND
SYNC0
4
VSN
SGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
SYNC1
5
VSP
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VDR
6
VOUT
VOUT
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
8
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
9
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
10
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
VIN
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
VS1
7
11
12
13
14
Pin Block Name
Group of pins
VIN
A8-10, B8-10, C8-10, D8-10, E8-10, F8-10, G8-10, H8-10, J8-10, K8-10
VS1
A14, B14, C14, D14, E14, F14, G14, H14, J14, K14
PGND
A12, B12, C12, D12, E12, F12, G12, H12, J12, K12
PGND
B5, C4-6, D4-6, E4-6, F2-6, G2-6, H2-6, J2-6, K6
VOUT
A6, B6
SGND
B2-4, C2-3, D1-3, E2-3
ZVS Regulators
Page 6 of 41
Rev 2.1
10/2021
PI352x-00
PI352x-00 Common Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Open Loop Gain
96
120
140
dB
Small Signal Gain-bandwidth
5
7
12
MHz
0.5
1
mV
2.5
V
Differential Amp
Input Offset
Common Mode Input Range
–0.1
Differential Mode Input Range
2
V
Input Bias Current
–1
1
µA
Output Current
–1
1
mA
Maximum VOUT
IVDIFF = –1mA
Minimum VOUT
IVDIFF = –1mA
4.85
Capacitive Load Range for Stability
V
0
Slew Rate
20
mV
50
pF
11
V/µs
PWRGD
VOUT Rising Threshold
VPG_HI%
78
84
90
% VOUT_DC
VOUT Falling Threshold
VPG_LO%
75
81
87
% VOUT_DC
PWRGD Output Low
VPG_SAT
0.4
V
Sink = 4mA
VDR
Voltage Set Point
VVDR
VIN_DC > 10V
External Loading
IVDR
See Application Description for details
4.9
5.05
0
5.2
V
2
mA
Enable
High Threshold
VEN_HI
0.9
1.0
1.1
V
Low Threshold
VEN_LO
0.7
0.8
0.9
V
Threshold Hysteresis
VEN_HYS
100
200
300
mV
Pull-Up Voltage Level for
Source Current
VEN_PU
Pull-Up Current
IEN_PU_POS
2
V
50
µA
MIL-HDBK-217, 25°C, Ground Benign: GB
12.6
MHrs
Telcordia SR-332, 25°C, Ground Benign: GB
96.9
MHrs
VIN > 8V, excluding tFR_DLY
Reliability
MTBF
[a]
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
ZVS Regulators
Page 7 of 41
Rev 2.1
10/2021
PI352x-00
PI3523-00 (3.3VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
30
48
60
V
Input Specifications
Input Voltage
VIN_DC
Input Current
IIN_DC
Input Current At Output Short
(fault condition duty cycle)
IIN_Short
VIN = 48V, TCASE = 25°C, IOUT = 22A
1.69
A
Short at terminals
4.7
mA
Input Quiescent Current
IQ_VIN
Disabled
0.75
Input Quiescent Current
IQ_VIN
Enabled, no load, TCASE = 25°C
1.8
Effective value VIN = 48V, 25°C
0.50
Input Voltage Slew Rate
VIN_SR
Input capacitance, Internal
CIN_INT
1.2
mA
mA
1
V/µs
µF
Output Specifications
EAIN Voltage Total Regulation
Output Voltage Trim Range
VEAIN
VOUT_DC
[b]
0.975
[b] [c]
2.2
Line Regulation
ΔVOUT / ΔVIN
Load Regulation
ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 22A
Output Voltage Ripple
At 25°C, 30V < VIN < 60V
[d]
VOUT_AC
IOUT = 20A, COUT = 8 x 100µF, 20MHz BW
Output Current
IOUT_DC
[e]
Current Limit
IOUT_CL
Typical current limit based on nominal 230nH inductor.
Maximum Array Size
Output Current, array of 2
Output Current, array of 3
NPARALLEL
0.990
1.005
3.3
4.0
%
0.10
%
76
mVp-p
22
25.3
[b]
IOUT_DC_ARRAY2 Total array capability,
IOUT_DC_ARRAY3 Total array capability,
[b]
see applications section for details
see applications section for details
V
0.10
0
[b]
V
A
A
3
Modules
0
[g]
A
0
[g]
A
27.0
29.1
V
2.08
2.50
V
Protection
Input UVLO Start Threshold
VUVLO_START
Input UVLO Stop Hysteresis
VUVLO_HYS
1.66
1.25
µs
Input OVLO Stop Threshold
VOVLO
62
64.3
V
Input OVLO Start Hysteresis
VOVLO_HYS
0.90
1.17
Input OVLO Response Time
tf
Input UVLO Response Time
Output Overvoltage Protection,
Relative
VOVP_REL
Output Overvoltage Protection,
Absolute
VOVP_ABS
Hysteresis active when OVLO present for at least tFR_DLY
Above set VOUT
4.5
[a]
1.60
V
1.25
µs
20
%
5.2
V
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Page 8 of 41
Rev 2.1
10/2021
PI352x-00
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
470
500
530
kHz
Timing
Switching Frequency
Fault Restart Delay
fs
[f] While
in Discontinuous Conduction Mode (DCM) only,
SYNCI grounded
tFR_DLY
30
ms
Synchronization Input (SYNCI)
Synchronization Frequency Range
fSYNCI
SYNCI Threshold
VSYNCI
–50% and +10% relative to set switching frequency (fS),
while in DCM operating mode only. [c] [f]
250
550
2.5
kHz
V
Synchronization Output (SYNCO)
SYNCO High
VSYNCO_HI
Source 1mA
SYNCO Low
VSYNCO_LO
Sink 1mA
4.5
V
SYNCO Rise Time
tSYNCO_RT
20pF load
10
ns
SYNCO Fall Time
tSYNCO_FT
20pF load
10
ns
0.5
V
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal)
VTRK
0
1.4
V
TRK Enable Threshold
VTRK_OV
20
40
60
mV
TRK to EAIN Offset
VEAIN_OV
40
80
120
mV
ITRK
30
50
70
µA
Charge Current (Soft Start)
Discharge Current (Fault)
ITRK_DIS
TRK Capacitance, Internal
CTRK_INT
Soft-Start Time
tSS
VTRK = 0.5V
8.7
mA
47
CTRK_EXT = 0µF
0.6
0.94
nF
1.6
ms
Error Amplifier Trans-Conductance
GMEAO
[b]
5.1
mS
PSM Skip Threshold
PSMSKIP
[b]
0.6
V
EAIN Capacitance, Internal
CEAIN_INT
56
pF
Error Amplifier Output Impedance
ROUT
[b]
Internal Compensation Capacitor
CHF
[b]
56
pf
RZI
[b]
6
kΩ
Internal Compensation Resistor
1
[a]
MΩ
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Page 9 of 41
Rev 2.1
10/2021
PI352x-00
94
93
92
91
90
89
88
87
86
85
84
83
82
9
8
Power Dissipation (W)
Efficiency (%)
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
2
4
6
8
10
12
14
16
18
20
7
6
5
4
3
2
1
0
22
2
4
6
8
Load Current (A)
VIN:
48V
30V
60V
VIN:
93
8
91
7
89
87
85
83
81
79
16
48V
30V
18
20
22
20
22
20
22
60V
6
5
4
3
2
1
4
6
8
10
12
14
16
18
20
2
22
4
6
8
48V
30V
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
60V
Figure 2 — System efficiency, low trim,
board temperature = 25°C
48V
30V
60V
Figure 5 — System power dissipation, low trim,
board temperature = 25°C
10
94
Power Dissipation (W)
92
Efficiency (%)
14
0
2
VIN:
90
88
86
84
82
80
12
Figure 4 — System power dissipation, nominal trim,
board temperature = 25°C
Power Dissipation (W)
Efficiency (%)
Figure 1 — System efficiency, nominal trim,
board temperature = 25°C
77
10
Load Current (A)
2
4
6
8
10
12
14
16
18
20
8
6
4
2
0
22
2
4
6
30V
Figure 3 — System efficiency, high trim,
board temperature = 25°C
48V
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
8
VIN:
60V
30V
48V
Figure 6 — System power dissipation, high trim,
board temperature = 25°C
ZVS Regulators
Rev 2.1
Page 10 of 41 10/2021
60V
PI352x-00
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
12
Power Dissipation (W)
92
Efficiency (%)
90
88
86
84
82
80
78
2
4
6
8
10
12
14
16
18
20
10
8
6
4
2
0
22
2
4
6
8
Load Current (A)
VIN:
60V
VIN:
Figure 7 — System efficiency, nominal trim,
board temperature = 100°C
16
18
20
22
48V
30V
20
22
20
22
60V
10
Power Dissipation (W)
89
Efficiency (%)
14
Figure 10 — System power dissipation, nominal trim,
board temperature = 100°C
91
87
85
83
81
79
77
2
4
6
8
10
12
14
16
18
20
9
8
7
6
5
4
3
2
1
0
22
2
4
6
8
Load Current (A)
VIN:
10
12
14
16
18
Load Current (A)
48V
30V
60V
VIN:
Figure 8 — System efficiency, low trim,
board temperature = 100°C
48V
30V
60V
Figure 11 — System power dissipation, low trim,
board temperature = 100°C
12
94
Power Dissipation (W)
92
Efficiency (%)
12
Load Current (A)
48V
30V
10
90
88
86
84
82
80
10
8
6
4
2
0
78
2
4
6
8
10
12
14
16
18
20
22
2
4
6
Load Current (A)
VIN:
30V
Figure 9 — System efficiency, high trim,
board temperature = 100°C
48V
8
10
12
14
16
18
Load Current (A)
VIN:
60V
30V
48V
Figure 12 — System power dissipation, high trim,
board temperature = 100°C
ZVS Regulators
Rev 2.1
Page 11 of 41 10/2021
60V
PI352x-00
94
8
92
7
Power Dissipation (W)
Efficiency (%)
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
90
88
86
84
82
6
5
4
3
2
1
0
80
2
4
6
8
10
12
14
16
18
20
2
22
4
6
8
Load Current (A)
VIN:
48V
30V
VIN:
60V
Figure 13 — System efficiency, nominal trim,
board temperature = –40°C
14
16
18
20
22
48V
30V
20
22
20
22
60V
6
Power Dissipation (W)
Efficiency (%)
12
Figure 16 — System power dissipation, nominal trim,
board temperature = –40°C
92
90
88
86
84
82
80
2
4
6
8
10
12
14
16
18
20
5
4
3
2
1
0
22
2
4
6
8
VIN:
48V
30V
10
12
14
16
18
Load Current (A)
Load Current (A)
VIN:
60V
Figure 14 — System efficiency, low trim,
board temperature = –40°C
48V
30V
60V
Figure 17 — System power dissipation, low trim,
board temperature = –40°C
8
Power Dissipation (W)
94
92
Efficiency (%)
10
Load Current (A)
90
88
86
84
82
80
2
4
6
8
10
12
14
16
18
20
7
6
5
4
3
2
1
0
22
2
4
6
Load Current (A)
VIN:
30V
48V
Figure 15 — System efficiency, high trim,
board temperature = –40°C
8
10
12
14
16
18
Load Current (A)
60V
VIN:
30V
48V
Figure 18 — System power dissipation, high trim,
board temperature = –40°C
ZVS Regulators
Rev 2.1
Page 12 of 41 10/2021
60V
PI352x-00
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
Figure 19 — Transient response: 50% to 100% load, at 1A/µs.
Nominal line, nominal trim,
COUT = 8 x 100µF ceramic
Figure 22 — Output short circuit, nominal line
Figure 20 — Output voltage ripple: nominal line, nominal trim,
100% load, COUT = 8 x 100µF ceramic
Figure 23 — Output voltage ripple: nominal line, nominal trim,
50% load, COUT = 8 x 100µF ceramic
Maximum Output Current (A)
600
Frequency (kHz)
500
400
300
200
100
0
1.1
3.3
5.5
7.7
9.9
12.1
14.3
16.5
18.7
20.9
Load Current (A)
30VIN
48VIN
20
15
Notes:
1. SiP is based on VS1 and VIN paths only.
2. Inductor is based on two leads and base
with inclusion of GEL 30 interface
resistance (0.15mm thick; 3.5W/m-K
thermal conductivity).
10
5
0
0
20
40
60
80
100
120
140
Temperature of Isothermal PCB (ºC)
60VIN
Figure 21 — Switching frequency vs. load, nominal trim
25
Figure 24 — System thermal specified operating area: Max IOUT at
nominal trim vs. temperature at locations noted
ZVS Regulators
Rev 2.1
Page 13 of 41 10/2021
PI352x-00
PI3523-00 (3.3VOUT) Electrical Characteristics (Cont.)
Output Current (A)
25
20
15
10
5
0
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
VEAO (V)
30VIN
48VIN
60VIN
Figure 25 — Output current vs. VEAO, nominal trim
Figure 28 — Start up from VIN applied, nominal line, nominal trim,
typical timing, PI3523
18
16
GMOD (S)
14
12
10
8
6
4
2
0
0.6
0.9
1.2
1.5
1.8
2.1
2.4
VEAO (V)
30VIN
48VIN
60VIN
rEQ_OUT (Ω)
Figure 26 — Small signal modulator gain vs. VEAO, nominal trim
20
18
16
14
12
10
8
6
4
2
0
-2
0.6
0.9
1.2
1.5
1.8
2.1
Figure 29 — Start up from EN, VIN pre-applied, nominal line,
nominal trim, typical timing, PI3523
2.4
VEAO (V)
30VIN
48VIN
60VIN
Figure 27 — rEQ_OUT vs VEAO, nominal trim
ZVS Regulators
Rev 2.1
Page 14 of 41 10/2021
PI352x-00
PI3525-00 (5.0VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
30
48
60
V
Input Specifications
Input Voltage
VIN_DC
Input Current
IIN_DC
Input Current At Output Short
(fault condition duty cycle)
IIN_Short
VIN = 48V, TCASE = 25°C, IOUT = 20A
2.28
A
Short at terminals
2.3
mA
Input Quiescent Current
IQ_VIN
Disabled
0.75
Input Quiescent Current
IQ_VIN
Enabled, no load, TCASE = 25°C
2.5
Effective value VIN = 48V, 25°C
0.50
Input Voltage Slew Rate
VIN_SR
Input capacitance, Internal
CIN_INT
1.2
mA
mA
1
V/µs
µF
Output Specifications
EAIN Voltage Total Regulation
Output Voltage Trim Range
VEAIN
VOUT_DC
[b]
0.975
[b] [c]
4.0
Line Regulation
ΔVOUT / ΔVIN
Load Regulation
ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A
Output Voltage Ripple
At 25°C, 30V < VIN < 60V
[d]
VOUT_AC
IOUT = 20A, COUT = 12 x 47µF, 20MHz BW
Output Current
IOUT_DC
[e]
Current Limit
IOUT_CL
Typical current limit based on nominal 230nH inductor.
Maximum Array Size
Output Current, array of 2
Output Current, array of 3
NPARALLEL
0.990
1.005
5.0
6.5
%
0.10
%
75
mVp-p
20
23
[b]
IOUT_DC_ARRAY2 Total array capability,
IOUT_DC_ARRAY3 Total array capability,
[b]
see applications section for details
see applications section for details
V
0.10
0
[b]
V
A
A
3
Modules
0
[g]
A
0
[g]
A
27.0
29.1
V
2.08
2.50
V
Protection
Input UVLO Start Threshold
VUVLO_START
Input UVLO Stop Hysteresis
VUVLO_HYS
1.66
1.25
µs
Input OVLO Stop Threshold
VOVLO
62
64.3
V
Input OVLO Start Hysteresis
VOVLO_HYS
0.90
1.17
Input OVLO Response Time
tf
Input UVLO Response Time
Output Overvoltage Protection,
Relative
VOVP_REL
Output Overvoltage Protection,
Absolute
VOVP_ABS
Hysteresis active when OVLO present for at least tFR_DLY
Above set VOUT
[a]
6.7
1.60
V
1.25
µs
20
%
7.5
V
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Rev 2.1
Page 15 of 41 10/2021
PI352x-00
PI3525-00 (5.0VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
564
600
636
kHz
Timing
Switching Frequency
Fault Restart Delay
fs
[f] While
in Discontinuous Conduction Mode (DCM) only,
SYNCI grounded
tFR_DLY
30
ms
Synchronization Input (SYNCI)
Synchronization Frequency Range
fSYNCI
SYNCI Threshold
VSYNCI
–50% and +10% relative to set switching frequency (fS),
while in DCM operating mode only. [c] [f]
300
660
2.5
kHz
V
Synchronization Output (SYNCO)
SYNCO High
VSYNCO_HI
Source 1mA
4.5
V
SYNCO Low
VSYNCO_LO
Sink 1mA
SYNCO Rise Time
tSYNCO_RT
20pF load
10
ns
SYNCO Fall Time
tSYNCO_FT
20pF load
10
ns
0.5
V
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal)
VTRK
0
TRK Enable Threshold
VTRK_OV
20
TRK to EAIN Offset
VEAIN_OV
ITRK
Charge Current (Soft Start)
Discharge Current (Fault)
ITRK_DIS
TRK Capacitance, Internal
CTRK_INT
Soft-Start Time
tSS
1.4
V
40
60
mV
40
80
120
mV
30
50
70
µA
VTRK = 0.5V
CTRK_EXT = 0µF
Error Amplifier Trans-Conductance
GMEAO
[b]
PSM Skip Threshold
PSMSKIP
[b]
EAIN Capacitance, Internal
CEAIN_INT
0.6
8.7
mA
47
nF
0.94
1.6
ms
7.6
mS
0.8
V
56
pF
Error Amplifier Output Impedance
ROUT
[b]
Internal Compensation Capacitor
CHF
[b]
56
pf
RZI
[b]
5
kΩ
Internal Compensation Resistor
[a]
1
MΩ
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Rev 2.1
Page 16 of 41 10/2021
PI352x-00
96
95
94
93
92
91
90
89
88
87
86
85
Power Dissipation (W)
Efficiency (%)
PI3525-00 (5VOUT) Electrical Characteristics (Cont.)
2
4
6
8
10
12
14
16
18
12
11
10
9
8
7
6
5
4
3
2
1
2
20
4
6
VIN:
30V
48V
VIN:
60V
2
4
6
8
10
12
14
30V
48V
16
18
2
20
4
4
6
8
10
12
6
30V
48V
Efficiency (%)
Figure 32 — System efficiency, high trim,
board temperature = 25°C
16
18
20
48V
18
20
18
20
60V
8
10
12
14
16
48V
30V
60V
Figure 34 — System power dissipation, low trim,
board temperature = 25°C
14
16
18
20
12
11
10
9
8
7
6
5
4
3
2
1
2
4
6
8
10
12
14
16
Load Current (A)
Load Current (A)
VIN:
30V
VIN:
60V
Power Dissipation (W)
2
14
Load Current (A)
Figure 31 — System efficiency, low trim,
board temperature = 25°C
96
95
94
93
92
91
90
89
88
87
86
85
12
12
11
10
9
8
7
6
5
4
3
2
1
Load Current (A)
VIN:
10
Figure 33 — System power dissipation, nominal trim,
board temperature = 25°C
Power Dissipation (W)
Efficiency (%)
Figure 30 — System efficiency, nominal trim,
board temperature = 25°C
96
95
94
93
92
91
90
89
88
87
86
85
8
Load Current (A)
Load Current (A)
VIN:
60V
30V
48V
Figure 35 — System power dissipation, high trim,
board temperature = 25°C
ZVS Regulators
Rev 2.1
Page 17 of 41 10/2021
60V
PI352x-00
96
95
94
93
92
91
90
89
88
87
86
85
Power Dissipation (W)
Efficiency (%)
PI3525-00 (5VOUT) Electrical Characteristics (Cont.)
2
4
6
8
10
12
14
16
18
12
11
10
9
8
7
6
5
4
3
2
1
20
2
4
6
Load Current (A)
VIN:
48V
30V
4
6
8
10
12
14
48V
30V
16
18
20
2
4
4
6
8
10
12
6
30V
14
48V
Efficiency (%)
Efficiency (%)
Figure 38 — System efficiency, high trim,
board temperature = 90°C
20
18
20
18
20
60V
8
10
12
14
16
48V
30V
60V
Figure 40 — System power dissipation, low trim,
board temperature = 90°C
16
18
20
12
11
10
9
8
7
6
5
4
3
2
1
2
4
6
Load Current (A)
VIN:
18
Load Current (A)
Power Dissipation (W)
2
16
48V
30V
VIN:
60V
Figure 37 — System efficiency, low trim,
board temperature = 90°C
96
95
94
93
92
91
90
89
88
87
86
85
14
12
11
10
9
8
7
6
5
4
3
2
1
Load Current (A)
VIN:
12
Figure 39 — System power dissipation, nominal trim,
board temperature = 90°C
Power Dissipation (W)
2
10
Load Current (A)
VIN:
60V
Figure 36 — System efficiency, nominal trim,
board temperature = 90°C
96
95
94
93
92
91
90
89
88
87
86
85
8
8
10
12
14
16
Load Current (A)
VIN:
60V
30V
48V
Figure 41 — System power dissipation, high trim,
board temperature = 90°C
ZVS Regulators
Rev 2.1
Page 18 of 41 10/2021
60V
PI352x-00
96
95
94
93
92
91
90
89
88
87
86
85
Power Dissipation (W)
Efficiency (%)
PI3525-00 (5VOUT) Electrical Characteristics (Cont.)
2
4
6
8
10
12
14
16
18
12
11
10
9
8
7
6
5
4
3
2
1
20
2
4
6
Load Current (A)
VIN:
30V
48V
VIN:
4
6
8
10
12
14
30V
48V
16
18
20
2
4
4
6
8
10
12
6
30V
48V
Efficiency (%)
Efficiency (%)
Figure 44 — System efficiency, high trim,
board temperature = –40°C
18
20
48V
18
20
18
20
60V
8
10
12
14
16
30V
48V
60V
Figure 46 — System power dissipation, low trim,
board temperature = –40°C
14
16
18
20
12
11
10
9
8
7
6
5
4
3
2
1
2
4
6
Load Current (A)
VIN:
30V
VIN:
60V
Power Dissipation (W)
2
16
Load Current (A)
Figure 43 — System efficiency, low trim,
board temperature = –40°C
96
95
94
93
92
91
90
89
88
87
86
85
14
12
11
10
9
8
7
6
5
4
3
2
1
Load Current (A)
VIN:
12
Figure 45 — System power dissipation, nominal trim,
board temperature = –40°C
Power Dissipation (W)
2
10
Load Current (A)
60V
Figure 42 — System efficiency, nominal trim,
board temperature = –40°C
96
95
94
93
92
91
90
89
88
87
86
85
8
8
10
12
14
16
Load Current (A)
60V
VIN:
30V
48V
Figure 47 — System power dissipation, high trim,
board temperature = –40°C
ZVS Regulators
Rev 2.1
Page 19 of 41 10/2021
60V
PI352x-00
PI3525-00 (5VOUT) Electrical Characteristics (Cont.)
Figure 49 — Output voltage ripple: nominal line, nominal trim,
100% load, COUT = 12 x 47µF ceramic
Figure 52 — Output voltage ripple: nominal line, nominal trim,
50% load, COUT = 12 x 47µF ceramic
625
600
575
550
525
500
475
450
425
400
375
350
325
300
0
2
4
6
8
10
12
14
16
18
Maximum Output Current (A)
Figure 51 — Output short circuit, nominal line
Frequency (kHz)
Figure 48 — Transient response: 50% to 100% load, at 1A/µs.
Nominal line, nominal trim,
COUT = 12 x 47µF ceramic
20
Load Current (A)
30VIN
48VIN
18
16
14
12
10
8
6
4
2
0
Note:
SiP is based on VIN and VS1 paths
only. Inductor is based on base with
inclusion of GEL 30 interface
resistance (0.15mm thick; 3.5W/m-K
thermal conductivity), and all leads.
25
50
75
100
125
Temperature of Isothermal SiP VIN and VS1 pins,
and PCB at Inductor (ºC)
60VIN
Figure 50 — Switching frequency vs. load, nominal trim
22
20
Figure 53 — System thermal specified operating area: Max IOUT at
nominal trim vs. temperature at locations noted
ZVS Regulators
Rev 2.1
Page 20 of 41 10/2021
PI352x-00
PI3525-00 (5VOUT) Electrical Characteristics (Cont.)
20
Output Current (A)
18
16
14
12
10
8
6
4
2
0.8
1.3
1.8
2.3
2.8
VEAO (V)
30VIN
48VIN
60VIN
Figure 54 — Output current vs. VEAO, nominal trim
Figure 57 — Start up from VIN applied, nominal line, nominal trim,
typical timing, PI3525
20
18
16
GMOD (S)
14
12
10
8
6
4
2
0
0.8
1
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
VEAO (V)
48VIN
30VIN
60VIN
Figure 55 — Small signal modulator gain vs. VEAO, nominal trim
Figure 58 — Start up from EN, VIN pre-applied, nominal line,
nominal trim, typical timing, PI3525
25
rEQ_OUT (Ω)
20
15
10
5
0
0.8
1.2
1.6
2.0
2.4
2.8
VEAO (V)
30VIN
48VIN
60VIN
Figure 56 — rEQ_OUT vs VEAO, nominal trim
ZVS Regulators
Rev 2.1
Page 21 of 41 10/2021
PI352x-00
PI3526-00 (12VOUT) Electrical Characteristics
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
30
48
60
V
Input Specifications
Input Voltage
VIN_DC
Input Current
IIN_DC
Input Current At Output Short
(fault condition duty cycle)
IIN_Short
VIN = 48V, TCASE = 25°C, IOUT = 18A
4.68
A
Short at terminals
4.5
mA
Input Quiescent Current
IQ_VIN
Disabled
0.75
Input Quiescent Current
IQ_VIN
Enabled, no load, TCASE = 25°C
3.2
Effective value VIN = 48V, 25°C
0.50
Input Voltage Slew Rate
VIN_SR
Input capacitance, Internal
CIN_INT
1.2
mA
mA
1
V/µs
µF
Output Specifications
EAIN Voltage Total Regulation
Output Voltage Trim Range
VEAIN
VOUT_DC
[b]
0.975
[b] [c]
6.5
Line Regulation
ΔVOUT / ΔVIN
Load Regulation
ΔVOUT / ΔIOUT At 25°C, 2A < IOUT < 20A
Output Voltage Ripple
At 25°C, 30V < VIN < 60V
[d]
VOUT_AC
IOUT = 18A, COUT = 8 x 10µF, 20MHz BW
Output Current
IOUT_DC
[e]
Current Limit
IOUT_CL
Typical current limit based on nominal 480nH inductor.
Maximum Array Size
Output Current, array of 2
Output Current, array of 3
NPARALLEL
0.990
1.005
12
14
%
0.10
%
240
mVp-p
18
20.7
[b]
IOUT_DC_ARRAY2 Total array capability,
IOUT_DC_ARRAY3 Total array capability,
[b]
see applications section for details
see applications section for details
V
0.10
0
[b]
V
A
A
3
Modules
0
[g]
A
0
[g]
A
27
29.1
V
2.08
2.50
V
Protection
Input UVLO Start Threshold
VUVLO_START
Input UVLO Stop Hysteresis
VUVLO_HYS
1.66
1.25
µs
Input OVLO Stop Threshold
VOVLO
62
64.3
V
Input OVLO Start Hysteresis
VOVLO_HYS
0.90
1.17
Input OVLO Response Time
tf
Input UVLO Response Time
Output Overvoltage Protection,
Relative
VOVP_REL
Output Overvoltage Protection,
Absolute
VOVP_ABS
Hysteresis active when OVLO present for at least tFR_DLY
Above set VOUT
[a]
14.6
1.60
V
1.25
µs
20
%
15.7
V
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Rev 2.1
Page 22 of 41 10/2021
PI352x-00
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
Specifications apply for –40°C < TINT < 120°C, VIN = 48V, EN = High, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
658
700
742
kHz
Timing
Switching Frequency
Fault Restart Delay
fs
[f] While
in DCM operating mode only, SYNCI grounded
tFR_DLY
30
ms
Synchronization Input (SYNCI)
Synchronization Frequency Range
fSYNCI
SYNCI Threshold
VSYNCI
–50% and +10% relative to set switching frequency (fS),
while in DCM operating mode only. [c] [f]
350
770
2.5
kHz
V
Synchronization Output (SYNCO)
SYNCO High
VSYNCO_HI
Source 1mA
4.5
V
SYNCO Low
VSYNCO_LO
Sink 1mA
SYNCO Rise Time
tSYNCO_RT
20pF load
10
ns
SYNCO Fall Time
tSYNCO_FT
20pF load
10
ns
0.5
V
Soft Start, Tracking and Error Amplifier
TRK Active Range (Nominal)
VTRK
0
TRK Enable Threshold
VTRK_OV
20
TRK to EAIN Offset
VEAIN_OV
ITRK
Charge Current (Soft Start)
Discharge Current (Fault)
ITRK_DIS
TRK Capacitance, Internal
CTRK_INT
Soft-Start Time
tSS
1.4
V
40
60
mV
40
80
120
mV
30
50
70
µA
VTRK = 0.5V
CTRK_EXT = 0µF
Error Amplifier Trans-Conductance
GMEAO
[b]
PSM Skip Threshold
PSMSKIP
[b]
EAIN Capacitance, Internal
CEAIN-INT
0.6
8.7
mA
47
nF
0.94
1.6
ms
7.6
mS
0.8
V
56
pF
Error Amplifier Output Impedance
ROUT
[b]
Internal Compensation Capacitor
CHF
[b]
56
pf
RZI
[b]
5
kΩ
Internal Compensation Resistor
[a]
1
MΩ
All parameters reflect regulator and inductor system performance. Measurements were made using a standard PI352x-00 evaluation board with 3 x 3"
dimensions and 4 layer, 2oz copper. Refer to inductor pairing table within Application Description section for specific inductor manufacturer and value.
[b] Regulator is assured to meet performance specifications by design, test correlation, characterization, and/or statistical process control.
Output voltage is determined by an external feedback divider ratio.
[c] Output current capability may be limited and other performance may vary from noted electrical characteristics when V
OUT is not set to nominal.
[d] Refer to Output Ripple plots.
[e] Refer to Load Current vs. Ambient Temperature curves.
[f] Refer to Switching Frequency vs. Load current curves.
[g] Contact factory applications for array derating and layout best practices to minimize sharing errors.
ZVS Regulators
Rev 2.1
Page 23 of 41 10/2021
PI352x-00
98
10
97
9
Power Dissipation (W)
Efficiency (%)
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
96
95
94
93
92
91
8
7
6
5
4
3
2
1
0
90
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
Load Current (A)
VIN:
48V
30V
VIN:
10.8
12.6
14.4
16.2
18
48V
30V
60V
Figure 62 — System power dissipation, nominal trim,
board temperature = 25°C
97
8
Power Dissipation (W)
96
Efficiency (%)
9
Load Current (A)
60V
Figure 59 — System efficiency, nominal trim,
board temperature = 25°C
95
94
93
92
91
90
89
7
6
5
4
3
2
1
0
88
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
48V
30V
7.2
9
10.8
12.6
14.4
16.2
18
Load Current (A)
Load Current (A)
VIN:
VIN:
60V
Figure 60 — System efficiency, low trim,
board temperature = 25°C
48V
30V
60V
Figure 63 — System power dissipation, low trim,
board temperature = 25°C
98
12
Power Dissipation (W)
97
Efficiency (%)
7.2
96
95
94
93
92
91
10
8
6
4
2
0
90
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
30V
48V
Figure 61 — System efficiency, high trim,
board temperature = 25°C
9
10.8
12.6
14.4
Load Current (A)
Load Current (A)
VIN:
7.2
VIN:
60V
30V
48V
Figure 64 — System power dissipation, high trim,
board temperature = 25°C
ZVS Regulators
Rev 2.1
Page 24 of 41 10/2021
60V
16.2
18
PI352x-00
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
14
97
12
Power Dissipation (W)
98
Efficiency (%)
96
95
94
93
92
91
90
10
89
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
8
6
4
2
0
18
1.8
3.6
5.4
Load Current (A)
VIN:
48V
30V
60V
VIN:
10.8
12.6
14.4
16.2
18
48V
30V
60V
Figure 68 — System power dissipation, nominal trim,
board temperature = 100°C
96
10
Power Dissipation (W)
95
94
Efficiency (%)
9
Load Current (A)
Figure 65 — System efficiency, nominal trim,
board temperature = 100°C
93
92
91
90
89
88
87
9
8
7
6
5
4
3
2
1
0
86
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
48V
30V
7.2
9
10.8
12.6
14.4
16.2
18
Load Current (A)
Load Current (A)
VIN:
VIN:
60V
Figure 66 — System efficiency, low trim,
board temperature = 100°C
48V
30V
60V
Figure 69 — System power dissipation, low trim,
board temperature = 100°C
98
14
Power Dissipation (W)
97
96
Efficiency (%)
7.2
95
94
93
92
91
90
12
10
8
6
4
2
0
89
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
30V
48V
Figure 67 — System efficiency, high trim,
board temperature = 100°C
9
10.8
12.6
14.4
Load Current (A)
Load Current (A)
VIN:
7.2
VIN:
60V
30V
48V
60V
Figure 70 — System power dissipation, high trim,
board temperature = 100°C
ZVS Regulators
Rev 2.1
Page 25 of 41 10/2021
16.2
18
PI352x-00
98
9
97
8
Power Dissipation (W)
Efficiency (%)
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
96
95
94
93
92
91
90
89
7
6
5
4
3
2
1
0
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
Load Current (A)
VIN:
30V
48V
60V
VIN:
10.8
12.6
14.4
16.2
18
48V
30V
60V
Figure 74 — System power dissipation, nominal trim,
board temperature = –40°C
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
7
Power Dissipation (W)
Efficiency (%)
9
Load Current (A)
Figure 71 — System efficiency, nominal trim,
board temperature = –40°C
6
5
4
3
2
1
0
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
48V
30V
7.2
9
10.8
12.6
14.4
16.2
18
Load Current (A)
Load Current (A)
VIN:
VIN:
60V
Figure 72 — System efficiency, low trim,
board temperature = –40°C
48V
30V
60V
Figure 75 — System power dissipation, low trim,
board temperature = –40°C
10
98
9
Power Dissipation (W)
99
97
Efficiency (%)
7.2
96
95
94
93
92
91
8
7
6
5
4
3
2
1
0
90
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
1.8
18
3.6
5.4
30V
48V
Figure 73 — System efficiency, high trim,
board temperature = –40°C
9
10.8
12.6
14.4
Load Current (A)
Load Current (A)
VIN:
7.2
VIN:
60V
30V
48V
60V
Figure 76 — System power dissipation, high trim,
board temperature = –40°C
ZVS Regulators
Rev 2.1
Page 26 of 41 10/2021
16.2
18
PI352x-00
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
Figure 77 — Transient response: 50% to 100% load, at 1A/µs.
nominal line, nominal trim,
COUT = 8 x 10µF ceramic
Figure 80 — Output short circuit, nominal line
Figure 78 — Output voltage ripple: nominal line, nominal trim,
100% load, COUT = 8 x 10µF ceramic
Figure 81 — Output voltage ripple: nominal line, nominal trim,
50% load, COUT = 8 x 10µF ceramic
Maximum Output Current (A)
Frequency (kHz)
725
650
575
500
425
350
1.8
3.6
5.4
7.2
9
10.8
12.6
14.4
16.2
18
Load Current (A)
30VIN
48VIN
18
16
14
12
Note:
SiP is based on VIN and VS1 paths
only. Inductor is based on base with
inclusion of GEL 30 interface
resistance (0.15mm thick; 3.5W/m-K
thermal conductivity), and all leads.
10
8
6
4
2
0
25
50
75
100
125
Temperature of Isothermal SiP VIN and VS1 pins,
and PCB at Inductor (ºC)
60VIN
Figure 79 — Switching frequency vs. load, nominal trim
20
Figure 82 — System thermal specified operating area: max IOUT at
nominal trim vs. temperature at locations noted
ZVS Regulators
Rev 2.1
Page 27 of 41 10/2021
PI352x-00
PI3526-00 (12VOUT) Electrical Characteristics (Cont.)
Output Current (A)
25
20
15
10
5
0
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
VEAO (V)
48VIN
30VIN
60VIN
Figure 83 — Output current vs. VEAO, nominal trim
Figure 86 — Start up from VIN applied, nominal line, nominal trim,
typical timing, PI3526
14
12
GMOD (S)
10
8
6
4
2
0
0.8
1
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
2.8
VEAO (V)
30VIN
48VIN
60VIN
Figure 84 — Small signal modulator gain vs. VEAO, nominal trim
Figure 87 — Start up from EN, VIN pre-applied, nominal line,
nominal trim, typical timing, PI3526
35
30
rEQ_OUT (Ω)
25
20
15
10
5
0
0.8
1.3
1.8
2.3
2.8
VEAO (V)
30VIN
48VIN
60VIN
Figure 85 — rEQ_OUT vs VEAO, nominal trim
ZVS Regulators
Rev 2.1
Page 28 of 41 10/2021
PI352x-00
Functional Description
Soft Start
The PI352x-00 is a family of highly integrated ZVS Buck
regulators. The PI352x-00 has an output voltage that can be set
within a prescribed range shown in Table 1. Performance and
maximum output current are characterized with a specific external
power inductor (see Table 3).
The PI352x-00 includes an internal soft-start capacitor to
control the rate of rise of the output voltage. See the Electrical
Characteristics Section for the default value. Connecting an
external capacitor from the TRK pin to SGND will increase the
start-up ramp period. See, “Soft Start Adjustment and Track,” in
the Applications Description section for more details.
Output Voltage Selection
L1
VIN
VIN
CIN
PGND
ZVS-Buck VOUT
VDR
SYNCO
SYNCI
PWRGD
EN
TESTx
VOUT
VS1
COUT
VSP
VSN
VDIFF
The PI352x-00 output voltage is set with REA1 and REA2 as
shown in Figure 88. Table 1 defines the allowable operational
voltage ranges for the PI352x-00 family. Refer to the Output
Voltage Set Point Application Description for details.
REA1
TRK
Output Voltage
EAIN
EAO
Device
REA2
COMP
Nominal
Range
PI3523-00
3.3V
2.2 – 4.0V
PI3525-00
5.0V
4.0 – 6.5V
PI3526-00
12V
6.5 – 14V
SGND
CCOMP
Figure 88 — ZVS buck with required components
For basic operation, Figure 88 shows the connections
and components required. No additional design or
settings are required.
ENABLE (EN)
EN is the enable pin of the converter. The EN Pin is referenced to
SGND and permits the user to turn the regulator on or off. The
EN default polarity is a positive logic assertion. If the EN pin is
left floating or asserted high, the converter output is enabled.
Pulling EN pin below VEN_LO with respect to SGND will disable the
regulator output.
Remote Sensing
If remote sensing is required, the PI352x-00 product family
is equipped with a general purpose op-amp. This amplifier
can allow full differential remote sense by configuring it
as a differential follower and connecting the VDIFF pin
to the EAIN pin.
Table 1 — PI352x-00 family output voltage ranges
Output Current Limit Protection
The PI352x-00 has a current limit protection, which prevents
the output from sourcing current higher than the regulator’s
maximum rated current. If the output current exceeds the
Current Limit (IOUT_CL) for 1024μs, a slow current limit fault is
initiated and the regulator is shutdown which eliminates output
current flow. After Fault Restart Delay (tFR_DLY ), a soft-start cycle
is initiated. This restart cycle will be repeated indefinitely until the
excessive load is removed.
The PI352x-00 also has short circuit protection which can
immediately stop switching to protect against catastrophic failure
of an external component such as a saturated inductor. If short
circuit protection is triggered the PI352x-00 will complete the
current cycle and stop switching. The module will attempt to soft
start after Fault Restart Delay (tFR_DLY ).
Input Undervoltage Lockout
If VIN falls below the input Undervoltage Lockout (UVLO)
threshold, but remains high enough to power the internal bias
supply, the PI352x-00 will complete the current cycle and stop
switching. The system will soft start once the input voltage is
reestablished and after the Fault Restart Delay.
ZVS Regulators
Rev 2.1
Page 29 of 41 10/2021
PI352x-00
Input Overvoltage Lockout
Pulse Skip Mode (PSM)
If VIN exceeds the input Overvoltage Lockout (OVLO) threshold
(VOVLO), while the controller is running, the PI352x-00 will
complete the current cycle and stop switching. If VIN remains
above OVLO for at least tFR_DLY, then the input voltage is
considered reestablished once VIN goes below VOVLO – VOVLO_HYS.
If VIN goes below OVLO before tFR_DLY elapses, then the input
voltage is considered reestablished once VIN goes below VOVLO.
The system will soft start once the input voltage is reestablished
and after the Fault Restart Delay.
PI352x-00 features a Pulse Skip Mode (PSM) to achieve high
efficiency at light loads. The regulators are setup to skip pulses
if EAO falls below a PSM threshold (PSMSKIP). Depending on
conditions and component values, this may result in single pulses
or several consecutive pulses followed by skipped pulses. Skipping
cycles significantly reduces gate drive power and improves light
load efficiency. The regulator will leave PSM once the EAO rises
above the Pulse Skip Mode threshold.
Output Overvoltage Protection
The PI352x-00 family is equipped with output Overvoltage
Protection (OVP) to prevent damage to input voltage sensitive
devices. If the output voltage exceeds VOVP-REL or VOVP-ABS, the
regulator will complete the current cycle and stop switching. The
system will resume operation once the output voltage falls below
the OVP threshold and after Fault Restart Delay.
Overtemperature Protection
The PI352x-00 features an over temperature protection (OTP),
which will not engage until after the product is operated
above the maximum rated temperature. The OTP circuit is only
designed to protect against catastrophic failure due to excessive
temperatures and should not be relied upon to ensure the device
stays within the recommended operating temperature range.
Thermal shutdown terminates switching and discharges the
soft-start capacitor. The PI352x-00 will restart after the excessive
temperature has decreased by 30°C
Variable Frequency Operation
Each PI352x-00 is preprogrammed to a base operating frequency,
with respect to the power stage inductor (see Table 2), to operate
at peak efficiency across line and load variations. At low line
and high load applications, the base frequency will decrease to
accommodate these extreme operating ranges. By stretching
the frequency, the ZVS operation is preserved throughout
the total input line voltage range therefore maintaining
optimum efficiency.
Thermal Characteristics
Figure 89(a) and 89(c) thermal impedance models that can predict
the maximum temperature of the hottest component for a given
operating condition. This model assumes that all customer PCB
connections are at one temperature, which is PCB equivalent
Temperature TPCB °C.
The SiP model can be simplified as shown in Figure 89(b). which
assumes all PCB nodes are at the same temperature.
ZVS Regulators
Rev 2.1
Page 30 of 41 10/2021
PI352x-00
Maximum SiP Internal Temperature
TINT ( oC )
SiP Power
Dissipa on
PDSiP (W)
Thermal Resistance
SiP Case Top
θINT-TOP oC / W
SiP Case Top
Temperature
TTOP oC
Thermal Resistances θINT-VIN
o
SiP PCB Pads
C/W
SiP PCB Pad
Temperatures
TVIN
o
C
θINT-VS1
o
C/W
θINT-PGND1
o
C/W
θINT-PGND2
o
C/W
θINT-SGND
o
C/W
TVS1
o
C
TPGND1
o
C
TPGND2
o
C
TSGND
o
C
(a)
Maximum SiP Internal Temperature
TINT ( oC )
SiP Power
Dissipa on
PDSIP (W)
Thermal Resistance
SiP Case Top
θINT-TOP oC / W
Thermal Resistance
SiP PCB Equivalent
θ INT-PCB oC / W
Case Top
Temperature
TTOP oC
SiP PCB Common
Temperature
TPCB oC
(b)
Maximum Inductor Internal Temperature
TINT ( oC )
Inductor Power
Dissipa on
PDIND (W)
Thermal Resistance
Inductor Case Top
θINT-TOP oC / W
Thermal Resistance
Inductor Case Bo om
θINT-BOTTOM oC / W
Inductor Case Top
Temperature
TTOP oC
Inductor Case Bo om
Temperature
TBOTTOM oC
Thermal Resistances θINT-LEAD1
o
Inductor PCB Pads
C/W
Inductor PCB Pad
Temperatures
(c)
Figure 89 — PI352x-00 thermal model (a), SiP simplified version (b) and inductor thermal model (c)
ZVS Regulators
Rev 2.1
Page 31 of 41 10/2021
TVS1
o
C
θINT-LEAD2
o
C/W
θINT-TAB
o
C/W
TVOUT
o
C
TTAB
o
C
PI352x-00
Where the symbol in Figure 89(a) and (b) is defined as the following:
θINT-TOP
the thermal impedance from the hottest component inside the SiP to the top side
θINT-PCB
the thermal impedance from the hottest component inside the SiP to the customer PCB, assuming all pins are
at one temperature.
θINT-VIN
the thermal impedance from the hottest component inside the SiP to the circuit board VIN pads.
θINT-VS1
the thermal impedance from the hottest component inside the SiP to the circuit board VS1 pads.
θINT-PGND1
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND1 pads.
PGND1 is pins 12A-K.
θINT-PGND2
the thermal impedance from the hottest component inside the SiP to the circuit board at the PGND2 pads .
PGND2 is pins 2F-J, 3F-J, 4C-J, 5B-J and 6C-K.
θINT-SGND
the thermal impedance from the hottest component inside the SiP to the circuit board at the SGND pads.
Where the symbol in Figure 89(c) is defined as the following:
θINT-TOP
the thermal impedance from the hot spot to the top surface of the core.
θINT-BOT
the thermal impedance from the hot spot to the bottom surface of the core.
θINT-TAB
the thermal impedance from the hot spot to the metal mounting tab on the core body, if applicable.
θINT-LEAD1
the thermal impedance from the hot spot to one of the mounting leads.
Since the leads are the same thermal impedance, there is no need to specify by explicit pin number.
θINT-LEAD2
the thermal impedance from the hot spot to the other mounting lead.
The following equation can predict the junction temperature
based on the heat load applied to the SiP and the known ambient
conditions with the simplified thermal circuit model:
TINT =
PD +
TTOP
θINT-TOP
1
+
θINT-TOP
Product
System
+
TPCB
θINT-PCB
1
(1)
θINT-PCB
Simplified SiP
Thermal Impedances
Detailed SiP Thermal Impedances
θINT-TOP
(°C / W)
θINT-PCB
(°C / W)
θINT-TOP
(°C / W)
θINT-VIN
(°C / W)
θINT-VS1
(°C / W)
θINT-PGND1
(°C / W)
θINT-PGND2
(°C / W)
θINT-SGND
(°C / W)
PI3523-00
70
0.98
70
3.4
1.7
9.8
27
87
PI3525-00
69
1.5
69
3.3
3.8
23
20
59
PI3526-00
110
1.8
110
3.4
5.8
24
27
86
Table 2 — PI352x-00 SiP Thermal Impedance
Product
System
Inductor Part
Number
Effective Thermal Impedances
θINT-TOP
θINT-LEAD1, θINT-LEAD2
θINT-BOTTOM
θINT-TAB
(°C / W)
(°C / W)
(°C / W)
(°C / W)
PI3523-00
FP2207R1-R230-R
11
9.4
6.9
n/a
PI3525-00
FP2207R1-R230-R
8.8
9.5
6.0
n/a
PI3526-00
HCV1707R1-R48-R
65
18
20
700
Table 3 — Inductor effective thermal model parameters
ZVS Regulators
Rev 2.1
Page 32 of 41 10/2021
PI352x-00
SiP Dissipation (% Total Loss)
SiP Power Dissipation as Percentage of Total System Losses
100
95
90
85
80
75
70
65
60
55
50
30
35
40
45
50
55
60
VIN (V)
IOUT:
工商网监
湘ICP备2023018690号
