ZVS Regulators
PI3740-00
8V – 60VIN , 10V – 50VOUT , 50 – 140W ZVS Buck-Boost Regulator
Product Description
Features & Benefits
The PI3740-00 is a high-efficiency, wide input and output
range DC-DC ZVS Buck-Boost Regulator. This high-density
System‑in‑Package (SiP) integrates controller, power switches,
and support components. The integration of a high-performance
Zero‑Voltage Switching (ZVS) topology within the PI3740-00
increases point-of-load performance, providing best-in-class
power efficiency.
• Up to 96% efficiency
• 50 – 140W continuous output power
• Parallel-capable with single-wire current sharing
• External frequency synchronization / interleaving
• High-side current sense amplifier
• General-purpose amplifier
The PI3740-00 requires an external inductor, resistive divider and
minimal capacitors to form a complete DC-DC switching mode
buck-boost regulator.
Device
PI3740-00
• Lighting / constant current mode (LGH)
• Input over / undervoltage lockout (OVLO / UVLO)
• Output overvoltage protection (OVP)
Output Voltage
Set
Range
12V
10 – 50V
• Overtemperature protection (OTP)
• Fast and slow current limits
• –40 to 115°C operating range (TJ), -LGIZ
• –55 to 115°C operating range (TJ), -LGMZ
The ZVS architecture also enables high-frequency operation while
minimizing switching losses and maximizing efficiency. The high
switching frequency operation reduces the size of the external
filtering components, improves power density and enables fast
dynamic response to line and load transients.
• Excellent light-load efficiency
Applications
• Battery Charging and Conditioning, Telecom,
Networking, Lighting
• Computing, Communications, Industrial,
Automotive Accessories
• 12, 24, 48 and 60V DC–DC Applications
Package Information
• 10 x 14 x 2.56mm LGA SiP
Typical Application
VS1
VIN
CIN
VS2 VOUT
PGND
PGND
ISP
COUT
R1
R2
ISN
VDR
10k
PI3740-00
IMON
VSN
VSP
PGD
VDIFF
EN
LGH
SYNCO
EAIN
SYNCI
TRK
EAO
SGND
CCOMP
CTRK
ZVS Regulators
Page 1 of 49
COMP
Rev 2.8
10/2021
CHF
PI3740-00
Contents
Order Information
3
Absolute Maximum Ratings
3
Output Voltage Trim
22
Pin Description
4
Soft Start Adjustment and Tracking
22
Package Pin-Out
5
Inductor Pairing
22
Large Pin Blocks
5
Filter Considerations
23
Storage and Handling Information
6
PI3740-00 Maximum COUT Capability at Start Up
26
Block Diagram
6
Thermal Design
27
PI3740-00 Electrical Characteristics
7
Thermal Design Inductor
29
PI3740-00 Performance Characteristics
11
Application Description
22
PI3740-00 Percentage of SiP Loss to Total Loss
31
MTBF 19
Evaluation Board Thermal De-rating
33
Functional Description
20
Parallel Operation
35
Enable
20
Synchronization 35
Switching Frequency Synchronization
20
Interleaving 35
Soft Start and Tracking
20
Small-Signal Models CV-CC Modes
Remote Sensing Differential Amplifier
20
Small-Signal Model – Constant Voltage Mode
36
Power Good
20
Error Amplifier
36
Output Current Limit Protection
20
Lighting Mode (LGH)
36
Input Undervoltage Lockout
20
LGH Amplifier Small-Signal Model
37
Input Overvoltage Lockout
20
VDR Bias Regulator
37
Output Overvoltage Protection
21
PI3740-00 Modulator Gain / Output Resistance
38
Overtemperature Protection
21
System Design Considerations
45
Pulse Skip Mode (PSM)
21
LGA Package Drawings
46
Variable Frequency Operation
21
LGA Receiving PCB Pattern Design Recommendations
47
IMON Amplifier
21
Revision History
48
36
Warranty 49
ZVS Regulators
Page 2 of 49
Rev 2.8
10/2021
PI3740-00
Order Information
Part Number
Description
PI3740-00-LGIZ
VIN 8 – 60V, VOUT 10 – 50V
–40 to 115°C Temperature Range
PI3740-00-LGMZ
VIN 8 – 60V, VOUT 10 – 50V
–55 to 115°C Temperature Range
Package
Transport Media
10 x 14mm 108-pin LGA
TRAY
Absolute Maximum Ratings
Note: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the
Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted.
Location
Name
VMAX
VMIN
ISOURCE
[b]
40A [b]
1 – 2, G – K
VIN
75V
–0.7V
4 – 5, G – K
VS1
75V
–0.7VDC [a]
40A [b]
18A [b]
10 – 11, G – K
VS2
75V
–0.7VDC [a]
40A [b]
18A [b]
13 – 14, G – K
VOUT
75V
–0.7VDC
40A [b]
40A [b]
1E
VDR
5.5V
–0.3V
30mA
200mA
1D
PGD
5.5V
–0.3V
20mA
20mA
1C
SYNCO
5.5V
–0.3V
5mA
5mA
1B
SYNCI
5.5V
–0.3V
5mA
5mA
1A
FT1
5.5V
–0.3V
5mA
5mA
2A
FT2
5.5V
–0.3V
5mA
5mA
3A
FT3
5.5V
–0.3V
5mA
5mA
4A
FT4
5.5V
–0.3V
10mA
10mA
5A
EN
5.5V
–0.3V
5mA
5mA
6A
TRK
5.5V
–0.3V
50mA
50mA
7A
LGH
5.5V
–0.3V
5mA
5mA
8A
COMP
5.5V
–0.3V
5mA
5mA
9A
VSN
5.5V
–1.5V
5mA
5mA
10A
VSP
5.5V
–1.5V
5mA
5mA
11A
VDIFF
5.5V
–0.5V
5mA
5mA
12A
EAIN
5.5V
–0.3V
5mA
5mA
13A
EAO
5.5V
–0.3V
5mA
5mA
14A
IMON
5.5V
–0.3V
5mA
5mA
14D
ISN [c]
75V
–2VDC
5mA
5mA
14E
ISP [c]
75V
–2VDC
5mA
5mA
10 – 14, B + 10 – 12, C – E
SGND
0.3V
–0.3V
200mA
200mA
2 – 9, B – E + 7 – 8, F – K
PGND
N/A
N/A
18A [b]
18A [b]
[a]
Transient VS1 voltages are guaranteed by design when the specified 420nH ±10% inductor is used.
Non-Operating Test Mode Limits.
[c] The ISP pin to ISN pin has a maximum differential limit of +5.5V
DC and –0.5VDC.
[b]
ZVS Regulators
Page 3 of 49
Rev 2.8
10/2021
40A
ISINK
PI3740-00
Pin Description
Pin Number
Pin Name
1–2, G–K
VIN
Input voltage and sense node for UVLO, OVLO and feed forward compensation.
Description
4–5, G–K
VS1
Input side switching node and ZVS sense node for power switches.
10–11, G–K
VS2
Output side switching node and ZVS sense node for power switches.
13–14, G–K
VOUT
1E
VDR
Internal 5.1V supply for gate drivers and internal logic. May be used as reference or low power bias supply
for up to 2mA. Must be impedance limited by the user.
1D
PGD
Fault & Power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less
than 1.4V.
1C
SYNCO
Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning
of each switching cycle, for synchronization of other regulators.
1B
SYNCI
Synchronization input. When a falling edge synchronization pulse is detected, the PI3740-00 will delay
the start of the next switching cycle until the next falling edge sync pulse arrives, up to a maximum delay
of two times the programmed switching period. If the next pulse does not arrive within two times the
programmed switching period, the controller will leave sync mode and start a switching cycle automatically.
Connect to SGND when not in use.
1A
FT1
For factory use only. Connect to SGND or leave floating in application.
2A
FT2
For factory use only. Connect to SGND or leave floating in application.
3A
FT3
For factory use only. Connect to SGND in application.
4A
FT4
For factory use only. Connect to SGND in application.
5A
EN
Regulator Enable control. Asserted high or left floating – regulator enabled;
Asserted low, regulator output disabled.
6A
TRK
Soft-start and track input. An external capacitor must be connected between TRK pin and SGND to
decrease the rate of output rise during soft start. Recommended value is 47nF for 1.6ms rise.
7A
LGH
Input for constant current lighting amplifier. Connect to SGND if not in use.
8A
COMP
9A
VSN
General purpose amplifier inverting input.
10A
VSP
General purpose amplifier non-inverting input.
11A
VDIFF
General Purpose amplifier output. When unused connect VDIFF to VSN and VSP to SGND.
12A
EAIN
Error amplifier inverting input and sense for PGD. Connect by resistive divider to the output.
13A
EAO
Error amp output: External connection for additional compensation and current sharing. Add 56pF
capacitor from EAO to SGND.
14A
IMON
14D
ISN
High side current sense amplifier negative input.
14E
ISP
High side current sense amplifier positive input.
10 – 14, B + 10 – 12, C – E
SGND
Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected
within the regulator package.
2 – 9, B – E + 7 – 8, F – K
PGND
Power ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the
regulator package.
ZVS Regulators
Page 4 of 49
Output voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV
and internal signals.
Error amp compensation dominant pole. Connect a capacitor of 4700pF by default between COMP and
SGND to set the control loop dominant pole.
High side current sense amplifier output.
Rev 2.8
10/2021
PI3740-00
Package Pin-Out
1
FT1
SYNCI
SYNC0
PGD/
FLT
VDR
VIN
VIN
VIN
VIN
2
FT2
PGND
PGND
PGND
PGND
VIN
VIN
VIN
VIN
3
FT3
PGND
PGND
PGND
PGND
4
FT4
PGND
PGND
PGND
PGND
VS1
VS1
VS1
VS1
5
EN
PGND
PGND
PGND
PGND
VS1
VS1
VS1
VS1
6
TRK
PGND
PGND
PGND
PGND
7
LGH/
FT5
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
8
COMP
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
PGND
9
VSN
PGND
PGND
PGND
PGND
10
VSP
SGND
SGND
SGND
SGND
VS2
VS2
VS2
VS2
11
VDIFF
SGND
SGND
SGND
SGND
VS2
VS2
VS2
VS2
12
EAIN
SGND
SGND
SGND
SGND
13
EAO
SGND
VOUT
VOUT
VOUT
VOUT
14
IMON
SGND
VOUT
VOUT
VOUT
VOUT
ISN
ISP
Large Pin Blocks
Pin Block Name
Group of pins
VIN
G1 – 2, H1 – 2, J1 – 2, K1 – 2
VS1
G4 – 5, H4 – 5, J4 – 5, K4 – 5
PGND
B2 – 9, C2 – 9, D2 – 9, E2 – 9, F7 – 8, G7 – 8, H7 – 8, J7 – 8, K7 – 8
VS2
G10 – 11, H10 – 11, J10 – 11, K10 – 11
VOUT
G13 – 14, H13 – 14, J13 – 14, K13 – 14
SGND
B10 – 14, C10 – 12, D10 – 12, E10 – 12
ZVS Regulators
Page 5 of 49
Rev 2.8
10/2021
PI3740-00
Storage and Handling Information
Storage Temperature
–65 to 150°C
Internal Operating Temperature
-LGIZ
–40 to 115°C
-LGMZ
–55 to 115°C
Soldering Temperature for 20 seconds
245°C
MSL Rating
3
ESD Rating [d]
2.0kV HBM; 1.0kV CDM
[d]
JS-200-2014, JESD22-A114F.
Block Diagram
LEXT
VIN
VOUT
Q1
Q3
VS1
VS2
Q2
+
Q4
+
VDR
Power
Control
VDR
ISN
ISP
IMON
VSN
VSP
VDIFF
LGH
+ 0.1V
VCC
ZVS Buck-Boost Control
SYNCO
SYNCI
and
FLT
EN
Digital Parametric Trim
+ 1.7V
EAIN
EAO
COMP
TRK
PGND
100pF
0Ω
FT1
FT2
FT3
FT4
SGND
ZVS Regulators
Page 6 of 49
Rev 2.8
10/2021
PI3740-00
PI3740-00 Electrical Characteristics
Specifications apply for the conditions –40°C < TJ < 115°C for -LGIZ, –55°C < TJ < 115°C for -LGMZ,
VIN = 24V, VOUT = 12V, LEXT = 420nH [e], external CIN = 6 x 2.2µF, external COUT = 8 x 10µF, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
8
24
60
V
Input Specifications
Input Voltage
Input Current During Output Short
(Fault Condition Duty Cycle)
Input Quiescent Current
VIN_DC
IIN_SHORT
[f]
3.75
mA
mA
IQ_VIN
Enabled (no load)
5
Input Quiescent Current
IQ_VIN
Disabled
2
Input Voltage Slew Rate
VIN_SR
[f]
Internal Input Capacitance
CIN
VIN UVLO Threshold Rising
VIN_UVLO_START
VIN UVLO Hysteresis
VIN OVLO Threshold Rising
VIN OVLO Hysteresis
mA
1
25°C, VIN = 48V
0.5
6.4
VIN_UVLO_HYS
6.9
µF
7.2
0.5
VIN_OVLO_START
61.0
VIN_OVLO_HYS
64.5
V / µs
V
V
68.2
2.66
V
V
Output Specifications
EAIN Voltage Total Regulation
VEAIN_DC
Output Voltage Range
VOUT_DC
Output Current Range
IOUT_DCR
Output Current Steady State
IOUT_DC
Output Power Steady State
POUT_DC
Maximum Array Size
NPARALLEL
[g]
1.667
1.7
1.734
V
10
12
50
V
See note 6
A
0
VIN = 8 – 16V, VOUT ≤ 12V, TCASE = 25°C
[g]
VIN = 16 – 24V, VOUT ≤ 12V, TCASE = 25°C
5.0
[g]
VIN = 8 – 60V, VOUT = 12 – 36V, TCASE = 25°C [g]
VIN = 16 – 28V, VOUT = 24 – 36V, TCASE = 25°C
A
6.5
[g]
60
W
123
3
Modules
Output Current, Array of 2
IOUT_DC-ARRAY2
Total array capability, see applications section for details
0
1.77 • IOUT_DC
Output Current, Array of 3
IOUT_DC-ARRAY3
Total array capability, see applications section for details
0
2.54 • IOUT_DC
Line Regulation
∆VOUT (∆VIN)
at 25°C, 8V < VIN < 60V
0.10
%
Load Regulation
∆VOUT (∆IOUT)
at 25°C, IOUT above 5% of the typical full load
0.10
%
96
mVP-P
0.75
µF
Output Ripple
VOUT_AC
Internal Output Capacitance
COUT
VOUT Overvoltage Threshold
VOUT_OVT
VOUT Overvoltage Hysteresis
VOUT_OVH
IOUT = 7.0A, VIN = 24V, VOUT = 12V, TCASE = 25°C
COUT_EX = 8 x 10µF, 50V, X7R, 20MHz BW
25°C, VOUT = 24V
Rising VOUT threshold to detect open loop
50.8
53.4
56
1.0
A
V
V
VDR
VDR Supply Voltage
VDR
Generated internally
4.9
External Loading
IVDR
See Application Description for details
[e]
0
See Inductor Pairing section.
Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[g] Output current capability varies with input & output voltage. See rated ouput current / power curves on page 9.
[f]
ZVS Regulators
Page 7 of 49
Rev 2.8
10/2021
5.1
5.36
V
2
mA
PI3740-00
PI3740-00 Electrical Characteristics (Cont.)
Specifications apply for the conditions –40°C < TJ < 115°C for -LGIZ, –55°C < TJ < 115°C for -LGMZ,
VIN = 24V, VOUT = 12V, LEXT = 420nH [e], external CIN = 6 x 2.2µF, external COUT = 8 x 10µF, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
150
260
µA
Current Sense Amplifier (Dedicated to monitor Input or Output Current)
ISP Pin Bias Current (Sink)
VOUT = 10V, Flows to SGND
ISN Pin Bias Current
VOUT = 10V
90
0
Common Mode Input Range
8
IMON Source Current
1
IMON Sink Current
1
IMON Output at No Load
µA
60
V
1.8
3
mA
1.6
2.6
mA
10
Full Scale Error
40mV input
Bandwidth
[f]
40
1%
20
µs
15mV measured across 5mΩ shunt
20
V/V
Settling Time for Full Scale Step
Gain
AV_CS
–4
mV
4
%
kHz
General Purpose Amplifier
Open Loop Gain
[e]
96
120
140
dB
Small Signal Gain-Bandwidth
[e]
5
7
12
MHz
–1
1
mV
–0.1
2.5
V
2
V
VDR – 0.2V
V
20
mV
100
pF
Offset
Common Mode Input Range
Differential Mode Input Range
Maximum Output Voltage
IDIFF = –1mA
Minimum Output Voltage
No Load
Capacitive Load for
Stable Operation
[f]
0
Slew Rate
10
Output Current
–1
V / µs
1
mA
105
mV
Current Amplifier (LGH)
Reference
95
Input Offset
0.5
Gain-Bandwidth Product
3
Internal Feedback Capacitance
See Inductor Pairing section.
[f] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[g] Output current capability varies with input & output voltage. See rated ouput current / power curves on page 9.
Rev 2.8
10/2021
mV
MHz
20
[e]
ZVS Regulators
Page 8 of 49
100
pF
PI3740-00
PI3740-00 Electrical Characteristics (Cont.)
Specifications apply for the conditions –40°C < TJ < 115°C for -LGIZ, –55°C < TJ < 115°C for -LGMZ,
VIN = 24V, VOUT = 12V, LEXT = 420nH [e], external CIN = 6 x 2.2µF, external COUT = 8 x 10µF, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
EAIN = EAO, 25°C
1.688
1.7
1.712
EAIN = EAO
1.667
1.7
1.734
Unit
Transconductance Error Amplifier
Reference
VREF
Input Range
VEAIN
Note VEAIN_OV below
0
Maximum Output Voltage
3.35
Minimum Output Voltage
V
VDR
V
3.6
4.0
V
0.05
0.15
V
Transconductance
Factory Set
7.6
mS
Zero Resistor
Factory Set
5
kΩ
EAO Output Current Sourcing
VEAO = 50mV, VEAIN = 0V
400
µA
EAO Output Current Sinking
VEAO = 2V, VEAIN = 5V
400
µA
Open Loop Gain
ROUT > 1MΩ [f]
80
dB
Input Capacitance
56
pF
Output Capacitance
1
pF
1
MHz
0.4
V
70
Control and Protection
Switching Frequency
VEAO Pulse Skip Threshold
Control Node Range
VEAO Overload Threshold
Overload Timeout
Overload Due to EAO limit
VEAIN Output Overvoltage Threshold
Overtemperature Fault Threshold
Overtemperature Restart Hysteresis
FSW
VEAO_PST
VEAO to SGND
VRAMP
0
VEAO_OL
VEAO to SGND
TOL
VEAO > VEAO_OL
IOUT_EAOLIM
VEAIN_OV
3.175
Module shuts down after 1ms of overload and restarts
after 30ms
VEAIN > VEAIN_OV
1.94
3.3
3.3
V
3.425
V
1
ms
7.7
A
2.04
2.14
V
TOTP
[f]
125
°C
TOPT_HYS
[f]
30
°C
VOUT Negative Fault Threshold
–0.45
–0.25
–0.15
V
1.7
V
70
mV
70
µA
Soft Start and Tracking Function
TRK Active Range
Nominal
0
TRK Disable Threshold
20
TRK Internal Capacitance
56
Soft Start Charge Current
30
Soft Start Discharge Current
Soft Start Time
VTRK = 0.5V
tSS
Ext CSS = 47nF
[e]
See Inductor Pairing section.
Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[g] Output current capability varies with input & output voltage. See rated ouput current / power curves on page 9.
[f]
ZVS Regulators
Page 9 of 49
45
Rev 2.8
10/2021
50
pF
9
mA
1.6
ms
PI3740-00
PI3740-00 Electrical Characteristics (Cont.)
Specifications apply for the conditions –40°C < TJ < 115°C for -LGIZ, –55°C < TJ < 115°C for -LGMZ,
VIN = 24V, VOUT = 12V, LEXT = 420nH [e], external CIN = 6 x 2.2µF, external COUT = 8 x 10µF, unless otherwise noted.
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
Enable
Enable High Threshold
ENIH
0.9
1
1.1
V
Enable Low Threshold
ENIL
0.7
0.8
0.9
V
ENHYS
100
200
300
mV
Enable Threshold Hysteresis
Enable Pin Bias Current
VEN = 0V or VEN = 2V
±50
µA
Enable Pull-Up Voltage
Floating
2.0
V
30
ms
Fault Restart Delay Time
tFR_DLY
Digital Signals
SYNCI High Threshold
VDR = 5.1V
SYNCO High
SYNCOOH
SYNCO Low
SYNCOOL
1/2 VDR
VDR – 0.5
V
VDR
V
ISYNCOUT = 1mA
0.5
V
PGD High Leakage
PGDILH
VPGD = VDR
10
µA
PGD Output Low
PGDOL
IPGD = 4mA
0.4
V
PGD EAIN Low Rise
1.41
1.45
1.48
V
PGD EAIN Low Fall
1.36
1.41
1.46
V
PGD EAIN Threshold Hysteresis
PGD EAIN High
[e]
35
1.94
See Inductor Pairing section.
Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control.
[g] Output current capability varies with input & output voltage. See rated ouput current / power curves on page 9.
[f]
ZVS Regulators
Rev 2.8
Page 10 of 49 10/2021
2.04
mV
2.14
V
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C [h]
160
Rated Output Power (W)
Rated Output Current (A)
8
7
6
5
4
3
2
1
140
120
100
80
60
40
20
0
0
5
10
15
20
25
30
35
40
45
50
55
5
60
10
15
20
25
10VOUT
24VOUT
12VOUT
28VOUT
10VOUT
18VOUT
36VOUT
24VOUT
50VOUT
Figure 1 — Output current of PI3740-00
45
50
55
60
12VOUT
28VOUT
18VOUT
36VOUT
50VOUT
95
Efficiency (%)
Efficiency (%)
40
100
95
90
85
80
90
85
80
75
70
0
1
2
3
4
5
6
7
75
8
0
1
2
Output Current (A)
8VIN
12VIN
3
4
5
6
7
Output Current (A)
18VIN
16VIN
36VIN
28VIN
48VIN
24VIN
8VIN
60VIN
12VIN
28VIN
Figure 3 — 10VOUT efficiency
18VIN
16VIN
36VIN
48VIN
24VIN
60VIN
Figure 5 — 18VOUT efficiency
100
100
95
95
Efficiency (%)
Efficiency (%)
35
Figure 2 — Output power of PI3740-00
100
90
85
80
75
90
85
80
75
70
0
1
2
3
4
5
6
7
70
8
0
1
Output Current (A)
8VIN
12VIN
28VIN
Figure 4 — 12VOUT efficiency
[h]
30
Input Voltage (V)
Input Voltage (V)
18VIN
16VIN
36VIN
48VIN
2
3
5
4
6
Output Current (A)
24VIN
8VIN
60VIN
12VIN
28VIN
Figure 6 — 24VOUT efficiency
Note: Testing was performed using a 3 x 3in, four 2oz copper layers, FR4 evaluation board platform.
ZVS Regulators
Rev 2.8
Page 11 of 49 10/2021
16VIN
36VIN
18VIN
48VIN
24VIN
60VIN
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.) [h]
100
100
95
Efficiency (%)
Efficiency (%)
95
90
85
80
75
90
85
80
75
70
65
0
1
2
3
4
0
5
1
Output Current (A)
8VIN
12VIN
28VIN
18VIN
16VIN
36VIN
48VIN
8VIN
24VIN
Figure 9 — 50VOUT efficiency
100
98
Efficiency (%)
96
94
92
90
88
86
84
82
0
1
2
3
4
Output Current (A)
8VIN
12VIN
28VIN
16VIN
36VIN
18VIN
48VIN
24VIN
60VIN
Figure 8 — 36VOUT efficiency
[h]
12VIN
28VIN
60VIN
Figure 7 — 28VOUT efficiency
80
2
3
Output Current (A)
Note: Testing was performed using a 3 x 3in, four 2oz copper layers, FR4 evaluation board platform.
ZVS Regulators
Rev 2.8
Page 12 of 49 10/2021
18VIN
16VIN
36VIN
48VIN
24VIN
60VIN
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.) [h]
1200
Operational Frequency (kHz)
Operational Frequency (kHz)
1200
1000
1000
800
600
400
200
800
600
400
200
0
0
0
1
2
3
4
5
6
7
0
8
1
2
8VIN
12VIN
28VIN
16VIN
18VIN
48VIN
36VIN
8VIN
24VIN
4
5
6
7
16VIN
18VIN
48VIN
36VIN
24VIN
60VIN
Figure 12 — Switching frequency vs. output current at 18VOUT
1200
1200
Operational Frequency (kHz)
Operational Frequency (kHz)
12VIN
28VIN
60VIN
Figure 10 — Switching frequency vs. output current at 10VOUT
1000
800
600
400
200
0
0
1
2
3
4
5
6
7
1000
800
600
400
200
0
8
0
1
2
8VIN
12VIN
28VIN
18VIN
16VIN
36VIN
48VIN
3
4
5
6
Output Current (A)
Output Current (A)
8VIN
24VIN
12VIN
28VIN
60VIN
Figure 11 — Switching frequency vs. output current at 12VOUT
[h]
3
Output Current (A)
Output Current (A)
16VIN
36VIN
18VIN
48VIN
24VIN
60VIN
Figure 13 — Switching frequency vs. output current at 24VOUT
Note: Testing was performed using a 3 x 3in, four 2oz copper layers, FR4 evaluation board platform.
ZVS Regulators
Rev 2.8
Page 13 of 49 10/2021
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.) [h]
1200
Operational Frequency (kHz)
Operational Frequency (kHz)
1200
1000
800
600
400
200
0
0
1
2
4
3
12VIN
28VIN
18VIN
16VIN
36VIN
48VIN
800
600
400
200
0
5
Output Current (A)
8VIN
1000
0
1
24VIN
8VIN
60VIN
Operational Frequency (kHz)
1000
800
600
400
200
0
1
2
3
4
Output Current (A)
8VIN
12VIN
28VIN
18VIN
16VIN
36VIN
48VIN
24VIN
60VIN
Figure 15 — Switching frequency vs. output current at 36VOUT
[h]
3
16VIN
36VIN
18VIN
48VIN
24VIN
60VIN
Figure 16 — Switching frequency vs. output current at 50VOUT
1200
0
12VIN
28VIN
Figure 14 — Switching frequency vs. output current at 28VOUT
2
Output Current (A)
Note: Testing was performed using a 3 x 3in, four 2oz copper layers, FR4 evaluation board platform.
ZVS Regulators
Rev 2.8
Page 14 of 49 10/2021
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.)
Figure 17 — Output voltage ripple at 24VIN to 10VOUT, 7.3A;
COUT = 8 x 10µF ceramic
Figure 19 — Output voltage ripple at 24VIN to 18VOUT, 6.3A;
COUT = 8 x 10µF ceramic
Figure 18 — Output voltage ripple at 24VIN to 12VOUT, 6.75A;
COUT = 8 x 10µF ceramic
Figure 20 — Output voltage ripple at 24VIN to 24VOUT, 5.3A;
COUT = 8 x 10µF ceramic
ZVS Regulators
Rev 2.8
Page 15 of 49 10/2021
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.)
Figure 21 — Output voltage ripple at 24VIN to 28VOUT, 4.5A;
COUT = 8 x 10µF ceramic
Figure 23 — Output voltage ripple at 24VIN to 50VOUT, 2.50A;
COUT = 8 x 2.2µF ceramic
Figure 22 — Output voltage ripple at 24VIN to 36VOUT, 3.65A;
COUT = 8 x 10µF ceramic
ZVS Regulators
Rev 2.8
Page 16 of 49 10/2021
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.)
Figure 24 — 24VIN to 10VOUT, COUT = 8 x 10µF ceramic
3.5 – 7.0A load step, 0.1A/µs
Figure 27 — 24VIN to 28VOUT, COUT = 8 x 10µF ceramic
2.25 – 4.5A load step, 0.1A/µs
Figure 25 — 24VIN to 12VOUT, COUT = 8 x 10µF ceramic
3.38 – 6.75A load step, 0.1A/µs
Figure 28 — 24VIN to 36VOUT, COUT = 8 x 10µF ceramic
1.5– 3.0A load step, 0.1A/µs
Figure 26 — 24VIN to 24VOUT, COUT = 8 x 10µF ceramic
2.5 – 5.0A load step, 0.1A/µs
Figure 29 — 24VIN to 50VOUT, COUT = 8 x 2.2µF ceramic
2.5 – 1.25A load step, 0.1A/µs
ZVS Regulators
Rev 2.8
Page 17 of 49 10/2021
PI3740-00
PI3740-00 Performance Characteristics TPCB = 25°C (Cont.)
Figure 30 — Start up with 8VIN to 24VOUT at 2.4A,
Ext CSS = 47nF
Figure 33 — Start up with 24VIN to 10VOUT at 6.5A,
Ext CSS = 47nF
Figure 31 — Start up with 8VIN to 12VOUT at 5A,
Ext CSS = 47nF
Figure 34 — Start up with 8VIN to 36VOUT at 1.7A,
Ext CSS = 47nF
Figure 32 — Start up with 24VIN to 12VOUT at 6A,
Ext CSS = 47nF
Figure 35 — Start up with 24VIN to 36VOUT at 2A,
Ext CSS = 47nF
ZVS Regulators
Rev 2.8
Page 18 of 49 10/2021
PI3740-00
MTBF
MTBF (Mhrs)
1000
100
10
1
-60
-40
-20
0
20
40
60
80
100
Temperature (°C)
MTBF Calculations Over Temperature Using Telcordia SR-332
Figure 36 — PI3740-00 calculated MTBF Telcordia SR-332 GB
ZVS Regulators
Rev 2.8
Page 19 of 49 10/2021
120
140
PI3740-00
Functional Description
The PI3740-00 is a highly integrated ZVS Buck-Boost regulator.
The PI3740-00 has an adjustable output voltage that is set with
a resistive divider. Performance and maximum output current are
characterized with a specific external power inductor as defined in
the electrical specifications, and in the inductor pairing section.
For basic operation, Figure 37 shows the minimum connections and
components required.
VS1
VIN
CIN
VS2 VOUT
PGND
PGND
COUT
ISP
R1
10kΩ
PI3740-00
PGD
The PI3740-00 PGD pin functions as a power good indicator
and pulls low when the regulator is not operating or if EAIN is
less than 1.4V.
VSN
VDIFF
LGH
SYNCO
EAIN
SYNCI
TRK
CTRK
EAO
SGND
COMP
A general purpose operational amplifier is provided to assist with
differential remote sensing and/or level shifting of the output
voltage. The VDIFF pin can be connected to the transconductance
error amplifier input EAIN pin, or with proper configuration can
also be connected to the EAO pin to drive the modulator directly. If
unused, connect in unity gain with VSP connected to SGND.
Power Good
IMON
VSP
EN
Remote Sensing Differential Amplifier
R2
ISN
VDR
and regulated output will proportionally follow the TRK ramp
when it is below 1.7VDC. When the ramp is greater than 1.7VDC,
the internal reference will remain at 1.7VDC while the TRK ramp
rises and clamps at 2.5VDC. If the TRK pin goes below the disable
threshold, the regulator will finish the current switching cycle and
then stop switching.
Output Current Limit Protection
CHF
CCOMP
Figure 37 — PI3740-00 with required components
Enable
The EN pin of the regulator is referenced to SGND and permits the
user to turn the regulator on or off. The EN polarity is a positive
logic assertion. If the EN pin is left floating or asserted high, the
regulator output is enabled. Pulling the EN pin below 0.8VDC with
respect to SGND will discharge the TRK pin until the output reaches
zero or the EN pin is released. When the converter is disabled via
the EN pin or due to a fault mode, the internal gate driver high
side charge pumps are enabled as long as there is enough input
voltage for the internal VDR supply voltage to be available. The
return path for this charge pump supply is through the output. If
the output load is disconnected or high impedance, the output
capacitors will float up to about 3.4V maximum, sourced by 960µA
of leakage current. This pre-biased condition poses no issue for
the converter. The 960µA leakage current may be safely bypassed
to SGND. A simple application circuit is available to bypass this
current in a non-dissipative manner. Please contact Applications
Engineering for details.
Switching Frequency Synchronization
The SYNCI input allows the user to synchronize the controller
switching frequency to the falling edge of an external clock
referenced to SGND. The external clock can synchronize the unit
between 50% and 110% of the preset switching frequency (FSW ).
The SYNCI pin should be connected to SGND when not in use, and
should never be left floating.
PI3740-00 has three methods implemented to protect from output
short circuit or over current condition.
Slow Current Limit protection: prevents the regulator load from
sourcing current higher than the maximum rated regulator current.
If the output current exceeds the VOUT Slow Current Limit (VOUT_SCL)
a slow current limit fault is initiated and the regulator is shutdown,
which eliminates output current flow. After the Fault Restart Delay
(tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be
repeated indefinitely until the excessive load is removed.
Fast Current Limit protection: monitors the external inductor
current pulse-by-pulse to prevent the output from supplying
saturation current. If the regulator senses a high inductor current
pulse, it will initiate a fault and stop switching. After the Fault
Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle
will be repeated indefinitely until the excessive load is removed.
Overload Timeout protection: If the regulator is providing
greater than the maximum output power for longer than the
Overload Timeout delay (TOL), it will initiate a fault and stop
switching. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is
initiated. This restart cycle will be repeated indefinitely until the
overload load is removed.
Input Undervoltage Lockout
If VIN falls below the input Undervoltage Lockout (UVLO) threshold,
the PI3740-00 will complete the current cycle and stop switching.
The system will restart once the input voltage is reestablished.
Input Overvoltage Lockout
If VIN rises above the input Overvoltage Lockout (OVLO) threshold,
the PI3740-00 will complete the current cycle and stop switching.
The system will restart once the input voltage is reestablished and
after the Fault Restart Delay.
Soft Start and Tracking
The PI3740-00 provides a soft start and tracking feature using the
TRK pin. Programmable Soft Start requires an external capacitor
from the TRK pin to SGND in addition to the internal 56pF softstart capacitor to set the start-up ramp period equal to tSS. The
recommended value is 47nF. The PI3740-00 internal reference
ZVS Regulators
Rev 2.8
Page 20 of 49 10/2021
PI3740-00
Output Overvoltage Protection
The PI3740-00 is equipped with two methods of detecting
an output overvoltage condition. To prevent damage to input
voltage-sensitive devices, if the output voltage exceeds 20% of
its set regulated value as measured by the EAIN pin (VEAIN_OV ), the
regulator will complete the current cycle, stop switching and issue
an OVP fault. Also if the output voltage of the regulator exceeds
the VOUT Overvoltage Threshold (VOUT_OVT ) then the regulator will
complete the current cycle, stop switching and issue an OVP fault.
The system will resume operation once the output voltage falls
below the OVP threshold and after Fault Restart Delay.
Overtemperature Protection
The PI3740-00 features an overtemperature protection (OTP),
which will not engage until after the product is operated above the
maximum rated temperature. The OTP circuit is only designed to
protect against catastrophic failure due to excessive temperatures
and should not be relied upon to ensure the device stays within the
recommended operating temperature range. Thermal shutdown
terminates switching and discharges the soft-start capacitor. As the
temperature falls the PI3740-00 will restart, and this will always
occur before the product returns to rated temperature range.
Pulse Skip Mode (PSM)
PI3740-00 features a hysteretic Pulse Skip Mode to achieve high
efficiency at light loads. The regulator is setup to skip pulses if
VEAO falls below the Pulse Skip Threshold (VEAO_PST ). Depending on
conditions and component values, this may result in single pulses
or several consecutive pulses followed by skipped pulses. Skipping
cycles significantly reduces gate drive power and improves light
load efficiency. The regulator will leave Pulse Skip Mode once the
control node rises above the Pulse Skip Mode threshold (VEAO_PST ).
Variable Frequency Operation
The PI3740-00 is preprogrammed to a fixed, maximum, base
operating frequency. The frequency is selected with respect to
the required power stage inductor to operate at peak efficiency
across line and load variations. The switching frequency period
will stretch as needed during each cycle to accommodate low line
and or high load conditions. By stretching the switching frequency
period, thus decreasing the switching frequency, the ZVS operation
is preserved throughout the input line voltage range maintaining
optimum efficiency.
IMON Amplifier
The PI3740-00 provides a differential amplifier with a level shifted,
SGND referenced output, the IMON Pin, which is useful for sensing
input or output current on high voltage rails. A fixed gain of 20:1
is provided over a large common mode range. When using the
amplifier, the ISN pin must be referenced to the common mode
voltage of the ISP pin for proper operation. See Absolute Maximum
Ratings for more information. If not in use, the ISN and ISP pins
should be connected to SGND and the IMON pin left floating.
ZVS Regulators
Rev 2.8
Page 21 of 49 10/2021
PI3740-00
Application Description
Output Voltage Trim
The output voltage can be adjusted by feeding back a portion of
the desired output through a voltage divider to the error amplifier’s
input (see Figure 37). Equation 1 can be used to determine resistor
values needed for the voltage divider.
R1 = R2 •
(
VOUT
1.7
)
For Direct Tracking, choose the regulator with the highest output
voltage as the parent and connect the parent to the TRK pin of the
other regulators through a divider (Figure 39) with the same ratio
as the child’s feedback divider (see Output Voltage Trim). The TRK
pin should not be driven without 1kΩ minimum series resistance.
Parent VOUT
(1)
–1
TRK
The R2 value is selected by the user; a 1.65kΩ resistor value
is recommended.
If, for example, a 12V output is needed, the user can select a
1.65kΩ (1%) resistor for R2 and use Equation 1 to calculate R1.
Once R1 value is calculated, the user should select the nearest
resistor value available. In this example, R1 is 9.997kΩ so a 10.0kΩ
should be selected.
Soft Start Adjustment and Tracking
The TRK pin offers a means to increase the regulator’s soft-start
time or to track with additional regulators. The soft-start slope is
controlled by an external capacitor and a fixed charge current to
provide the startup ramp. The following equation can be used to
calculate the proper capacitor for a desired soft-start time:
CTRK =
(tTRK • ISS )
1.7
(2)
– 56 • 10 -12
Where tTRK is the desired soft-start time and ISS is the TRK pin
source current (see Electrical Characteristics for limits).
The PI3740-00 allows the tracking of multiple like regulators. Two
methods of tracking can be chosen: proportional or direct tracking.
Proportional tracking will force all connected
regulators to startup and reach regulation at the same time (see
Figure 38 (a)). To implement proportional tracking, simply connect
all devices TRK pins together.
VOUT 1
VOUT 2
Child
R2
SGND
Figure 39 — Voltage divider connections for direct tracking
All connected regulators’ soft-start slopes will track with this
method. Direct tracking timing is demonstrated in Figure 38 (b). All
tracking regulators should have their Enable (EN) pins connected
together for proper operation.
Inductor Pairing
The PI3740-00 utilizes an external inductor. This inductor
has been optimized for maximum efficiency performance.
Product specifications are guaranteed by use of the
specific, approved inductor(s) listed in the inductor
pairing table. Use of any other inductor shall void product
specifications and warranty.
Table 1 details the specific inductor value and part number
utilized for PI3740-00.
Device
Inductor
(nH)
PI3740-00
420
Inductor
Part Number
Manufacturer
HCV1206-R42-R
Eaton
PA5119.421NLT
Pulse
Table 1 — PI3740-00 inductor pairing
Propor onal
Tracking
(a)
Parent VOUT
VOUT 2
R1
PI3740
Direct
Tracking
(b)
t
Figure 38 — PI3740-00 tracking methods
ZVS Regulators
Rev 2.8
Page 22 of 49 10/2021
PI3740-00
Filter Considerations
The PI3740-00 requires low impedance ceramic input capacitors
(X7R/X5R or equivalent) to ensure proper start up and high
frequency decoupling for the power stage. The PI3740-00 will
draw nearly all of the high frequency current from the low
impedance ceramic capacitors when the main high side MOSFET(s)
are conducting. During the time the MOSFET(s) are off, the
input capacitors are replenished from the source. Table 2 shows
the recommended input and output capacitors to be used for
the PI3740-00. Divide the total RMS current by the number of
ceramic capacitors used to calculate the individual capacitor’s
RMS current. Table 3 includes the recommended input and output
ceramic capacitor. It is very important to verify that the voltage
supply source as well as the interconnecting line are stable and
do not oscillate.
Input Filter case 1; Inductive source and local, external, input
decoupling capacitance with negligible ESR (i.e., ceramic type)
The voltage source impedance can be modeled as a series RLINE
LLINE circuit. The high performance ceramic decoupling capacitors
will not significantly damp the network because of their low ESR;
therefore in order to guarantee stability the following conditions
must be verified:
RLINE >
(C
IN_INT
LLINE
+ CIN_EXT
)• r
(3)
Input Filter case 2; Inductive source and local, external input
decoupling capacitance with significant RCIN_EXT ESR
(i.e., electrolytic type)
In order to simplify the analysis in this case, the voltage source
impedance can be modeled as a simple inductor LLINE. Notice that
the high performance ceramic capacitors CIN_INT within the PI374000 should be included in the external electrolytic capacitance value
for this purpose. The stability criteria will be:
(5)
rEQ_IN > RCIN_EXT
LLINE
CIN_INT • RCIN_EXT
(6)
< rEQ_IN
Equation 6 shows that if the aggregate ESR is too small – for
example by using very high quality input capacitors (CIN_EXT ) – the
system will be under-damped and may even become destabilized.
Again, an octave of design margin in satisfying Equation 5 should
be considered the minimum.
Note: When applying an electrolytic capacitor for input filter damping the
ESR value must be chosen to avoid loss of converter efficiency and excessive
power dissipation in the electrolytic capacitor.
EQ_IN
(4)
RLINE 400µA
When regulating in CC mode, it will be necessary to add a
compensating zero to avoid loss of phase margin caused by the
integrator stage of the LGH amplifier. A simple approach is to add a
series R–C in parallel with RLGH as shown in the lighting application
diagram in Figure 61. The capacitor will be chosen to work with
RLGH to add a zero approximately 1.2kHz before the zero provided
by the GMLGH transfer function (the trans‑conductance stage of
the LGH amplifier). The external added resistor will form a high
frequency pole to roll the gain off at higher frequency. Note that it
is very important to understand the AC resistance of the LED’s that
are being used. Please consult the LED manufacturer for details. For
a series string, you should add the individual LED resistances and
combine them into one lumped value to simplify the analysis.
LGH Amplifier Small-Signal Model
A small signal model of the LGH amplifier is shown in Figure 62.
The VDR internal bias regulator is a ZVS switching regulator that
resides internal to the PI3740-00 SiP. It is intended primarily to
power the internal controller and driver circuitry. The power
capability of this regulator is sized only for the PI3740-00, with
adequate reserve for the application it was intended for. It may be
used as a pull-up source for open-collector applications and for
other very low power uses with the following restrictions:
n
The total external loading on VDR must be less than 2mA.
400µA
IEAO
VEAO
GMLGH
CINT
VLGH
RZI
+
+
+
CHF
RZI
ROUT
CCOMP
EINT
ELS
n
No direct connection is allowed. Any noise source that can
disturb the VDR voltage can also affect the internal controller
operation. A series impedance is required between the VDR pin
and any external circuitry.
n
All loads must be locally decoupled using a 0.1µF ceramic
capacitor. This capacitor must be connected to the VDR output
through a series resistor no smaller than 1kΩ, which forms a
low-pass filter.
Figure 62 — LGH amplifier small-signal model
The LGH amplifier consists of three distinct stages. The first is a
wide-bandwidth integrator stage, followed by a fixed gain level
shift circuit. Finally, the level shift circuit drives a trans‑conductance
(TCA) amplifier with an open collector sink only output stage. Since
the LGH output is internally connected to the output of the voltage
error amplifier, the compensation components show up in the
model and are used by both stages, depending on which one is in
use. Only one stage should be in use at a time. When using LGH or
if the LGH input rises above the internal reference, the voltage error
ZVS Regulators
Rev 2.8
Page 37 of 49 10/2021
PI3740-00
9.0
40
4.5
8.0
4
35
7.0
7.0
30
3.5
6.0
3
5.0
2.5
4.0
2
3.0
1.5
2.0
1
1.0
1.00
1.50
2.00
2.50
3.00
0
3.50
20
4.0
15
3.0
2.0
10
1.0
5
0.0
0.00
0.50
1.00
VEAO (V)
IOUT@VIN = 8V
GMOD@VIN = 8V
IOUT@VIN = 12V
IOUT@VIN = 16V
GMOD@VIN = 12V
IOUT@VIN = 8V
GMOD@VIN = 16V
rEQ_OUT@VIN = 8V
5
7.0
6.0
4
5.0
3
4.0
3.0
2
2.0
1
1.0
1.50
2.00
2.50
3.00
Output Current DC Amps
6
8.0
1.00
IOUT@VIN = 18V
IOUT@VIN = 24V
30
6.0
25
5.0
20
4.0
15
3.0
2.0
10
1.0
5
0.50
1.00
IOUT@VIN = 18V
5.0
3
4.0
2
3.0
2.0
1
1.0
GMOD@VIN = 36V
GMOD@VIN = 48V
2.50
3.00
0
3.50
2.50
3.00
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
50
9.0
40
8.0
7.0
30
6.0
5.0
20
4.0
10
3.0
2.0
0
1.0
0.0
0.00
0
3.50
0.50
1.00
1.50
2.00
2.50
3.00
-10
3.50
VEAO (V)
VEAO (V)
IOUT@VIN = 48V
2.00
10.0
Output Current DC Amps
4
6.0
IOUT@VIN = 36V
1.50
Figure 67 — rEQ_OUT vs. Output Current vs. VEAO, VOUT = 10V;
18 – 28VIN
GMOD (S)
Output Current DC Amps
7.0
2.00
rEQ_OUT@VIN = 16V
35
rEQ_OUT@VIN = 18V
5
8.0
1.50
rEQ_OUT@VIN = 12V
7.0
GMOD@VIN = 28V
6
1.00
IOUT@VIN = 16V
40
IOUT@VIN = 28V
GMOD@VIN = 24V
9.0
0.50
IOUT@VIN = 12V
VEAO (V)
10.0
0.00
0
3.50
8.0
0.0
0.00
0
3.50
Figure 64 — GMOD vs output current vs. VEAO, VOUT = 10V;
18 – 28VIN
0.0
3.00
9.0
VEAO (V)
GMOD@VIN = 18V
2.50
Figure 66 — rEQ_OUT vs. output current vs. VEAO, VOUT = 10V;
8 – 16VIN
GMOD (S)
Output Current DC Amps
9.0
0.50
2.00
VEAO (V)
Figure 63 — GMOD vs output current vs. VEAO, VOUT = 10V;
8 – 16VIN
0.0
0.00
1.50
Ohms
0.50
25
5.0
IOUT@VIN = 36V
IOUT@VIN = 60V
rEQ_OUT@VIN = 36V
GMOD@VIN = 60V
Figure 65 — GMOD vs output current vs. VEAO, VOUT = 10V;
36 – 60VIN
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 68 — rEQ_OUT vs. output current vs. VEAO, VOUT = 10V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 38 of 49 10/2021
Ohms
0.0
0.00
0.5
6.0
Ohms
5
8.0
Output Current DC Amps
9.0
GMOD (S)
Output Current DC Amps
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C
PI3740-00
4.5
8.0
7.0
4
7.0
6.0
3.5
2.5
4.0
2
3.0
1.5
2.0
1
1.0
0.5
0.0
1.00
1.50
2.00
2.50
3.00
0
3.50
40
5.0
30
4.0
3.0
20
2.0
10
1.0
0.0
0.00
0.50
1.00
GMOD@VIN = 8V
IOUT@VIN = 12V
IOUT@VIN = 8V
IOUT@VIN = 16V
GMOD@VIN = 12V
rEQ_OUT@VIN = 8V
GMOD@VIN = 16V
Figure 69 — GMOD vs output current vs. VEAO, VOUT = 12V;
8 – 16VIN
6.0
4
5.0
3
4.0
3.0
2
2.0
1
1.0
1.50
2.00
2.50
3.00
IOUT@VIN = 18V
IOUT@VIN = 24V
6.0
40
5.0
30
4.0
3.0
20
2.0
10
1.0
0.0
0.00
0.50
1.00
IOUT@VIN = 18V
rEQ_OUT@VIN = 18V
GMOD@VIN = 28V
5.0
3
4.0
2
3.0
2.0
1
1.0
2.50
3.00
Output Current DC Amps
4
6.0
GMOD (S)
Output Current DC Amps
7.0
IOUT@VIN = 36V
IOUT@VIN = 48V
GMOD@VIN = 48V
2.50
3.00
0
3.50
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
50
9.0
40
8.0
7.0
30
6.0
5.0
20
4.0
10
3.0
2.0
0
1.0
0.0
0.00
0
3.50
0.50
1.00
1.50
2.00
2.50
3.00
-10
3.50
VEAO (V)
VEAO (V)
GMOD@VIN = 36V
2.00
10.0
5
8.0
2.00
1.50
Figure 73 — rEQ_OUT vs. output current vs. VEAO, VOUT = 12V;
18 – 28VIN
6
1.50
rEQ_OUT@VIN = 16V
50
IOUT@VIN = 28V
GMOD@VIN = 24V
9.0
1.00
rEQ_OUT@VIN = 12V
VEAO (V)
10.0
0.50
IOUT@VIN = 16V
7.0
0
3.50
Figure 70 — GMOD vs output current vs. VEAO, VOUT = 12V;
18 – 28VIN
0.0
0.00
IOUT@VIN = 12V
60
VEAO (V)
GMOD@VIN = 18V
0
3.50
8.0
Output Current DC Amps
5
7.0
1.00
3.00
9.0
6
8.0
0.50
2.50
Figure 72 — rEQ_OUT vs. output current vs. VEAO, VOUT = 12V;
8 – 16VIN
GMOD (S)
Output Current DC Amps
9.0
0.0
0.00
2.00
VEAO (V)
VEAO (V)
IOUT@VIN = 8V
1.50
Ohms
0.50
50
6.0
IOUT@VIN = 36V
IOUT@VIN = 60V
rEQ_OUT@VIN = 36V
GMOD@VIN = 60V
Figure 71 — GMOD vs output current vs. VEAO, VOUT = 12V;
36 – 60VIN
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 74 — rEQ_OUT vs. output current vs. VEAO, VOUT = 12V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 39 of 49 10/2021
Ohms
0.00
60
Ohms
3
5.0
Output Current DC Amps
8.0
GMOD (S)
Output Current DC Amps
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
PI3740-00
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
3.5
5.0
3
4.0
2.5
3.0
2
1.5
2.0
1
1.0
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
120
6.0
100
5.0
80
4.0
60
3.0
40
2.0
20
1.0
0.0
0.00
0.50
1.00
GMOD@VIN = 8V
IOUT@VIN = 12V
IOUT@VIN = 8V
IOUT@VIN = 16V
GMOD@VIN = 12V
rEQ_OUT@VIN = 8V
GMOD@VIN = 16V
5
8.0
7.0
4.5
7.0
4
6.0
3.5
5.0
3
4.0
2.5
3.0
2
1.5
2.0
1
1.0
0.5
0.50
1.00
1.50
2.00
2.50
3.00
Output Current DC Amps
8.0
0.00
IOUT@VIN = 18V
0
3.50
0
3.50
IOUT@VIN = 12V
IOUT@VIN = 16V
rEQ_OUT@VIN = 12V
rEQ_OUT@VIN = 16V
100
6.0
80
5.0
4.0
60
3.0
40
2.0
20
1.0
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
IOUT@VIN = 24V
IOUT@VIN = 28V
GMOD@VIN = 24V
IOUT@VIN = 18V
GMOD@VIN = 28V
rEQ_OUT@VIN = 18V
Figure 76 — GMOD vs output current vs. VEAO, VOUT = 18V;
18 – 28VIN
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
Figure 79 — rEQ_OUT vs. output current vs. VEAO, VOUT = 18V;
18 – 28VIN
4.5
8.0
100
7.0
4
7.0
90
6.0
3.5
5.0
2.5
4.0
2
3.0
1.5
2.0
1
1.0
0.5
0.0
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
80
6.0
70
5.0
60
4.0
50
3.0
40
30
2.0
20
1.0
10
0.0
0.00
0.50
1.00
VEAO (V)
IOUT@VIN = 36V
GMOD@VIN = 36V
IOUT@VIN = 48V
GMOD@VIN = 48V
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
IOUT@VIN = 60V
IOUT@VIN = 36V
GMOD@VIN = 60V
Figure 77 — GMOD vs output current vs. VEAO, VOUT = 18V;
36 – 60VIN
rEQ_OUT@VIN = 36V
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 80 — rEQ_OUT vs. output current vs.VEAO, VOUT = 18V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 40 of 49 10/2021
Ohms
3
Output Current DC Amps
8.0
GMOD (S)
Output Current DC Amps
3.00
120
VEAO (V)
GMOD@VIN = 18V
2.50
Figure 78 — rEQ_OUT vs. output current vs. VEAO, VOUT = 18V;
8 – 16VIN
GMOD (S)
Output Current DC Amps
Figure 75 — GMOD vs output current vs. VEAO, VOUT = 18V
8 – 16VIN
0.0
2.00
VEAO (V)
VEAO (V)
IOUT@VIN = 8V
1.50
Ohms
0.0
0.00
0.5
7.0
Ohms
6.0
GMOD (S)
Output Current DC Amps
4
Output Current DC Amps
4.5
7.0
PI3740-00
5.0
3
2.5
4.0
2
3.0
1.5
2.0
1
1.0
0.5
0.50
1.00
1.50
2.00
2.50
3.00
160
5.0
140
4.0
120
100
3.0
80
60
2.0
40
1.0
20
0.0
0.00
0.50
1.00
VEAO (V)
IOUT@VIN = 8V
GMOD@VIN = 8V
IOUT@VIN = 12V
IOUT@VIN = 16V
GMOD@VIN = 12V
IOUT@VIN = 8V
GMOD@VIN = 16V
rEQ_OUT@VIN = 8V
6.0
3.5
6.0
3
5.0
2.5
4.0
2
3.0
1.5
2.0
1
1.0
0.5
1.50
2.00
2.50
3.00
Output Current DC Amps
7.0
GMOD (S)
Output Current DC Amps
4
1.00
IOUT@VIN = 18V
0
3.50
IOUT@VIN = 24V
120
100
3.0
80
60
2.0
40
1.0
20
0.50
1.00
IOUT@VIN = 18V
3.0
2
1.5
2.0
1
1.0
0.5
0.0
GMOD@VIN = 48V
2.50
3.00
0
3.50
2.50
3.00
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
180
160
5.0
140
4.0
120
100
3.0
80
2.0
60
40
1.0
20
0.0
0.00
0
3.50
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
VEAO (V)
GMOD@VIN = 36V
2.00
6.0
Output Current DC Amps
2.5
IOUT@VIN = 48V
1.50
Figure 85 — rEQ_OUT vs. output current vs. VEAO, VOUT = 24V;
18 – 28VIN
3
4.0
IOUT@VIN = 36V
rEQ_OUT@VIN = 16V
140
rEQ_OUT@VIN = 18V
GMOD (S)
Output Current DC Amps
5.0
2.00
rEQ_OUT@VIN = 12V
4.0
GMOD@VIN = 28V
3.5
1.50
IOUT@VIN = 16V
5.0
IOUT@VIN = 28V
GMOD@VIN = 24V
4
1.00
IOUT@VIN = 12V
VEAO (V)
6.0
0.50
0
3.50
160
0.0
0.00
Figure 82 — GMOD vs output current vs. VEAO, VOUT = 24V;
18 – 28VIN
0.00
3.00
180
VEAO (V)
GMOD@VIN = 18V
2.50
Figure 84 — rEQ_OUT vs. output current vs. VEAO, VOUT = 24V;
8 – 16VIN
7.0
0.50
2.00
VEAO (V)
Figure 81 — GMOD vs output current vs. VEAO, VOUT = 24V;
8 – 16VIN
0.0
0.00
1.50
Ohms
0.00
0
3.50
180
IOUT@VIN = 36V
IOUT@VIN = 60V
rEQ_OUT@VIN = 36V
GMOD@VIN = 60V
Figure 83 — GMOD vs output current vs. VEAO, VOUT = 24V;
36 – 60VIN
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 86 — rEQ_OUT vs. output current vs. VEAO, VOUT = 24V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 41 of 49 10/2021
Ohms
0.0
6.0
Ohms
3.5
Output Current DC Amps
6.0
GMOD (S)
Output Current DC Amps
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
PI3740-00
5.0
3
2.5
4.0
2
3.0
1.5
2.0
1
1.0
0.5
0.00
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
250
5.0
200
4.0
150
3.0
100
2.0
50
1.0
0.0
0.00
0.50
1.00
VEAO (V)
IOUT@VIN = 12V
IOUT@VIN = 16V
GMOD@VIN = 12V
IOUT@VIN = 8V
GMOD@VIN = 16V
rEQ_OUT@VIN = 8V
6.0
3.5
5.0
3
4.0
2
3.0
1.5
2.0
1
1.0
0.5
1.00
1.50
2.00
2.50
3.00
0
3.50
2.5
2
1.5
2.0
1
1.0
0.5
0.0
2.00
0
2.50
3.00
0.50
1.00
GMOD@VIN = 36V
IOUT@VIN = 48V
GMOD@VIN = 48V
2.00
2.50
3.00
3.50
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
0
3.50
250
5.0
200
4.0
150
3.0
100
2.0
50
1.0
0.0
0.00
0.50
1.00
VEAO (V)
IOUT@VIN = 36V
1.50
6.0
GMOD (S)
Output Current DC Amps
3
1.50
50
1.0
rEQ_OUT@VIN = 18V
5.0
1.00
100
2.0
Figure 91 — rEQ_OUT vs. output current vs. VEAO, VOUT = 28V;
18 – 28VIN
3.5
0.50
150
3.0
VEAO (V)
6.0
0.00
4.0
IOUT@VIN = 18V
Figure 88 — GMOD vs output current vs. VEAO, VOUT = 28V;
18 – 28VIN
3.0
rEQ_OUT@VIN = 16V
200
GMOD@VIN = 28V
4.0
rEQ_OUT@VIN = 12V
5.0
IOUT@VIN = 28V
GMOD@VIN = 24V
IOUT@VIN = 16V
250
0.00
Output Current DC Amps
GMOD@VIN = 18V
IOUT@VIN = 24V
IOUT@VIN = 12V
0.0
VEAO (V)
IOUT@VIN = 18V
0
3.50
6.0
2.5
0.50
3.00
Figure 90 — rEQ_OUT vs. output current vs. VEAO, VOUT = 28V;
8 – 16VIN
GMOD (S)
Output Current DC Amps
Figure 87 — GMOD vs output current vs. VEAO, VOUT = 28V;
8 – 16VIN
0.0
0.00
2.50
Ohms
GMOD@VIN = 8V
2.00
VEAO (V)
Output Current DC Amps
IOUT@VIN = 8V
1.50
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
IOUT@VIN = 60V
IOUT@VIN = 36V
GMOD@VIN = 60V
Figure 89 — GMOD vs output current vs. VEAO, VOUT = 28V;
36 – 60VIN
Ohms
0.0
6.0
Ohms
3.5
Output Current DC Amps
6.0
GMOD (S)
Output Current DC Amps
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
rEQ_OUT@VIN = 36V
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 92 — rEQ_OUTvs. output current vs. VEAO, VOUT = 28V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 42 of 49 10/2021
PI3740-00
2.5
3.5
2
3.0
2.5
1.5
2.0
1
1.5
1.0
0.5
0.5
1.00
1.50
2.00
2.50
3.00
450
4.0
400
3.5
350
3.0
300
2.5
250
2.0
200
1.5
150
1.0
100
0.5
50
0.0
0.00
0
3.50
0.50
1.00
VEAO (V)
IOUT@VIN = 8V
GMOD@VIN = 8V
IOUT@VIN = 12V
IOUT@VIN = 16V
GMOD@VIN = 12V
IOUT@VIN = 8V
GMOD@VIN = 16V
rEQ_OUT@VIN = 8V
3.5
2
3.0
2.5
1.5
2.0
1
1.5
1.0
0.5
0.5
1.50
2.00
2.50
3.00
Output Current DC Amps
2.5
4.0
1.00
IOUT@VIN = 18V
IOUT@VIN = 24V
300
250
3.0
200
2.5
2.0
150
1.5
100
1.0
50
0.5
0.50
1.00
IOUT@VIN = 18V
rEQ_OUT@VIN = 18V
2.5
1.5
2.0
1.5
1
1.0
0.5
0.5
2.50
3.00
Output Current DC Amps
2
GMOD@VIN = 36V
GMOD@VIN = 48V
2.50
3.00
0
3.50
IOUT@VIN = 24V
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
350
4.0
300
3.5
250
3.0
2.5
200
2.0
150
1.5
100
1.0
50
0.5
0.0
0.00
0
3.50
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
VEAO (V)
IOUT@VIN = 48V
2.00
4.5
GMOD (S)
Output Current DC Amps
3.0
IOUT@VIN = 36V
1.50
Figure 97 — rEQ_OUTvs. output current vs. VEAO, VOUT = 36V;
18 – 28VIN
2.5
3.5
2.00
rEQ_OUT@VIN = 16V
3.5
GMOD@VIN = 28V
3
1.50
rEQ_OUT@VIN = 12V
4.0
IOUT@VIN = 28V
GMOD@VIN = 24V
4.0
1.00
IOUT@VIN = 16V
VEAO (V)
4.5
0.50
IOUT@VIN = 12V
350
0.0
0.00
0
3.50
Figure 94 — GMOD vs output current vs. VEAO, VOUT = 36V;
18 – 28VIN
0.0
0.00
0
3.50
4.5
VEAO (V)
GMOD@VIN = 18V
3.00
5.0
GMOD (S)
Output Current DC Amps
4.5
0.50
2.50
Figure 96 — rEQ_OUT vs. output current vs. VEAO, VOUT = 36V;
8 – 16VIN
3
5.0
0.00
2.00
VEAO (V)
Figure 93 — GMOD vs output current vs. VEAO, VOUT = 36V;
8 – 16VIN
0.0
1.50
Ohms
0.50
4.5
IOUT@VIN = 36V
IOUT@VIN = 60V
rEQ_OUT@VIN = 36V
GMOD@VIN = 60V
Figure 95 — GMOD vs output current vs. VEAO, VOUT = 36V;
36 – 60VIN
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 98 — rEQ_OUT vs. output current vs. VEAO, VOUT = 36V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 43 of 49 10/2021
Ohms
0.0
0.00
GMOD (S)
Output Current DC Amps
4.0
Output Current DC Amps
3
4.5
Ohms
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
PI3740-00
PI3740-00 Modulator Gain / Output Resistance TPCB = 25°C (Cont.)
1.4
2.0
1.2
1
1.5
0.8
0.6
1.0
0.4
0.5
0.2
1.50
2.00
2.50
3.00
3.50
GMOD@VIN = 8V
IOUT@VIN = 12V
GMOD@VIN = 12V
Output Current DC Amps
1.4
2.0
1.2
1
1.5
0.8
0.6
1.0
0.4
0.5
0.2
2.50
3.00
3.50
0
IOUT@VIN = 24V
0.0
0.00
Output Current DC Amps
1.2
1
0.8
GMOD (S)
Output Current DC Amps
1.4
0.6
0.4
0.5
0.2
0.50
1.00
1.50
2.00
2.50
3.00
3.50
0
GMOD@VIN = 36V
IOUT@VIN = 48V
GMOD@VIN = 48V
IOUT@VIN = 12V
IOUT@VIN = 16V
rEQ_OUT@VIN = 12V
rEQ_OUT@VIN = 16V
500
2.0
400
1.5
300
1.0
200
0.5
100
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
IOUT@VIN = 28V
rEQ_OUT@VIN = 24V
rEQ_OUT@VIN = 28V
700
2.5
600
500
2.0
400
1.5
300
1.0
200
0.5
100
0.50
1.00
1.50
2.00
2.50
3.00
0
3.50
VEAO (V)
IOUT@VIN = 60V
IOUT@VIN = 36V
GMOD@VIN = 60V
Figure 101 — GMOD vs output current vs. VEAO, VOUT = 50V;
36 – 60VIN
IOUT@VIN = 24V
3.0
0.0
0.00
VEAO (V)
IOUT@VIN = 36V
0
3.50
Figure 103 — rEQ_OUTvs. output current vs. VEAO, VOUT = 50V;
18 – 28VIN
1.6
1.0
3.00
2.5
rEQ_OUT@VIN = 18V
1.8
1.5
2.50
VEAO (V)
2
2.0
2.00
600
IOUT@VIN = 18V
Figure 100 — GMOD vs output current vs. VEAO, VOUT = 50V;
18 – 28VIN
2.5
1.50
3.0
GMOD@VIN = 28V
3.0
1.00
700
IOUT@VIN = 28V
GMOD@VIN = 24V
0.50
3.5
0.0
0.00
VEAO (V)
GMOD@VIN = 18V
100
Figure 102 — rEQ_OUT vs. output current vs. VEAO, VOUT = 50V;
8 – 16VIN
GMOD (S)
Output Current DC Amps
2.5
IOUT@VIN = 18V
200
0.5
rEQ_OUT@VIN = 8V
1.6
2.00
300
1.0
VEAO (V)
1.8
3.0
1.50
400
IOUT@VIN = 8V
2
1.00
500
1.5
GMOD@VIN = 16V
3.5
0.50
600
2.0
IOUT@VIN = 16V
Figure 99 — GMOD vs output current vs. VEAO, VOUT = 50V;
8 – 16VIN
0.0
0.00
700
0.0
0.00
VEAO (V)
IOUT@VIN = 8V
800
2.5
Ohms
1.00
900
3.0
Ohms
0.50
0
1000
Ohms
Output Current DC Amps
1.6
2.5
GMOD (S)
Output Current DC Amps
1.8
3.0
0.0
0.00
3.5
2
3.5
rEQ_OUT@VIN = 36V
IOUT@VIN = 48V
rEQ_OUT@VIN = 48V
IOUT@VIN = 60V
rEQ_OUT@VIN = 60V
Figure 104 — rEQ_OUT vs. output current vs. VEAO, VOUT = 50V;
36 – 60VIN
ZVS Regulators
Rev 2.8
Page 44 of 49 10/2021
PI3740-00
System Design Considerations
Inductive Loads: As with all power electronic applications,
consideration must be given to driving inductive loads that
may be exposed to a fault in the system which could result in
consequences beyond the scope of the power supply primary
protection mechanisms. An inductive load could be a filter, fan
motor or even excessively long cables. Consider an instantaneous
short circuit through an un-damped inductance that occurs when
the output capacitors are already at an initial condition of fully
charged. The only thing that limits the current is the inductance of
the short circuit and any series resistance. Even if the power supply
is off at the time of the short circuit, the current could ramp up in
the external inductor and store considerable energy. The release of
this energy will result in considerable ringing, with the possibility
of ringing nodes connected to the output voltage below ground.
The system designer should plan for this by considering the use of
other external circuit protection such as load switches, fuses, and
transient voltage protectors. The inductive filters should be critically
damped to avoid excessive ringing or damaging voltages. Adding a
high current Schottky diode from the output voltage to PGND close
to the PI3740-00 is recommended for these applications.
Low Voltage Operation: There is no isolation from an SELV
(Safety-Extra-Low-Voltage) power system. Powering low voltage
loads from input voltages as high as 60V may require additional
consideration to protect low voltage circuits from excessive voltage
in the event of a short circuit from input to output. A fast TVS
(transient voltage suppressor) gating an external load switch is an
example of such protection.
ZVS Regulators
Rev 2.8
Page 45 of 49 10/2021
PI3740-00
LGA Package Drawings
E1
A
G
K
E
D
A
1
2
3
4
5
6
7
D1
D
8
9
10
1
11
12
13
14
E
DETAIL B
1
DETAIL A
A
M
M
A
M
M
L
2
L
3
A2
A
DETAIL B
SEATING PLANE
METALLIZED
PAD
A1
SOLDER MASK
DETAIL A
A
A1
A2
AND POSITION
L
D
E
D1
E1
L1
ZVS Regulators
Rev 2.8
Page 46 of 49 10/2021
L1
PI3740-00
LGA Receiving PCB Pattern Design Recommendations
E1
PIN 1
D1
L
PCB LAND PATTERN
BB 10x14mm SiP
DIMENSIONAL REFERENCES
REF.
b
D1
E1
e
L
MIN.
0.50
0.50
NOM.
MAX.
0.55
0.60
13.00 BSC
9.00 BSC
1.00 BSC
0.55
0.60
Recommended receiving footprint for PI3740-00 10 x 14mm package. All pads should have a final copper size of 0.55 x 0.55mm,
whether they are solder-mask defined or copper defined, on a 1 x 1mm grid. All stencil openings are 0.45mm when using either a
5 or 6mil stencil.
ZVS Regulators
Rev 2.8
Page 47 of 49 10/2021
PI3740-00
Revision History
Revision
Date
Description
Page Number(s)
1.0
02/10/17
Initial Release
1.1
02/27/17
Current Sense Amplifier clarifications
8
1.2
03/10/17
Miscellaneous typo corrections
7
1.3
03/31/17
Correct LGH pin name
Include additional PCB Pattern information
5
46
1.4
04/27/17
Correct Absolute Min rating for VIN
3
1.5
06/05/17
Update IMON Output voltage specification
8
1.6
06/16/17
Add Maximum COUT Capability at Startup section
Correct Percentage of SiP Loss to Total Loss 50VOUT figure
Parallel Operation update
26
32
34
1.7
08/12/17
Update diagrams to show signal ground
1.8
08/24/17
Updated thermal impedance tables and thermal design inductor
28 – 30
Updated LGA package drawings
Added BGA package information
Updated UVLO threshold rising min, OVLO hysteresis, overvoltage threshold,
current sense amplifier IMON output at no load and
transconductance error amplifier reference min/max
46, 47
48, 49
n/a
1, 20, 35 – 37
1.9
06/15/18
2.0
10/12/18
2.1
11/05/18
Updated VIN OVLO threshold rising max spec
7
2.2
11/19/18
Updated VOUT overvoltage threshold min spec
7
2.3
02/04/20
Added extended-temperature and lead solder ball options
1, 3, 6 – 10
2.4
05/15/20
Updated to add recommended Pulse Electronics inductor
22
2.5
08/12/20
Updated terminology
2.6
02/22/21
Updated to include PI3040-00-LGMZ part number
2.7
05/06/21
Removed BGA package option
2.8
10/04/21
Revised inductor pairing information
Please note: Pages added in Rev 1.6 and 1.9; pages removed in Rev 2.7.
ZVS Regulators
Rev 2.8
Page 48 of 49 10/2021
7, 8, 9
22
1, 3, 6, 7, 8, 9, 10
1, 2, 3, 6, 7– 10
22
PI3740-00
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ZVS Regulators
Rev 2.8
Page 49 of 49 10/2021
