PI3749-00-EVAL1

End of Life Cool-Power® ZVS Switching Regulators PI3749-x0 16V to 34VIN, 12V to 28VOUT, 240W Cool-Power ZVS Buck-Boost Product Description Features & Benefits The PI3749-x0 is high efficiency, wide range DC-DC ZVS Buck‑Boost regulator. This high density System-in-Package (SiP) integrates controller, power switches, and support components. The integration of a high performance Zero-Voltage Switching (ZVS) topology, within the PI3749-x0, increases point of load performance providing best in class power efficiency. The PI3749-x0 requires an external inductor, resistive feedback divider and minimal capacitors to form a complete DC-DC switching mode buck-boost regulator. • Up to 98.5% efficiency at 800kHz FSW The ZVS architecture also enables high frequency operation while minimizing switching losses and maximizing efficiency. The high switching frequency operation reduces the size of the external filtering components, improves power density, and enables very fast dynamic response to line and load transients. • General Purpose Amplifier • Up to 240W of continuous output power (for specific conditions) • Fast transient response • Parallel capable with single wire current sharing • External frequency synchronization / interleaving • High Side Current Sense Amplifier • Input Over/Undervoltage Lockout (OVLO/UVLO) • Output Overvoltage Protection (OVP) • Overtemperature Protection (OTP) • Fast and slow current limits • -40°C to 115°C operating range (TJ) • Excellent light load efficiency • Optional I2C™ * functionality & programmability: ■■VOUT margining ■■Fault reporting ■■Enable and SYNCI pin polarity Applications • Computing, Communications, Industrial • Variable output step up/down voltage regulation Package Information • 10mm x 14mm x 2.56mm LGA SiP Typical Application VIN CIN VS1 VS2 VOUT PGND PGND VOUT COUT Efficiency (%) VIN ISP PI3749-00 ISN IMON VDR PGD VSN EN VSP R1 VDIFF SYNCO EAIN SYNCI TRK EAO SGND COMP 99 5 98 4.5 97 4 96 3.5 95 3 94 2.5 93 2 92 1.5 91 1 15 R2 20 30 VIN (V) Efficiency * I2C™ is a trademark of NXP semiconductor Cool-Power® ZVS Switching Regulators Page 1 of 27 25 Rev 2.1 09/2017 Power Dissipation 35 Power Dissipation (W) L1 End of Life PI3749-x0 Contents Order Information 3 Applications Information 17 Absolute Maximum Ratings 3 Input / Output Range Limitation 17 Pin Description 4 Output Voltage Trim 17 Package Pin-Out 5 Soft-Start Adjustment and Tracking 17 Large Pin Blocks 5 Inductor Pairing 17 Storage and Handling Information 6 Thermal De-rating 17 Block Diagram 6 Filter Considerations 18 Electrical Characteristics 7 Parallel Operation 19 Performance Characteristics 10 Synchronization 19 Efficiency & Power Loss 12 Interleaving 19 12 I2C Addressing 21 13 I2C Command Structure 21 MTBF 14 I2C Parameter Readback 22 Functional Description 15 Fault Monitoring 22 Safe Operating Area Thermal De-Rating Enable 15 I2C Volatile Addresses for Parameter Programming 22 Switching Frequency Synchronization 15 MRGN: Margin Control 23 Soft-Start and Tracking 15 Package Drawings 24 Remote Sensing Differential Amplifier 15 Receiving PCB Pattern Design Recommendations 25 Power Good 15 Revision History 26 Output Current Limit Protection 15 Product Warranty 27 Input Undervoltage Lockout 15 Input Overvoltage Lockout 15 Output Overvoltage Protection 15 Overtemperature Protection 16 Pulse Skip Mode (PSM) 16 Variable Frequency Operation 16 I2C 16 Interface Operation Cool-Power® ZVS Switching Regulators Page 2 of 27 Rev 2.1 09/2017 End of Life PI3749-x0 Order Information Part Number Description Package Transport Media MFG PI3749-00-LGIZ 16VIN to 34VIN SiP 10mm x 14mm 108-pin LGA TRAY Vicor PI3749-20-LGIZ 16VIN to 34VIN SiP I2C™ compatible 10mm x 14mm 108-pin LGA TRAY Vicor Absolute Maximum Ratings Note: Stresses beyond these limits may cause permanent damage to the device. Operation at these conditions or conditions beyond those listed in the Electrical Specifications table is not guaranteed. All voltage nodes are referenced to PGND unless otherwise noted. Location [2] VMAX VMIN ISOURCE [1] 40A [1] VIN 36V -0.7V 4-5,G-K VS1 36V -0.7VDC 40A [1] 18A [1] 10-11,G-K VS2 36V -0.7VDC 40A [1] 18A [1] 13-14,G-K VOUT 36V -0.7VDC 40A [1] 40A [1] 1E VDR 5.5V -0.3V 30mA 200mA 1D PGD 5.5V -0.3V 20mA 20mA 1C SYNCO 5.5V -0.3V 5mA 5mA 1B SYNCI 5.5V -0.3V 5mA 5mA 1A ADR1 5.5V -0.3V 5mA 5mA 2A ADR0 5.5V -0.3V 5mA 5mA 3A SCL 5.5V -0.3V 5mA 5mA 4A SDA 5.5V -0.3V 10mA 10mA 5A EN 5.5V -0.3V 5mA 5mA 6A TRK 5.5V -0.3V 50mA 50mA 7A LGH 5.5V -0.3V 5mA 5mA 8A COMP 5.5V -0.3V 5mA 5mA 9A VSN 5.5V -1.5V 5mA 5mA 10A VSP 5.5V -1.5V 5mA 5mA 11A VDIFF 5.5V -0.5V 5mA 5mA 12A EAIN 5.5V -0.3V 5mA 5mA 13A EAO 5.5V -0.3V 5mA 5mA 14A IMON 5.5V -0.3V 5mA 5mA 14D ISN [2] 40V -2VDC 5mA 5mA ISP [2] 40V -2VDC 5mA 5mA 10-14,B + 10-12,C-E SGND 0.3V -0.3V 200mA 200mA 2-9,B-E + 7-8,F-K PGND N/A N/A 18A [1] 18A [1] Non-Operating Test Mode Limits. The ISP pin to ISN pin has a maximum differential limit of +5.5VDC and -0.5VDC. Cool-Power® ZVS Switching Regulators Page 3 of 27 Rev 2.1 09/2017 40A ISINK 1-2,G-K 14E [1] Name End of Life PI3749-x0 Pin Description Pin Number Pin Name Description 1-2,G-K VIN Input voltage and sense node for UVLO, OVLO and feed forward compensation. 4-5,G-K VS1 Input side switching node and ZVS sense node for power switches. 10-11,G-K VS2 Output side switching node and ZVS sense node for power switches. 13-14,G-K VOUT 1E VDR Internal 5.1V supply for gate drivers and internal logic; not for external use. 1D PGD Fault & Power Good indicator. PGD pulls low when the regulator is not operating or if EAIN is less than 1.4V. 1C SYNCO Synchronization output. Outputs a high signal for ½ of the programmed switching period at the beginning of each switching cycle, for synchronization of other regulators. 1B SYNCI Synchronization input. When a falling edge synchronization pulse is detected, the PI3749-x0 will delay the start of the next switching cycle until the next falling edge sync pulse arrives, up to a maximum delay of two times the programmed switching period. If the next pulse does not arrive within two times the programmed switching period, the controller will leave sync mode and start a switching cycle automatically. Connect to SGND when not in use. 1A ADR1 I2C™ Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00. 2A ADR0 3A SCL I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00. 4A SDA I2C Clock, for use with the PI3749-20 only. Connect to SGND for PI3749-00. 5A EN Regulator Enable control. Asserted high or left floating = regulator enabled; asserted low, regulator output disabled. 6A TRK Soft-start and track input. An external capacitor may be connected between TRK pin and SGND to decrease the rate of output rise during soft-start. 7A LGH For factory use only. Connect to SGND in application. 8A COMP Output voltage and sense node for power switches, VOUT feed forward compensation, VOUT_OV and internal signals. I2C Addressing Pin, for use with PI3749-20 only. No connect for the PI3749-00. Error amp compensation dominant pole. Connect a capacitor between COMP and SGND to set the control loop dominant pole. 9A VSN General purpose amplifier inverting input 10A VSP General purpose amplifier non-inverting input 11A VDIFF General Purpose amplifier output. When unused connect VDIFF to VSN and VSP to SGND. 12A EAIN Error amplifier inverting input and sense for PGD. Connect by resistive divider to the output. 13A EAO Transconductance error amplifier output, PWM input and external connection for load sharing. Connect a capacitor between EAO and SGND to set the control loop high frequency pole. 14A IMON 14D ISN High side current sense amplifier negative input 14E ISP High side current sense amplifier positive input 10-14,B + 10-12,C-E SGND Signal ground. Internal logic and analog ground for the regulator. SGND and PGND are star connected within the regulator package. 2-9,B-E + 7-8,F-K PGND Power ground. VIN, VOUT, VS1 and VS2 power returns. SGND and PGND are star connected within the regulator package. Cool-Power® ZVS Switching Regulators Page 4 of 27 High side current sense amplifier output Rev 2.1 09/2017 End of Life PI3749-x0 Package Pin-Out 1 FT1 SYNCI SYNC0 PGD VDR VIN VIN VIN VIN 2 FT2 PGND PGND PGND PGND VIN VIN VIN VIN 3 FT3 PGND PGND PGND PGND 4 FT4 PGND PGND PGND PGND VS1 VS1 VS1 VS1 5 EN PGND PGND PGND PGND VS1 VS1 VS1 VS1 6 TRK PGND PGND PGND PGND 7 LGH PGND PGND PGND PGND PGND PGND PGND PGND PGND 8 COMP PGND PGND PGND PGND PGND PGND PGND PGND PGND 9 VSN PGND PGND PGND PGND 10 VSP SGND SGND SGND SGND VS2 VS2 VS2 VS2 11 VDIFF SGND SGND SGND SGND VS2 VS2 VS2 VS2 12 EAIN SGND SGND SGND SGND 13 EAO SGND VOUT VOUT VOUT VOUT 14 IMON SGND VOUT VOUT VOUT VOUT ISN ISP Large Pin Blocks Pin Block Name Group of pins VIN K1-2, J1-2, H1-2, G1-2 VS1 K4-5, J4-5, H4-5, G4-5 PGND K7-8, J7-8, H7-8, G7-8, F7-8, E2-9, D2-9, C2-9, B2-9 VS2 K10-11, J10-11, H10-11, G10-11 VOUT K13-14, J13-14, H13-14, G13-14 SGND E10-12, D10-12, C10-12, B10-14 Cool-Power® ZVS Switching Regulators Page 5 of 27 Rev 2.1 09/2017 End of Life PI3749-x0 Storage and Handling Information Maximum Storage Temperature Range -65°C to 150°C Maximum Operating Junction Temperature Range -40°C to 115°C Soldering Temperature for 20 seconds 245°C MSL Rating 3 ESD Rating [3] [3] 500V HBM; 1.0kV CDM JESD22-C101F, JESD22-A114F. Block Diagram VS1 VS2 VIN VOUT Q1 Q3 VS1 VS2 Q2 Q4 + + LDO VDR SYNCO SYNCI PGD EN FT1 - FT5 ZVS Buck Boost Control and Digital Parametric Trim + VREF 0Ω ADR0* ADR1* SDA* SCL* SGND *Simplified Block Diagram (I2C pins SCL, SDA, ADRO, ADR1, only active for PI3749-20 device version) Cool-Power® ZVS Switching Regulators Page 6 of 27 ISP IMON VSN VSP VDIFF EAIN EAO COMP CLAMP PGND ISN Rev 2.1 09/2017 TRK End of Life PI3749-x0 Electrical Characteristics Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V – 34V, VOUT = 24V, LEXT = 480nH [4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit 16 24 34 V Input Specifications Input Voltage VIN_DC Input Current IIN_DC IOUT = 4A, VIN = 24V, VOUT = 24V, TCASE = 25°C 4.06 A Input Current IIN_DC IOUT = 7.0A, VIN = 16V, VOUT = 24V, TCASE = 25°C 10.8 A [5] 2.5 mA IQ_VIN Enabled (no load) 6.6 mA VIN_SR [5] Input Current During Output Short (Fault Condition Duty Cycle) Input Quiescent Current Input Voltage Slew Rate IIN_SHORT Internal Input Capacitance CIN VIN UVLO Threshold Rising VIN_UVLO_START VIN UVLO Hysteresis VIN OVLO Threshold Rising VIN OVLO Hysteresis 1 50V, X7R type 25°C, VOUT = 0V 2 13.0 VIN_UVLO_HYS 14.1 µF 15.0 0.7 VIN_OVLO_START 35.2 VIN_OVLO_HYS 37.4 V/µs V V 39.5 0.75 V V Output Specifications Output Voltage Range VOUT_DC VIN = 16V to 34V 12 29 VIN = 24V to 34V 12 34 VIN =24V, VOUT = 24V, TCASE = 25°C [6] Output Current Steady State Output Power Steady State IOUT_DC POUT_DC VIN = 16V, VOUT = 24V, TCASE = 25°C [6] VIN = 24V, VOUT = 12V, TCASE = 25°C [6] VOUT_AC Internal Output Capacitance COUT VOUT Over Voltage Threshold VOUT_OVT V Drive VDR 7.2 A 10 163.2 VIN = 16V, VOUT = 24V, TCASE = 25°C [6] 172.8 VIN = 24V, VOUT = 12V, TCASE = 25°C Output Ripple 6.8 VIN = 24V, VOUT = 24V, TCASE = 25°C [6] [6] V W 120 IOUT = 4A, VIN = 24V, VOUT = 16V, Tcase = 25°C COUT_EX = 8 x 10µF, 50V, X7S, 20MHz BW 137 50V, X7R type 25°C, VOUT = 0V mVp-p 1 µF Rising VOUT threshold to detect open loop 35.2 37.4 39.5 V Internal drive supply, internal use only 4.84 5.10 5.36 V 150 260 µA Current Sense Amplifier (Dedicated to Monitor Input or Output Current) ISP Pin Bias Current (Sink) VOUT = 10V, Flows to SGND ISN Pin Bias Current VOUT = 10V 90 0 Common Mode Input Range 8 IMON Source Current 1 IMON Sink Current IMON Output At No Load µA 36 V 1.8 3 mA 1 1.6 2.6 mA 0 10 20 mV 4 % Full Scale Error 40mV input Bandwidth [5] 40 kHz Settling Time for Full Scale Step 1% 20 µs 20 V/V Gain -4 AV_CS [4] See Inductor Pairing section. [5] Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control. [6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17. Cool-Power® ZVS Switching Regulators Page 7 of 27 Rev 2.1 09/2017 End of Life PI3749-x0 Electrical Characteristics (Cont.) Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V – 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit General Purpose Amplifier Open Loop Gain [5] 96 120 140 dB Small Signal Gain-Bandwidth [5] 5 7 12 MHz -1 0.2 1 mV 2.5 V 2 V VDR - 0.2V V 20 mV 100 pF Offset Common Mode Input Range -0.1 Differential Mode Input Range Maximum Output Voltage IDIFF = -1mA Minimum Output Voltage No Load Capacitive Load for Stable Operation [5] 0 Slew Rate 10 Output Current -1 V/µs 1 mA 1.734 V 0 VDR V 3.45 4.0 V 0.1 V Transconductance Error Amplifier Reference VREF EAIN = EAO 1.667 Input Range VEAIN Note VEAIN_OV below Maximum Output Voltage Minimum Output Voltage 1.7 0 Transconductance Factory Set Zero Resistor EAO Output Current Sourcing EAO Output Current Sinking Open Loop Gain 7.6 mS Factory Set 7.0 kΩ VEAO = 50mV, VEAIN = 0V 400 µA VEAO = 2V, VEAIN = 5V 400 µA 80 dB ROUT > 1MΩ [5] 70 Control and Protection Switching Frequency FSW VIN = VOUT = 24V, IOUT = 2A 800 kHz Switching Frequency FSW VIN = 16V, VOUT = 12V, IOUT = 7A 480 kHz VEAO to SGND 0.6 V VEAO Pulse Skip Threshold Control Node Range VEAO Overload Threshold Overload Timeout VEAO_PST VRAMP V 3.2 3.4 V VEAO to SGND TOL VEAO > VEAO_OL 1 ms 10µs time constant 18 A 2.04 V 125 129 °C -0.35 -0.25 VOUT_SCL VEAIN Output Overvoltage Threshold VEAIN_OV Overtemperature Restart Hysteresis 3.3 VEAO_OL VOUT Slow Current Limit Overtemperature Fault Threshold 0 VEAIN > VEAIN_OV TOTP [5] TOPT_HYS [5] 30 VOUT Negative Fault Threshold [4] See Inductor Pairing section. Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control. [6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17. [5] Cool-Power® ZVS Switching Regulators Page 8 of 27 Rev 2.1 09/2017 °C -0.15 V End of Life PI3749-x0 Electrical Characteristics (Cont.) Specifications apply for the conditions -40°C < TJ < 115°C, VIN = 16V - 34V, VOUT = 24V, LEXT = 480nH[4], external CIN = COUT = 20µF, unless otherwise noted. Parameter Symbol Conditions Min Typ Max Unit 1.7 V 70 mV Soft Start and Tracking Function TRK Active Range Nominal 0 TRK Disable Threshold 20 TRK Internal Capacitance 0.047 Soft Start Charge Current 30 Soft Start Discharge Current Soft Start Time 40 tSS 50 µF 70 µA VTRK = 0.5V 8.5 mA Ext CSS = 0μF 1.6 ms Enable Enable High Threshold ENIH 0.9 1 1.1 V Enable Low Threshold ENIL 0.7 0.8 0.9 V ENHYS 100 200 300 mV Enable Threshold Hysteresis Enable Pin Bias Current VEN = 0V or VEN = 2V -50 µA Enable Pull-Up Voltage Floating 2.0 V 30 ms Fault Restart Delay Time tFR_DLY Digital Signals SYNCI Threshold Rising VDR = 5.1V 3.1 V SYNCI Threshold Falling VDR = 5.1V 2.2 V SYNCO High SYNCOOH SYNCO Low SYNCOOL VDR - 0.5 VDR V ISYNCOUT = 1mA 0.5 V PGD High Leakage PGDILH VPGD = VDR 10 µA PGD Output Low PGDOL IPGD = 4mA 0.4 V V PGD EAIN Low Rise 1.41 1.45 1.48 PGD EAIN Low Fall 1.36 1.41 1.46 PGD EAIN Threshold Hysteresis 35 PGD EAIN High 1.94 2.04 VADRx-HI 3.872 4.59 1.452 I 2C I2C™ I2C Address High Threshold V mV 2.14 V Digital Signals (PI3749-20 only) V Address Mid Threshold VADRx-MID I2C Address Low Threshold VADRx-LOW I2C Address Resistance, Within Mid Thresholds RADRx-MID Resistance to 2.5V, when ADRx pin voltage within VADRx_MID 10 V I2C Address Resistance, Outside Mid Thresholds RADRx-MID Resistance to 2.5V, when ADRx pin voltage outside range of VADRx_MID 200 V SCL, SDA In High VSER_IH SCL, SDA In Low VSER_IL SDA Out Low VSER_OL SCL, SDA Pull-Down Current ISER_I 0.51 V V 2.1 V 1.5 V Sinking up to 3mA 0.4 V Weak pull-down current to SGND 10 V [4] See Inductor Pairing section. Assured to meet performance specification by design, test correlation, characterization, and/or statistical process control. [6] Output current capability varies with input & output voltage. See performance curves in Figures 15 – 17. [5] Cool-Power® ZVS Switching Regulators Page 9 of 27 3.752 1.072 Rev 2.1 09/2017 End of Life PI3749-x0 Performance Characteristics TA = 25°C Efficiency (%) 100 95 90 85 80 0 1 2 3 4 5 6 7 Output Current (A) 16VIN 24VIN 34VIN Figure 4 — 34VIN to 12VOUT, COUT = 8 x 10µF Ceramic 5.0A Load Step at 5A/µs Figure 1 — 24VOUT Efficiency Efficiency (%) 100 95 90 85 80 0 1 2 3 4 5 6 7 8 9 10 11 Output Current (A) 16VIN 24VIN 34VIN Figure 2 — 12VOUT Efficiency Figure 5 — 24VIN to 24VOUT, COUT = 8 x 10µF Ceramic 3.0A Load Step at 5A/µs Efficiency (%) 100 95 90 85 80 0 1 2 3 4 5 6 7 8 Output Current (A) 16VIN Figure 3 — 28VOUT Efficiency 24VIN 34VIN Figure 6 — 16VIN to 28VOUT, COUT = 8 x 10µF Ceramic 3.0A Load Step at 5A/µs Cool-Power® ZVS Switching Regulators Rev 2.1 Page 10 of 27 09/2017 End of Life PI3749-x0 Operational Frequency (kHz) Performance Characteristics TA = 25°C (Cont.) 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 9 10 11 Output Current (A) 16VIN 24VIN 34VIN Operational Frequency (kHz) Figure 7 — Switching Frequency vs. Output Current @ 12VOUT Figure 10 — Start-up with 24VIN to 24VOUT at 5A 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 Output Current (A) 16VIN 24VIN 34VIN Operational Frequency (Hz) Figure 8 — Switching Frequency vs. Output Current @ 24VOUT Figure 11 — Short Circuit with 24VIN to 24VOUT at 5A 900 800 700 600 500 400 300 200 100 0 0 1 2 3 4 5 6 7 8 Output Current (A) 16VIN 18VIN 20VIN 24VIN 34VIN Figure 9 — Switching Frequency vs. Output Current @ 28VOUT Cool-Power® ZVS Switching Regulators Rev 2.1 Page 11 of 27 09/2017 End of Life Safe Operating Area TA = 25°C [7] 4.5 4 3.5 96.5 3 96 2.5 95.5 2 95 25 30 180 12 160 11 140 10 120 9 100 8 80 7 60 6 40 5 20 0 12 35 14 16 18 20 IOUT Power Dissipation 5 98 4.5 97 4 96 3.5 95 3 94 2.5 93 2 92 1.5 IOUT (A) 99 20 25 30 Current Limit 10 200 9 150 8 100 7 50 12 14 16 18 20 24 26 28 30 32 34 0 4.5 97.8 4 97.6 3.5 97.4 3 97.2 2.5 2 10 9 30 200 8 7 6 1.5 96.8 250 Safe Operating Area (SOA) IOUT (A) 5 98 POUT Figure 16 — Power and current output at 24VIN Power Dissipation (W) 98.2 Current Limit Non-Operating Area Efficiency (%) 5.5 97 5 35 12 14 16 18 IOUT Power Dissipation Figure 14 — 28VOUT Efficiency and Power Dissipation at 6A over Input Voltage Range 20 22 24 26 28 30 32 150 100 50 34 0 VOUT (V) VIN (V) [7] 22 VOUT (V) 6 Efficiency POUT 250 IOUT 98.6 25 34 11 Power Dissipation 98.4 20 32 300 35 Figure 13 — 24VOUT Efficiency and Power Dissipation at 7A over Input Voltage Range 15 30 12 VIN (V) Efficiency 28 6 1 15 26 Figure 15 — Power and current output at 34VIN Power Dissipation (W) Efficiency (%) Figure 12 — 12VOUT Efficiency and Power Dissipation at 7A over Input Voltage Range 91 24 VOUT (V) VIN (V) Efficiency 22 Current Limit POUT Figure 17 — Power and current output at VIN less than 24V Note: Testing was performed using a 3 in. x 3 in., four 2 oz. copper layers, FR4 evaluation board platform. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 12 of 27 09/2017 POUT (W) 20 200 13 4 1.5 15 14 POUT (W) 97 IOUT (A) Efficiency (%) 97.5 Power Dissipation (W) 98 POUT (W) Efficiency & Power Loss TA = 25°C [7] PI3749-x0 End of Life PI3749-x0 12 11 10 9 8 7 6 5 4 3 2 1 0 Maximum Output Current (A) Maximum Load Current (A) Thermal De-Rating [7] 25 35 45 55 65 75 85 95 105 8 7 6 5 4 3 2 1 0 20 30 40 16VIN 24VIN 7 Output Current (A) Maximum Load Current (A) 8 7 6 5 4 3 2 1 90 100 110 28VIN 34VIN 5 4 3 2 1 20 30 40 50 60 16VIN 70 80 90 100 0 110 20 30 40 24VIN 34VIN 24VIN 8 7 6 5 4 3 2 1 30 40 50 60 70 80 90 100 Ambient Temperature (°C) 16VIN 24VIN 60 70 80 90 100 110 30VIN 34VIN Figure 22 — Thermal de-rating @ VOUT = 34V with Limited Input Range (24VIN to 34VIN) 9 20 50 Ambient Temperature (°C) Figure 19 — Thermal de-rating @ VOUT = 24V Maximum Load Current (A) 80 6 Ambient Temperature (°C) 34VIN Figure 20 — Thermal de-rating @ VOUT = 28V [7] 70 Figure 21 — Thermal de-rating @ VOUT = 30V with Limited Input Range (24VIN to 34VIN) 8 0 60 24VIN 34VIN Figure 18 — Thermal de-rating @ VOUT = 12V 0 50 Ambient Temperature (°C) Ambient Temperature (°C) Note: Testing was performed using a 3 in. x 3 in., four 2 oz. copper layers, FR4 evaluation board platform. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 13 of 27 09/2017 End of Life PI3749-x0 MTBF PI3749-00-LGIZ vs. Temperature, Assuming 50% Derating and GB MTBF (Mhrs) 10000 1000 100 10 1 -60 -40 -20 0 20 40 60 80 100 Temperature (°C) MTBF Calculations Over Temperature Using Telcordia SR-332 Figure 23 — PI3749-x0 calculated MTBF Telcordia SR-332 GB Cool-Power® ZVS Switching Regulators Rev 2.1 Page 14 of 27 09/2017 120 140 End of Life Functional Description Soft-Start and Tracking The PI3749-x0 is part of a family of highly integrated ZVS Buck‑Boost regulators. The PI3749-x0 has a variable output voltage that is set with a resistive divider. Performance and maximum output current are characterized with a specific external power inductor as defined in electrical specifications, with Inductor Pairing section. L1 VIN VIN CIN VS1 The PI3749-x0 provides a soft start and tracking feature using the TRK pin. Programmable Soft Start requires an external capacitor from the TRK pin to SGND in addition to the internal 47nF soft‑start capacitor to set the start-up ramp period greater then tSS. The PI3749-x0 output will proportionately follow the TRK pin when it is below 1.7VDC. If the TRK pin is goes below the disable threshold, the regulator will finish the current switching cycle and then stop switching. Remote Sensing Differential Amplifier VS2 VOUT PGND PGND VOUT COUT ISP PI3749-00 ISN IMON VDR PGD VSN EN VSP R1 VDIFF SYNCO EAIN SYNCI TRK PI3749-x0 EAO SGND COMP R2 A general purpose operational amplifier is provided to assist with differential remote sensing and or level shifting of the output voltage. The VDIFF pin can be connected to the transconductance error amplifier input EAIN pin, or with proper configuration can also be connected to the EAO pin to drive the modulator directly. Power Good The PI3749-x0 PGD pin functions as a power good indicator and pulls low when the regulator is not operating or if EAIN is less than 1.4V. Output Current Limit Protection Figure 24 — ZVS Buck-Boost with required components For basic operation, Figure 24 shows the minimum connections and components required. Enable PI3749-x0 has three methods implemented to protect from output short circuit or over current condition. Slow Current Limit protection: prevents the output load from sourcing current higher than the maximum rated regulator current. If the output current exceeds the VOUT Slow Current Limit (VOUT_SCL) a slow current limit fault is initiated and the regulator is shutdown which eliminates output current flow. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. The EN pin of the regulator is referenced to SGND and permits the user to turn the regulator on or off. The EN polarity is a positive logic assertion. If the EN pin is left floating or asserted high, the regulator output is enabled. Pulling the EN pin below 0.8VDC with respect to SGND will discharge the SS/TRK pin until the output reaches zero or the EN pin is released. When the converter is disabled via the EN pin or due to a fault mode, the internal gate driver high side charge pumps are enabled as long as there is enough input voltage for the internal VDR supply voltage to be available. The return path for this charge pump supply is through the output. If the output load is disconnected or high impedance, the output capacitors will float up to about 3.4V maximum, sourced by 960µA of leakage current. This pre-biased condition poses no issue for the converter. The 960µA leakage current may be safely bypassed to SGND. A simple application circuit is available to bypass this current in a non-dissipative manner. Please contact Applications Engineering for details. Overload Timeout protection: If the regulator is providing maximum output power for longer than the Overload Timeout Delay (TOL), it will initiate a fault and stop switching. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the overload load is removed. Switching Frequency Synchronization Input Undervoltage Lockout The SYNCI input allows the user to synchronize the controller switching frequency to the falling edge of an external clock referenced to SGND. The external clock can synchronize the unit between 50% and 110% of the preset switching frequency (FSW ). The SYNCI pin should be connected to SGND when not in use, and should never be left floating. If VIN falls below the input Under Voltage Lockout (UVLO) threshold, the PI3749-x0 will complete the current cycle and stop switching. The system will restart once the input voltage is reestablished and after the Fault Restart Delay. Fast Current Limit protection: monitors the regulator inductor current pulse-by-pulse to prevent the output from supplying very high current. If the regulator senses a high inductor current pulse, it will initiate a fault and stop switching. After Fault Restart Delay (tFR_DLY ), a soft-start cycle is initiated. This restart cycle will be repeated indefinitely until the excessive load is removed. Input Overvoltage Lockout If VIN rises above the input Overvoltage Lockout (OVLO) threshold, the PI3749-x0 will complete the current cycle and stop switching. The system will restart once the input voltage is reestablished and after the Fault Restart Delay. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 15 of 27 09/2017 End of Life PI3749-x0 Output Overvoltage Protection IMON Amplifier The PI3749-x0 family is equipped with two methods of detecting an output overvoltage condition. Output Overvoltage Protection (OVP) to prevent damage to input voltage sensitive devices. If the output voltage exceeds 20% of its set regulated value as measured by the EAIN pin (VEAIN_OV ), the regulator will complete the current cycle, stop switching and issue an OVP fault. Also if the output voltage of the regulator exceeds the VOUT Overvoltage Threshold (VOUT_OVT ) then the regulator will complete the current cycle, stop switching and issue an OVP fault. The system will resume operation once the output voltage falls below the OVP threshold and after Fault Restart Delay. The PI3749-x0 provides a differential amplifier with a level shifted, SGND referenced output, the IMON Pin, which is useful for sensing input or output current on high voltage rails. A fixed gain of 20:1 is provided over a large common mode range. When using the amplifier, the ISN pin must be referenced to the common mode voltage of the ISP pin for proper operation. See Absolute Maximum Ratings for more information. If not in use, the ISN and ISP pins should be connected to SGND and the IMON pin left floating. Overtemperature Protection The internal package temperature is monitored to prevent internal components from reaching their thermal maximum. If the Overtemperature Protection Threshold is exceeded (TOTP), the regulator will complete the current switching cycle, enter a low power mode, set a fault flag, and will soft-start when the internal temperature decreases by more than the Overtemperature Restart Hysteresis (TOTP_HYS). I2C Interface Operation PI3749-20 devices provide an I2C digital interface that enables the user to: Device Configuration Options: nnDynamic VOUT margining nnProgrammable Sync Phase Delay Fault telemetry including: Pulse Skip Mode (PSM) PI3749-x0 features a hysteretic Pulse Skip Mode to achieve high efficiency at light loads. The regulator is setup to skip pulses if VEAO falls below the Pulse Skip Threshold (VEAO_PST ). Depending on conditions and component values, this may result in single pulses or several consecutive pulses followed by skipped pulses. Skipping cycles significantly reduces gate drive power and improves light load efficiency. The regulator will leave Pulse Skip Mode once the control node rises above the Pulse Skip Mode Threshold (VEAO_PST ). Variable Frequency Operation The PI3749-x0 is preprogrammed to a fixed, maximum, base operating frequency. The frequency is selected with respect to the required power stage inductor to operate at peak efficiency across line and load variations. The switching frequency period will stretch as needed during each cycle to accommodate low line and or high load conditions. By stretching the switching frequency period, thus decreasing the switching frequency, the ZVS operation is preserved throughout the input line voltage range maintaining optimum efficiency. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 16 of 27 09/2017 nnInput and Output Overvoltage nnInput and Output Undervoltage nnInternal Bias Supply Undervoltage nnOvertemperature Protection nnMulti Tiered Current Limit reporting End of Life Applications Information PI3749-x0 to startup and reach regulation at the same time (see Figure 25 (a)). To implement proportional tracking, simply connect all devices TRK pins together. Input / Output Range Limitation The PI3749-x0 is capable of wide step-up and step-down conversions, but high boosting ratios place thermal stress on the external inductor that may not be fully protected by the controller overtemperature shut down. For this reason boosting above 29V out when the input voltage is less than 24V is not supported. For Direct Tracking, choose the regulator with the highest output voltage as the master and connect the master to the TRK pin of the other regulators through a divider (Figure 26) with the same ratio as the slave’s feedback divider (see Output Voltage Trim). Master VOUT Output Voltage Trim The output voltage can be adjusted by feeding back a portion of the desired output through a voltage divider to the error amplifier’s input (see Figure 24). Equation 1 can be used to determine resistor values needed for the voltage divider. R1 = R2 • ( VOUT 1.7 ) The R2 value is selected by the user; a 1.07kΩ resistor value is recommended. If, for example, a 24V output is needed, the user can select a 1.07kΩ (1%) resistor for R2 and use equation (1) to calculate R1. Once R1 value is calculated, the user should select the nearest resistor value available. In this example, R1 is 14.03kΩ so a 14.0kΩ should be selected. Soft-Start Adjustment and Tracking The TRK pin offers a means to increase the regulator’s soft-start time or to track with additional regulators. The soft-start slope is controlled by an internal 47nF and a fixed charge current to provide a minimum startup time of 1.6ms (typical). By adding an external capacitor to the TRK pin, the soft-start time can be increased further. The following equation can be used to calculate the proper capacitor for a desired soft-start times: Where, tTRK is the desired soft-start time and ISS is the TRK pin source current (see Electrical Characteristics for limits). CTRK = 1.7 (2) – 47 • 10 -9 The PI3749-x0 allows the tracking of multiple like regulators. Two methods of tracking can be chosen: proportional or direct tracking. Proportional tracking will force all connected regulators R1 TRK Slave (1) -1 (tTRK • ISS ) PI3749 R2 SGND Figure 26 — Voltage divider connections for direct tracking All connected regulators’ soft-start slopes will track with this method. Direct tracking timing is demonstrated in Figure 25 (b). All tracking regulators should have their Enable (EN) pins connected together for proper operation. Inductor Pairing Operations and characterization of the PI3749-x0 was performed using a 480nH inductor, Part # HCV1206-R48-R, manufactured by Eaton. This Inductor has a form factor of 12.5mm x 10mm x 5mm. No other inductor is recommended for use with the PI3749-x0. For additional inductor information and sourcing, please contact Eaton directly. Thermal De-rating Thermal de-rating curves are provided (page 13) that are based on component temperature changes versus load current, input voltage and no air flow. It is recommended to use these curves as a guideline for proper thermal de-rating. These curves represent the entire system and are inclusive to both the SiP and the external inductor. Maximum thermal operation is limited by either the MOSFETs or inductor depending upon line and load conditions. All thermal testing was performed using a 3in. x 3in., four 2oz. copper layers, FR4 evaluation board platform. Thermal measurements were made on the five main power devices; the four internal MOSFETS and the external inductor. VOUT 1 VOUT 2 (a) Master VOUT VOUT 2 (b) t Figure 25 — PI3749-x0 tracking methods Cool-Power® ZVS Switching Regulators Rev 2.1 Page 17 of 27 09/2017 End of Life Filter Considerations The PI3749-x0 requires low impedance ceramic input capacitors (X7R/X5R or equivalent) to ensure proper start up and high frequency decoupling for the power stage. The PI3749-x0 will draw nearly all of the high frequency current from the low impedance ceramic capacitors when the main high side MOSFET(s) are conducting. During the time the MOSFET(s) are off, the input capacitors are replenished from the source. Table 1 shows the recommended input and output capacitors to be used for the PI3749-x0 as well as total RMS current, and input and output ripple voltages. Divide the total RMS current by the number of ceramic capacitors used to calculate the individual capacitor’s RMS current. Table 2 includes the recommended input and output ceramic capacitor. It is very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. Input Filter Case 1; Inductive source and local, external, input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series Rline Lline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified: Rline > (C IN_INT Rline RCIN_EXT Lline CIN_INT • RCIN_EXT < rEQ_IN (6) Equation (6) shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT ) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying Equation (5) should be considered the minimum. Note: When applying an electrolytic capacitor for input filter damping the ESR value must be chosen to avoid loss of converter efficiency and excessive power dissipation in the electrolytic capacitor. EQ_IN (4) Where, rEQ_IN can be calculated by dividing the lowest line voltage by the full load input current. It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, Equation (4). However, Rline cannot be made arbitrarily low otherwise Equation (3) is violated and the system will show instability, due to under-damped RLC input network. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 18 of 27 09/2017 End of Life PI3749-x0 Parallel Operation Synchronization PI3749-x0 can be connected in parallel to increase the output capability of a single output rail. When connecting modules in parallel, each EAO, TRK, and EN pin should be connected together. Current sharing will occur automatically in this manner so long as each inductor is the same value. EAIN pins should remain separated, each with an REA1 and REA2, to reject noise differences between different modules’ SGND pins. Up to three modules may be connected in parallel. The modules current sharing accuracy is determined by the inductor tolerance (±10%) and to a lesser extent, timing variation (±1.5%). Current sharing may be considered independent of synchronization and/or interleaving. Modules do not have to be interleaved or synchronized to share current. The following equation determines the output capability of N modules (up to three) to be determined: PI3749-x0 units may be synchronized to an external clock by driving the SYNCI pin. The synchronization frequency must not be higher than 110% of the programmed maximum value FSW. This is the switching frequency during DCM of operation. The minimum synchronization frequency is FSW / 2. In order to ensure proper power delivery during synchronization, the user should refer to the switching frequency vs. output current curves for the load current, output voltage and input voltage operating point. The synchronization frequency should not be lower than that determined by the curve or reduced output power will result. The power reduction is approximately the ratio between required frequency and synchronizing frequency. If the required frequency is 1MHz and the sync frequency is 600kHz, the user should expect a 40% reduction in output capability. ( ) Iarray = Imod + Imod • (N – 1) • 0.77 (7) Where: Iarray is the maximum output current of the array Imod is the maximum output per module N is the number of modules L1 CIN_1 VIN VS2 VOUT VS1 PGND PGND COUT_1 REA1_1 REA2_1 ISP ISN VDR EN PI3749-x0 TRK Interleaving is primarily done to reduce output ripple and the required number of output capacitors by introducing phase current cancellation. The PI3749-x0 has a fixed delay that is proportional to to the maximum value of FSW shown in the datasheet. When connecting two units as showin in Figure 58, they will operate at 180 degrees out of phase when the converters switching frequency is equal to FSW. If the converter enters CrCM and the switching frequency is lower than FSW, the phase delay will no longer be 180 degrees and ripple cancellation will begin to decay. Interleaving when the switching frequency is reduced to lower than 80% of the programmed maximum value is not recommended. Operation over high boost ratios such as 8V in to 36V out or narrow buck ratios like 28V in to 24V is not recommended for interleaving. VDIFF PGD EN LGH SYNCO 2.5kΩ IMON VSN VSP Interleaving EAIN SYNCI TRK EAO COMP SGND CHF_1 CCOMP_1 CTRK_1 L2 CIN_2 VIN VS2 VOUT VS1 PGND PGND ISP COUT_2 REA1_2 REA2_2 ISN VDR EN PI3749-x0 PGD EN VDIFF LGH SYNCO SYNCI TRK TRK CTRK_2 IMON VSN VSP SGND EAIN EAO COMP CHF_2 CCOMP_2 Figure 27 — PI3749-x0 parallel operation Cool-Power® ZVS Switching Regulators Rev 2.1 Page 19 of 27 09/2017 End of Life VOUT (V) VIN (V) 12 16 12 20 12 24 12 28 12 34 24 16 24 20 24 24 24 28 24 34 28 16 28 20 28 24 28 28 28 34 34 24 34 29 34 ILOAD (A) 34 5 7 6 9 6 10 6 11 7 11 5 7 5 7 5 7 5 7 5 7 6 9 5 7 5 6 5 7 4 6 5 7 4 6 3 5 CINPUT (see table 2) COUTPUT (see table 2) 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF 8 X 10µF 6 X 10µF CINPUT Ripple Current (IRMS) 8 X 10µF PI3749-x0 COUTPUT Ripple Current (IRMS) Output Ripple (mVpp) Input Ripple (mVpp) 3.55 3.65 37.1 67.5 4.59 4.89 60.6 113 4.45 4.43 44 84.3 6.08 6.32 80.5 162 4.68 4.36 40.2 81 6.93 6.84 88 184 5.06 4.34 43.4 90.1 7.66 7.21 95 217 5.78 4.64 50 125 7.8 6.76 87 240 5.13 4.49 75.4 63.5 7.08 6.07 138 114 4.28 3.91 61.6 56 5.3 4.6 85 75 4.24 4.13 64 82 4.7 4.5 68 88 4.55 4.4 68 105 5.1 5.1 74 121 5.1 4.66 72.5 142 5.93 5.67 83 176 7.18 6.5 143.5 108 10.62 9.37 301 223 5.09 4.65 84 70 6.49 5.51 122 95 4.68 4.46 82 83 5.06 4.68 87 83.5 4.66 4.54 83 107.5 5.31 5.16 93 119 4.5 4.18 77.4 130.6 5.49 5.26 95 168 5.6 5.39 124 95 6.66 5.76 148 100 4.5 4.5 107 107 5.6 5.33 133 122 3.87 3.7 90.4 118 5.12 4.95 124 160 Table 1 — Recommended input and output capacitance Part Number Description MFG Description C3225X7S1H106M250AB 10µF Capacitor, X7S 20% 50V, 1210 TDK Table 2 — Capacitor manufacturer part numbers Cool-Power® ZVS Switching Regulators Rev 2.1 Page 20 of 27 09/2017 End of Life PI3749-x0 I2C Addressing The PI3749-20 is hardware compatible with the NXP I2C™ Bus Specification Version 2.1, January 2000, in Standard Mode (100kHz) for all bus timing and voltage levels up to 5.5V. It operates as a slave on the I2C bus. The PI3749-20 I2C interface responds to the address programmed by the two I2C Address pins, ADR1 and ADR0. The address pins are three level inputs, providing nine possible combination pairs, although only eight of these combinations are unique, as shown in table 3. Considering only the 7 bit address sub-field, the high-order address bits through are hardcoded to 4’b1001, while the lower order address bits through are modified by the ADRx pins. ADDRx state Resultant I2C address sub-field Sub-field bit positions Fully formed address write word (including lsb of the transfer set for a write) ADR1 ADR0 Hexadecimal Decimal Binary Binary L L 7’h48 72 7’b100_1000 8’b1001_0001 L M 7’h49 73 7’b100_1001 8’b1001_0011 L H 7’h4A 74 7’b100_1010 8’b1001_0101 M L 7’h4B 75 7’b100_1011 8’b1001_0111 M M 7’h4C 76 7’b100_1100 8’b1001_1001 M H 7’h4D 77 7’b100_1101 8’b1001_1011 H L 7’h4E 78 7’b100_1110 8’b1001_1101 H M 7’h4F 79 7’b100_1111 8’b1001_1111 H H 7’h4F 79 7’b100_1111 8’b1001_1111 Table 3 — I2C Address selection Note that the state of the ADRx pins is resolved on each I2C address transfer. Therefore the PI3749-20 address can be changed while the regulator is powered up and in operation. I2C Command Structure Depending on the state of the read/write bit, two types of transfers are possible: a. Write: Data transferred from the I2C master to the PI3749-20 slave The first byte is transmitted by the master and includes the slave address and the R/W bit set to write (as shown in the last column of Table 3.) The second byte is also transmitted by the master and is the write data. The slave responds between each byte with an acknowledge bit. b. Read: Data returned from the PI3749-20 slave to the master The first byte is transmitted by the master and includes the slave address but the R/W bit is set to read. The slave responds to the first byte (the address transmitted by the master) with an acknowledge bit. The second byte is transmitted by the slave back to the master and is the read data. The master responds after the read data byte with a not-acknowledge bit (since the PI3749-20 read data are all single byte registers). Figure 28 — Data transfer on the I2C bus Per the I2C standard, the master generates all serial clock pulses, and all data is transferred MSB first. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 21 of 27 09/2017 End of Life PI3749-x0 I2C™ Parameter Readback Fault Monitoring Register Name Register Address Bit Bit Bit Bit Bit Bit Bit Bit FLT2 2 TRISE OTP VOUT_NEG VOUT_OV EAIN_HI VIN_OV VIN_UV VCC_UV FLT3 3 0 0 0 0 Q1_FIL Q3_SIL Q3_FIL SLOW_IL FLTREG_CLR 4 Write only, data ignored Table 4 — PI3749-20 Fault Readback/Clear Registers The fault bits in the FLT2 and FLT3 registers are only latched when the regulator first stops operating due to a given fault type. If the regulator is already not operating (perhaps due to a fault protection or being disabled) then should a new fault condition occur, the fault bit associated with the new fault will not be registered. Both versions of the PI3749-x0 will auto recover from any fault protection mechanism, once the fault is corrected. However in order to aid in monitoring of the regulator via the I2C fault monitoring registers, when a fault occurs, the associated fault bit(s) will set and latch until they are explicitly cleared by the I2C host using the FLTREG_CLR register. A write to the FLTREG_CLR register address will clear all latched fault register bits. Fault Bit Name Fault Bit Location TRISE FLT2, Bit Overtemperature Protection: The predicted maximum hot-spot temperature, based on measured temperature and loading, exceeded the maximum safe operating temperature. OTP FLT2, Bit Overtemperature Protection: The internal measured temperature exceeded the maximum safe operating temperature. VOUT_NEG FLT2, Bit VOUT negative fault. The output voltage was below ground. VOUT_OV FLT2, Bit Output Overvoltage protection. EAIN_HI FLT2, Bit Current Limit: Overload Timeout. VIN_OV FLT2, Bit Input Overvoltage Lockout. VIN_UV FLT2, Bit Input Undervoltage Lockout. VCC_UV FLT2, Bit VCC undervoltage. The internal bias supply faulted due to undervoltage. Q1_FIL FLT3, Bit Current Limit: Fast current limit (Q1) The peak current through Q1 and the inductor was higher than the maximum current allowed. Q3_SIL FLT3, Bit Current Limit: Slow current limit (Q3) Q3_FIL FLT3, Bit Current Limit: Fast current limit (Q3) The peak current through Q3 and the inductor was higher than the maximum current allowed. SLOW_IL FLT3, Bit Current Limit: Slow current limit. Fault Destination Table 5 — Fault register bit summary I2C Volatile Addresses for Parameter Programming Register Name Register Address Readback capable? Bit Bit Bit Bit MRGN 5 Yes MRGN_ENA MRGN MRGN MRGN Table 6 — PI3749-20 Parameter Programming Volatile Registers Cool-Power® ZVS Switching Regulators Rev 2.1 Page 22 of 27 09/2017 End of Life PI3749-x0 MRGN: Margin Control By default, output voltage margining is disabled, corresponding to B3 being cleared. In this case, the reference to the error amplifier is at its nominal value of 1.700V. When margining is enabled, the reference can be modified in 85mV steps according to Table 7. MRGN state MRGN data MRGN_ENA MRGN 1 Resultant Margin Function Margin active? Reference Voltage (V) 100 Yes 1.360 1 101 Yes 1.445 1 110 Yes 1.530 1 111 Yes 1.615 0 xxx No (data ignored), default 1.700 1 000 Yes 1.785 1 001 1.870 1 010 Yes Yes 1 011 Yes 1.955 2.040 Table 7 — Margin control register programming The MRGN state is always controlled by four bit wide volatile register. At power up, the register always resets to 4’b0000. The MRGN address can be freely read and written, as there are no one-time programmable fuses involved. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 23 of 27 09/2017 End of Life PI3749-x0 Package Drawings DETAIL A (SECTION VIEW) E PIN 1 INDEX ddd M C A B eee M C D b SEE NOTE 2 L PAD OPENING (b) b SEE NOTE 2 aaa C (4)PL TOP VIEW ddd M C A B eee M C DETAIL B BB 10x14mm SiP DIMENSIONAL REFERENCES REF. MIN. NOM. MAX. 2.49 2.56 2.63 A A1 --0.04 A2 --2.59 0.50 0.55 0.60 b D 14.00 BSC E 10.00 BSC D1 13.00 BSC E1 9.00 BSC e 1.00 BSC L .175 0.225 .275 DETAIL A E1 e SEE NOTE 1 e SEE NOTE 1 14 13 12 BB 10x14mm SiP DIMENSIONAL REFERENCES TOLERANCE OF FORM AND REF. POSITION 11 10 aaa bbb ccc ddd eee 9 8 D1 7 0.10 0.10 0.08 0.10 0.08 6 5 4 NOTES: 1. 'e' REPRESENTS THE BASIC TERMINAL PITCH. SPECIFIES THE TRUE GEOMETRIC POSITION OF THE TERMINAL AXIS. 3 2. DIMENSION 'b' APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.00mm AND 0.25mm FROM TERMINAL TIP. 2 3. DIMENSION 'A' INCLUDES PACKAGE WARPAGE 1 4. EXPOSED METALLIZED PADS ARE Cu PADS WITH SURFACE FINISH PROTECTION. PIN 1 INDEX A B C D E F G H J K DETAIL B BOTTOM VIEW 5. RoHS COMPLIANT PER CST-0001 LATEST REVISION. 6. ALL DIMENSIONS ARE IN MM UNLESS OTHERWISE SPECIFIED. bbb C A2 A SEE NOTE 3 ccc C SEATING PLANE b C Cool-Power® ZVS Switching Regulators Rev 2.1 Page 24 of 27 09/2017 A1 End of Life PI3749-x0 Receiving PCB Pattern Design Recommendations E1 PIN 1 e e D1 b PCB LAND PATTERN b BB 10x14mm SiP DIMENSIONAL REFERENCES REF. MIN. NOM. MAX. b 0.50 0.55 0.60 D1 13.00 BSC E1 9.00 BSC e 1.00 BSC Recommended receiving footprint for PI3749-x0 10mm x 14mm package. All pads should have a final copper size of 0.55mm x 0.55mm, whether they are solder-mask defined or copper defined, on a 1mm x 1mm grid. All stencil openings are 0.45mm when using either a 5mil or 6mil stencil. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 25 of 27 09/2017 End of Life PI3749-x0 Revision History Revision Date Description 1.0 04/13/15 Initial Release n/a 1.1 07/14/15 Updated conditions column Added additional specifications Clarified parameters and updated typical Corrected labels Corrected labels Inductor Pairing updated 7 8 9 10 15 18 1.2 08/03/15 Inductor value corrected 7-9 1.3 09/03/15 Added I2C capability throughout all 1.4 10/12/15 Added documentation for I2C capability Changed frequency units for readability Reformatted for readability 1.5 04/08/16 Updated VDIFF description 1.6 09/27/16 Power level updated 1.7 02/14/17 Corrections to Typical Application, Figure 24 Package drawings updated 1, 15 5, 23, 24 1.8 03/31/17 Correct LGH pin name Parallel Operation section updated Include additional PCB Pattern information 3-5 18 24 1.9 05/31/17 Update Absolute Maximum Ratings Update IMON Output voltage 2.0 06/14/17 Parallel Operation update 2.1 09/15/17 Updated functional description of enable Please note: Page added in Rev 2.0. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 26 of 27 09/2017 Page Number(s) 1, 4, 6, 7, 8, 9 & 20 11 19 4 ALL 3 7 18-19 15 End of Life PI3749-x0 Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems. Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor makes no representations or warranties with respect to the accuracy or completeness of the contents of this publication. Vicor reserves the right to make changes to any products, specifications, and product descriptions at any time without notice. Information published by Vicor has been checked and is believed to be accurate at the time it was printed; however, Vicor assumes no responsibility for inaccuracies. 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No license, whether express, implied, or arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Interested parties should contact Vicor’s Intellectual Property Department. The products described on this data sheet are protected by U.S. Patents. Please see www.vicorpower.com/patents for the latest patent information. Contact Us: http://www.vicorpower.com/contact-us Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 www.vicorpower.com email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com ©2017 – 2020 Vicor Corporation. All rights reserved. The Vicor name is a registered trademark of Vicor Corporation. All other trademarks, product names, logos and brands are property of their respective owners. Cool-Power® ZVS Switching Regulators Rev 2.1 Page 27 of 27 09/2017