Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
PRM™
Regulator
FEATURES
DESCRIPTION
The V•I Chip™ PRM™ Regulator is a high efficiency
converter, operating from a 38 to 55 Vdc input to generate
a regulated 5 to 55 Vdc output. The ZVS buck – boost
topology enables high switching frequency (~1 MHz)
operation with high conversion efficiency. High switching
frequency reduces the size of reactive components
enabling power density up to 1,360 W/in3.
45 V (38 to 55), non-isolated ZVS buck-boost regulator
5 to 55 V adjustable output range
Building block for high efficiency DC-DC systems
400W output power in 1.1 in2 footprint
97% typical efficiency, at full load
1,360 W/in3 (83 W/cm3) Power Density
Enables a 48 V to 1.5 V, 230 A isolated, regulated
solution with total footprint of 3.3 in2 (21 cm2)
Flexible “Remote Sense” architecture optimizes
regulation / feedback loop design to fit application
requirements
Current feedback signal allows dynamic adjustment of
current limit setpoint
3.61 MHrs MTBF (MIL-HDBK-217Plus Parts Count)
The full V•I Chip package is compatible with standard pickand-place and surface mount assembly processes with a
planar thermal interface area and superior thermal
conductivity.
In a Factorized Power Architecture™ system, the
PRM48BF480T400A00 and downstream VTM™ current
multiplier minimize distribution and conversion losses in a
high power solution.
TYPICAL APPLICATIONS
An external control loop and current sensor maintain
regulation and enable flexibility both in the design of
voltage and current compensation loops to control of
output voltages and currents.
High Efficiency Server Processor and Memory Power
High Density ATE System DC-DC Power
Telecom NPU and ASIC Core Power
LED Drivers
High Density Power Supply DC-DC Rail Outputs
Non-isolated Power Converters
48 V to 1.5 V, 230A Voltage Regulator
Voltage
Control
Feedback
Enable/
Disable
Voltage
Reference
PC
PR
+IN
TM
+OUT
PC
38 to 55
Vdc Input
-IN
IF RE
VTMTM Current
Multiplier
-IN
-OUT
SG VC
VC
Current
Sense
Constant
Vc
+OUT1
+OUT2
+IN
PRMTM
Regulator
Load
-OUT1
-OUT2
PC
+OUT1
+OUT2
+IN
VTMTM Current
Multiplier
-IN
VC
-OUT1
-OUT2
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 1 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
1.0 ABSOLUTE MAXIMUM RATINGS
The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All
voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.
PR
………………………………………………………………………..
PC
………………………………………………………………………..
TM
………………………………………………………………………..
+IN to –IN ……………………………………………………………………………
VS
………………………………………………………………………..
SG ……………………………………………………………………………
IF ……………………………………………………………………………
RE ……………………………………………………………………………
VC to –OUT
+OUT to –OUT
Output Current
Operating Analog IC Junction Temperature
Storage Temperature
………………………………………………………………………..
……………………………………………………………………………
……………………………………………………………………………
……………………………………………………………………………
……………………………………………………………………………
Min
-0.3
-0.3
-0.3
-1
-0.5
-0.5
-0.3
-0.5
-1
-40
-40
Max
10.5
±10
5.7
±10
5.7
±1
62
10.5
±100
±100
5.7
5
18
±1.8
62
±11
125
125
Unit
V
mA
V
mA
V
mA
V
V
mA
mA
V
V
V
A
V
A
ºC
ºC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20V to 55V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Attribute
Conditions / Notes
Symbol
Min
Typ
Max
Unit
38
0.001
45
55
1000
4
8.5
11.0
V
V/ms
W
mA
A
F
mΩ
55
8.33
400
V
A
W
POWER INPUT SPECIFICATION
Input Voltage Range
VIN Slew Rate
No Load Power Dissipation
Input Quiescent Current
Input Current
Input Capacitance (Internal)
Input Capacitance (Internal) ESR
VIN
dVIN/dt
PNL
IQC
IIN DC
CIN INT
RCin
0 < VIN < 18 V
PC HIGH, VIN = 45 V
PC LOW, VIN = 45 V
IOUT = 8.33A, VIN = 38 V, VOUT = 48 V
Effective value, VIN = 45 V (see Fig. 20)
2.4
4.5
10.9
4
1.5
POWER OUTPUT SPECIFICATION
Output Voltage Range
Output Current
Output Power
VOUT
IOUT
POUT
Output Turn-ON Delay
TON
Current Sharing Difference
(exclusive of current limit)
Efficiency
Output Discharge current
Output Voltage Ripple
Output Inductance (Parasitic)
Output Capacitance (Internal)
Output Capacitance (Internal) ESR
POWERTRAIN PROTECTIONS
Input Undervoltage Turn-ON
Input Undervoltage Turn-OFF
Input Overvoltage Turn-ON
Input Overvoltage Turn-OFF
Overcurrent (IF) and Input
Over/Undervoltage Blanking Time
Output Overvoltage Threshold
Thermal Shutdown Setpoint
Overtemperature, Output Overvoltage
and PC Shutdown Response Time
Short Circuit Vout Threshold
Short Circuit Vout Recovery Threshold
Short Circuit Vpr Threshold
Short Circuit Vpr Recovery Threshold
Short Circuit Timeout
Short Circuit Recovery Time
Output Power Limit
IOUT_SHARE
η
IOD
VOUT PP
LOUT PAR
COUT INT
RCout
VIN UVLO+
VIN UVLOVIN OVLO+
VIN OVLO-
5
See Fig.16, SOA
See Fig.16, SOA
From VIN applied, PC floating
From PC pin release, VIN applied, TOFF expired
Equal input, output and PR voltage at full load;
VIN = 45 V, VOUT = 48 V
Equal input, output and PR voltage at full load;
Over line and trim, with 25°C < TC < 100°C but negligible part-part temp mismatch
Equal input, output and PR voltage at full load;
Over line and trim, with 25°C < TC < 100°C and 50% load; over temperature
Section 4.0
COUT_EXT = 0 F, IOUT = 8.33 A, VIN = 45 V, VOUT = 48 V, 20 MHz BW
Frequency @ 1 MHz, Simulated J-Lead model
Effective value, VOUT = 48 V (see Fig. 20)
TBLNK
VOUT OVLO+
TJ OTP
Instantaneous, latched shutdown
Instantaneous, latched shutdown; guaranteed by design, not production tested; VTM = 4.03V
s
20
96.5
94.8
90.0
±10
%
±24
%
±35
%
97.4
13
960
1.9
4
1.5
Instantanous powertrain shutdown, latched after TBLNK
Instantanous powertrain shutdown, latched after TBLNK
48
1500
%
%
%
mA
mV
nH
F
mΩ
31.97
55.91
35.75
33.56
57.24
58.44
59.91
V
V
V
V
50
120
150
s
55.25
130
56.57
59.04
V
ºC
37.13
TPROT
2
s
VSC VOUT
VSC VOUTR
VSC VPR
VSC VPRR
TSC
TSCR
PPROT
3.0
4.0
7.2
7.1
20
0.1
V
V
V
V
ms
ms
W
Short circuit fault latched after VSC_VOUT and VSC_VPR thresholds persist for this time
400
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 2 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted.
Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Primary Control
PC
• The PC pin enables and disables the PRM
• In PRM array configurations, PC pins should be connected in order to synchronize startup.
• It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a short circuit fault is latched.
Signal Type
State
Conditions / Notes
Attribute
Symbol
VPC
PC Voltage
Regular
Operation
IPC_OP
PC Available Current
Analog Output
After TOFF
IPC_EN
PC Source Current
Startup
TOFF
Minimum Time to Start
Section 5.0
VPC_EN
Startup
PC Enable Threshold
VPC_DIS
Digital Input / Output
PC Disable Threshold
Standby
RPC_EXT Resistance to SG required to disable the PRM
PC Resistance (External)
IPC_SC
Short circuit, PC voltage 1 V or above
Digital Output [Short Circuit Fault]
Fault
PC Sink Current to SG
IPC_FAULT Tempature, over- and undervoltage, overcurrent
Digital Output [All other Faults]
Fault
PC Sink Current to ~1V
Voltage Source
VS
• Intended to power feedback components and/or auxiliary circuits.
• 9 V, 5mA regulated voltage source
• With > 5% output load, VS ripple typically 100mV
Signal Type
State
Attribute
VS Voltage
Regular
VS Available Current
Operation
Analog Output
VS Voltage Ripple
Transition
VS Capacitance (External)
VS Fault Response Time
Conditions / Notes
Symbol
VVS
IVS
VVS_PP
CVS_EXT
TFR_VS
Transition
RE Voltage Ripple
PC to RE Delay
RE Capacitance (External)
VS to RE Delay
Control Node
PR
• Modulator control node input
• Sinks constant current when externally driven in active range
• Sources current when pulled below active range
Signal Type
State
Attribute
PR Voltage Active Range
PR Source Current
Regular
Analog Input
Operation
PR Sink Current
PR Resistance to SG
VRE_PP
TPC_RE
CRE_EXT
TVS_RE
Symbol
VPR
IPR
IPR_Low
RPR
10.0
1.75
Typ
5
Max
5.3
90
18.0
2.50
2.40
30.0
3.20
300
25
10
Min
8.55
5
Iout = 0A, Cvs_ext=0. Maximum specification
includes powertrain operation in burst mode.
Typ
9.00
100
From fault recognition to VS = 1.5 V
Reference Enable
RE
• RE signals successful startup and a powertrain that is ready for operation
• Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor
Signal Type
State
Conditions / Notes
Attribute
Symbol
VRE
RE Voltage
Regular
IRE
RE Available Current
Operation
%RE
across load and temperature
RE Regulation
Analog Output
Min
4.7
1.8
Max
9.45
Unit
V
mA
400
mV
0.04
F
s
Max
3.6
Unit
V
30
Min
3.0
Typ
3.3
8.0
2.5
100
100
in burst mode
Fault detected
0.1
VS = 8.1 V to RE high, VIN > VIN_UVLO-
Conditions / Notes
1
mA
%
mV
s
F
ms
Min
0.79
Typ
Max
7.40
2
Unit
V
mA
250
500
93.3
750
A
kΩ
VPR 0.79V
VPR 0.79V
Unit
V
mA
A
ms
V
V
Ω
mA
Current Feedback
IF
• A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)
• Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLNK
Signal Type
State
Conditions / Notes
Min
Typ
Max
Attribute
Symbol
VIN = 45 V; TJ = 25 °C
VIF_IL
Current Limit (clamp) Threshold
1.90
2.00
2.10
Not Production Tested; Guaranted by Design;
VIF_OC
Regular
Overcurrent Protection Threshold
2.58
2.69
2.80
TJ = 25 °C
Analog Input
Operation
RIF
IF Input Impedance
2.13
2.11
2.15
BWIL
Current Limit Bandwidth
2
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Unit
V
kΩ
kHz
Rev. 1.2
07 / 2012
Page 3 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
Temperature Monitor
TM
• The TM pin monitors the internal temperature of the PRM analog control IC.
• "Power Good" flag to verify that the PRM is operating
Signal Type
State
Attribute
TM Voltage
TM Voltage reference
Regular
Analog Output
TM Voltage Ripple
Operation
TM Available Current
TM Gain
Digital Output [Fault Flag]
Fault or Standby TM Disabled Current
Symbol
VTM
VTM_AMB
VVS_PP
ITM
ATM
ITM_DIS
Conditions / Notes
Full temperature range
TJ = 27 °C
Min
2.12
2.94
Powertrain in burst mode
Typ
3.00
200
Max
4.04
3.06
100
DC state with TM Voltage +/- 0.5V. This is a high
impedance state.
Unit
V
V
mV
A
10
mV/°C
0.0
mA
Signal Ground
SG
• All control signals must be referenced to this pin, with the exception of VC
• SG is internally connected to -IN and -OUT
Signal Type
State
Attribute
Analog Input / Output
Any
Maximum Allowable Current
Symbol
ISG
Conditions / Notes
Min
-100
Typ
Max
100
Unit
mA
VTM Control
VC
• Pulsed voltage source used to power and synchronize downstream VTM
• If not used, must be resistively terminated to -OUT
Signal Type
State
Attribute
VC Voltage
Symbol
VVC
Conditions / Notes
RVC_EXT = 68
VC 20 V
Min
13
200
7
Typ
Max
10
20
16
Unit
V
mA
ms
V/s
Analog Output
Startup
VC Available Current
VC duration
VC Slew Rate
IVC
TVC
dVC/dt
RVC = 1k
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 4 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
4.0 FUNCTIONAL BLOCK DIAGRAM
+Vin
+Vout
Vcc
Vcc
3.3V
Linear
Regulator
Internal
Vcc
Regulator
-Vin
PC
16V
PR Vout
Cin
Cout
3.3V
Q3
Q1
uC 8051
RE
L
-Vout
+Vout
9V
Q4
Q2
Output
Discharge
(OD)
8.2V
PR
Modulator
PR
93.3k
Enable
Var. Vclamp
2.5mA Min
VTM Vc Start up pulse
0.5mA
14V
VC
10ms
Vcc
100uA
Q
Q
SET
CLR
Fault Logic
TOFF
delay
S
Instant
latch
R
R
Vout
(OV)
5V
2mA max
3V
RE
RE
Latch after
120us
3.3V
Vin
(OV, UV)
Vs
9V
0.01uF
Enable
PC
10uA
PC
VPC_EN
Overtemperature
Protection
TM
3 V @ 27°C
SG
Current Limit
VIF_IL
Overcurrent
Protection
Temperature
dependent voltage
source
IF
Vref
(130°C)
VIF_OC
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 5 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 6 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
6.0 TIMING DIAGRAMS
Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following:
Single PRM (no array)
VS powers error amplifier
RE powers voltage reference and output current transducer
IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load
2
1
Start up with
1.2V/ms < dVIN/dt < maximum
VIN
OV
TOFF
3
4
Quick OC Input OV
(t 45º : for the closed loop response, the
phase should be greater than 45º where the gain crosses
0dB.
2) Gain Margin > 10dB : The closed loop gain should be
lower than -10dB where the phase crosses 0º.
3) Gain Slope = -20dB/decade : The closed loop gain
should have a slope of -20dB/decade at the crossover
frequency.
The compensation characteristics must be selected to
meet these stability criteria. Refer to Figure 27 for a local
sense, voltage-mode control example based on the
configuration in Figure 26. In this example, it is assumed
that the maximum crossover frequency (FCMAX) has been
selected to occur between B and C. Type-2 compensation
(Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
Modulator Gain GPR: See Figures 17, 18, 19
Powertrain equivalent resistance rEQ: See Figures
17, 18, 19
rEQ _ OUT RLOAD
Main pole frequency:
FP
10.2.3 Control loop compensation requirements
rEQ _ OUT RLOAD
1
2 π
rEQ _ OUT RLOAD
rEQ _ OUT RLOAD
Compensation Mid-Band Gain:
G MB 20 log
R3
R1
[1]
Compensation Zero:
FZ1
COUT _ INT COUT _ EXT
1
2 π R 3 C1
[2]
Compensation Pole:
FP 2
1
R C C
2 π 3 1 2
C1 C2
and for FP2>>FZ1 (C1 + C2 ≈ C1):
FP 2
1
2 R3 C2
[3]
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 17 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
10.2.4 Midband Gain Design (R1,R3):
10.2.5 Compensation Zero Design (C1):
With reference to Figure 27: curve ABC is the:
minimum output voltage in the application
maximum input voltage expected in the application
maximum load
PRM open loop response, and is where the maximum
crossover frequency occurs. In order for the maximum
crossover frequency to occur at the design choice FCMAX,
the compensation gain must be equal and opposite of the
powertrain gain at this frequency. For stability purposes,
the compensation should be in the Mid-band (J-K) at the
crossover. Using Equation [1], the mid-band gain can be
selected appropriately.
With reference to Figure 27: curve EFG is the:
maximum output voltage in the application
minimum input voltage expected in the application
minimum load in the application
PRM open loop response, and is where the minimum
crossover frequency FCMIN occurs. Based on stability
criteria, the compensation must be in the mid-band at the
minimum crossover frequency, therefore FCMIN will occur
where EFG is equal and opposite of GMB. C1 can be
selected using Equation [2] so that FZ1 occurs prior to
FCMIN.
TM
PRM
Regulator
Figure 26 – Control circuit example
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 18 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
Open Loop Gain vs. Frequency
80
60
Gain (dB)
40
20
I
Application's op-amp G·BW
Compensation Gain
F
E
PRM Open Loop Min Load
B
A
PRM Open Loop Max Load
J
K
L
FCMIN
0
FCMAX
-20
C
G
-40
Frequency, Log scale
(y-intercept is application specific)
Figure 27 – Reference asymptotic Bode plot for the considered system
10.2.6
High Frequency Pole Design (C2):
based on the ratio of the “kick” to “droop” (as defined in
Fig. 28).
Using Equation [3], C2 should be selected so that FP2 is at
least one decade above FCMAX and prior to the gain
bandwidth product of the operational amplifier (10MHz for
this example). For applications with a higher desired
crossover frequency the use of a high gain bandwidth
product amplifier may be necessary to ensure that the real
pole can be set at least one decade above the maximum
crossover frequency.
10.2.7 Verifying Stability:
The preferred method for verifying stability is to use a
network analyzer, measuring the closed loop response
across various lines and load conditions.
In the absence of a network analyzer, a load step transient
response can be used in order to estimate stability.
Figure 28 illustrates an example of a load step response.
Equation [4] can be used to predict the phase margin
Figure 28 – load step response example and “droop”
vs. “kick” definition
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 19 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
2
k
ln
d
m 100
2
k
2
ln
d
[4]
Figure 20 provides the effective internal capacitance of the
module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by
equation [5]:
QTOT
V
10.3
Burst Mode Operation:
At light loads, the PRM will operate in a burst mode due to
minimum timing constraints. An example burst operation
waveform is illustrated in Figure 29.
For very light loads, and also for higher input voltages, the
minimum time power switching cycle from the powertrain
will exceed the power required by the load. In this case the
external error amplifier will periodically drive PR below the
switching threshold in order to maintain regulation.
Switching will cease momentarily until the error amplifier
once again drives PR voltage above the threshold.
CINT
I FL 0.4
f SW
C EXT
[5]
QTOT is the total input (Fig. 15) or output (Fig. 14) charge
per switching cycle at full load, while CINT is the module
internal effective capacitance at the considered voltage
(Fig. 20) and CEXT is the external effective capacitance at
the considered voltage.
10.5
Input filter stability
The PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply
source as well as the interconnecting line are stable and
do not oscillate. For this purpose, the converter dynamic
input impedance magnitude rEQ _ IN is provided in Figures
22, 23, 24. It is recommended to provide adequate design
margin with respect to the stability conditions illustrated in
10.5.1 and 10.5.2 .
10.5.1 Inductive source and local, external input
decoupling capacitance with negligible ESR (i.e.: ceramic
type)
Figure 29 – light load burst mode of operation
Note that during the bursts of switching, the powertrain
frequency is constant, but the number of pulses as well as
the time between bursts is variable. The variability
depends on many factors including input voltage, output
voltages, load impedance, and external error amplifier
output impedance.
In burst mode, the gain of the PR input to the plant which
is modeled in the previous sections is time varying.
Therefore the small signal analysis can not be directly
applied to burst mode operation.
10.4
Input and Output filter design
Figures 14 and 15 provide the total input and output
charge per cycle, as well as switching frequency, of the
PRM at full load under various input and output voltages
conditions.
The voltage source impedance can be modeled as a
series RlineLline circuit. The high performance ceramic
decoupling capacitors will not significantly damp the
network because of their low ESR; therefore in order to
guarantee stability the following conditions must be
verified:
Rline
(C IN _ INT
Lline
C IN _ EXT ) rEQ _ IN
Rline rEQ _ IN
[6]
[7]
It is critical that the line source impedance be at least an
octave lower than the converter’s dynamic input
resistance, [7]. However, Rline cannot be made arbitrarily
low otherwise equation [6] is violated and the system will
show instability, due to under-damped RLC input network.
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 20 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
10.5.2 Inductive source and local, external input
decoupling capacitance with significant RCIN_EXT ESR (i.e.:
electrolytic type)
In order to simplify the analysis in this case, the voltage
source impedance can be modeled as a simple inductor
Lline. Notice that, the high performance ceramic capacitors
CIN_INT within the PRM should be included in the external
electrolytic capacitance value for this purpose. The
stability criteria will be
rEQ _ IN RC IN _ EXT
[8]
Lline
rEQ _ IN
C IN _ EXT RC IN _ EXT
[9]
Equation [9] shows that if the aggregate ESR is too small
– for example by using very high quality input capacitors
(CIN_EXT) – the system will be under-damped and may even
become destabilized. Again, an octave of design margin in
satisfying [8] should be considered the minimum.
10.6
Arrays
Up to ten PRMs of the same type may be placed in
parallel to expand the power capacity of the system. The
following high-level guidelines must be followed in order
for the resultant system to start up and operate properly,
and to avoid overstress or exceeding any absolute
maximum ratings.
–IN pins of all PRMs must be connected together.
Both inductance and resistance from the common
power source to each PRM should be minimized,
and matched.
Input voltage to all PRMs must be the same.
Independent fuses for each PRM are
recommended.
PC pins must be connected together for
synchronization and proper fault response.
Reference supply to the control loop voltage
reference and current sense circuitry must be
enabled when all modules’ RE pins have reached
their operational voltage levels.
There must be one single external voltage control
loop. The control loop must drive each PR pin
relative to each modules’ SG pin, and the local PR
voltage must be the same across all modules.
Each PRM must have its own local current shunt
and current sense circuitry to drive it’s IF pin.
The number of PRMs required to achieve a given
array capacity must consider all sources of
mismatch to avoid overstress of any PRM in the
array. Imbalances in sharing are not only due to
current sharing accuracy specifications, but also
temperature differences among PRMs, Vin
variations, and error terms in the buffering of the
error amplifier output to the PR pins.
Control loop compensation procedures above will
hold for an array, in general, although many
parameters must be scaled against the number of
PRMs in the system.
Please contact Vicor Applications for assistance.
10.7
Input Fuse Recommendations
A fuse should be incorporated at the input to each PRM, in
series with the +IN pin. A 15A or smaller input fuse
®
2®
451/453 Series, or equivalent) is
(Littelfuse NANO
required to safety agency conditions of acceptability.
Always ascertain and observe the safety, regulatory, or
other agency specifications that apply to your specific
application.
10.8
Layout considerations
Application Note AN:005 details board layout using V•I
Chip components. Additional consideration must be given
to the external control circuit components.
The current sense shunt signal voltage is highly sensitive
to noise. As such, current sensing circuitry should be
located close to the shunt to minimize the length of the
sense signals. A Kelvined connection at the shunt is
recommended for best results.
The control signal from a remote voltage sense circuit to
the PRM should be shielded. Avoid routing this, or other
control signals directly underneath the PRM, if possible.
Components that tie directly to the PRM should be located
close to their respective pins. It is also critical that all
control components be referenced to SG, and that SG not
be tied to any other ground in the system, including –IN or
–OUT of the PRM.
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 21 of 22
Not Recommended for New Designs
PRM48BF480T400A00
(Formerly VIP0001TFJ)
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in
normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application
or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original
purchaser only.
EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED,
INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR
PURPOSE.
Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty,
the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products
returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the
product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty.
Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is
assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve
reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or
circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not
recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten
life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes
all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC
modules and accessory components, fully configurable AC-DC and DC-DC power supplies,
and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for
its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or
malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are
available upon request.
Specifications are subject to change without notice.
Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent
applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual
Property Department.
The products described on this data sheet are protected by the following U.S. Patents Numbers:
5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917;
7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for
use under 6,975,098 and 6,984,965.
Vicor Corporation
25 Frontage Road
Andover, MA, USA 01810
Tel: 800-735-6200
Fax: 978-475-6715
email
Customer Service: custserv@vicorpower.com
Technical Support: apps@vicorpower.com
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.2
07 / 2012
Page 22 of 22
