PRM® Regulator
PRM48BH480T200B00
S
C
NRTL
US
High Efficiency Remote Sense PRM Converter
FEATURES
DESCRIPTION
®
TYPICAL APPLICATIONS
•
•
•
•
•
•
®
The VI Chip PRM Regulator is a high efficiency
converter, operating from a 38 to 55 Vdc input to generate
a regulated 5 to 55 Vdc output. The ZVS Buck – Boost
topology enables high switching frequency (~1 MHz)
operation with high conversion efficiency. High switching
frequency reduces the size of reactive components
3
enabling power density up to 1,300 W/in .
• 45 V (38 to 55 VIN), non-isolated ZVS buck-boost
regulator
• 5 to 55 V adjustable output range
• Building block for high efficiency DC-DC systems
2
• 200 W Output Power in 0.57 in footprint
• 97% typical efficiency, at full load
3
3
• 1,300 W/in (81 W/cm ) Power Density
• Enables a 48 V to 1.5 V, 130 A isolated, regulated
2
2
solution with total footprint of 1.7 in (11 cm )
• Flexible “Remote Sense” architecture optimizes
regulation / feedback loop design to fit application
requirements
• Current Feedback signal allows dynamic adjustment of
current limit setpoint
• 4.93 MHrs MTBF (MIL-HDBK-217Plus Parts Count)
High Efficiency Server Processor and Memory Power
High Density ATE system DC-DC power
Telecom NPU and ASIC core power
LED drivers
High Density Power Supply DC-DC rail outputs
Non-isolated power converters
The half VI Chip package is compatible with standard pickand-place and surface mount assembly processes with a
planar thermal interface area and superior thermal
conductivity.
In a Factorized Power Architecture™ system, the
®
PRM48BH480T200B00 and downstream VTM
transformer minimize distribution and conversion losses in
a high power solution.
An external control loop and current sensor maintain
regulation and enable flexibility both in the design of
voltage and current compensation loops to control of
output voltages and currents.
48 V to 1.2 V, 130A Voltage Regulator
Voltage
Control
Feedback
Enable/
Disable
Voltage
Reference
PR
PC
TM
+OUT
+IN
38 to 55
Vdc Input
PRM
-IN
IF RE
IM
PC
+IN
TM
+OUT1
+OUT2
-IN
-OUT
SG VC
VC
Current
Sense
VTM
PRM® Regulator
Rev 1.1
vicorpower.com
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7/2015
800 927.9474
-OUT1
-OUT2
Load
PRM48BH480T200B00
1.0 ABSOLUTE MAXIMUM RATINGS
The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause
permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All
voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.
PR
………………………………………………………………………..
PC
………………………………………………………………………..
TM
………………………………………………………………………..
+IN to –IN ……………………………………………………………………………
VS
………………………………………………………………………..
SG ……………………………………………………………………………
IF ……………………………………………………………………………
RE ……………………………………………………………………………
VC to –OUT
+OUT to –OUT
Output Current
Operating Analog IC Junction Temperature
Storage Temperature
………………………………………………………………………..
……………………………………………………………………………
……………………………………………………………………………
……………………………………………………………………………
……………………………………………………………………………
Min
-0.3
Max
10.5
±10
5.7
±10
5.7
±1
62
10.5
±100
±100
5.7
5
18
±1.8
62
±5.5
125
125
-0.3
-0.3
-1
-0.5
-0.5
-0.3
-0.5
-1
-40
-40
Unit
V
mA
V
mA
V
mA
V
V
mA
mA
V
V
V
A
V
A
ºC
ºC
2.0 ELECTRICAL CHARACTERISTICS
Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20 V to 55 V, unless otherwise
noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Attribute
Symbol
Conditions / Notes
Min
Typ
Max
Unit
38
0.001
45
55
1000
4
8.5
5.7
V
V/ms
W
mA
A
µF
mΩ
55
4.17
200
±10
V
A
W
µs
ms
%
See sec 10.6
%
POWER INPUT SPECIFICATION
VIN
dVIN/dt
P NL
I QC
IIN_DC
CIN_INT
RCin
Input Voltage range
VIN Slew Rate
No Load Power Dissipation
Input Quiescent current
Input Current
Input Capacitance (Internal)
Input Capacitance (Internal) ESR
0 < VIN < 18 V
PC High, VIN = 45 V
PC Low, VIN = 45 V
IOUT = 4.17 A, VIN = 38 V, V OUT = 48 V
Effective value, V IN = 45 V (see Fig. 20)
2.6
4.5
5.5
2
3
POWER OUTPUT SPECIFICATION
V OUT
I OUT
P OUT
TON
TOFF + TON
Output Voltage range
Output Current
Output Power
Output Turn-ON Delay
Current Sharing accuracy
Efficiency
Output
Output
Output
Output
Output
Discharge current
Voltage Ripple
Inductance (Parasitic)
Capacitance (Internal)
Capacitance (Internal) ESR
IOUT_PS
η
I OD
VOUT_PP
LOUT_PAR
COUT_INT
RCout
5
See Fig.16, SOA
See Fig.16, SOA
From PC pin release to V OUT, VIN pre-applied and TOFF already expired
From VIN applied to V OUT, PC floating
Equal input, output and PR voltage at full load; V IN = 45 V, V OUT = 48 V, exclusive of current limit
Equal input, output and PR voltage at full load;
Over line, trim, and temperature; exclusive of current limit
Nominal line, full load, V OUT = 48V
50% load and VOUT = 48 V; over temperature
50% load; over temperature
Section 4.0
COUT_EXT = 0 F, IOUT = 4.17 A, VIN = 45 V, V OUT = 48 V, 20 MHz BW
Frequency @ 1 MHz, Simulated J-Lead model
Effective value, V OUT = 48 V (see Fig. 20)
48
20
18.02
95.7
94.5
88.5
96.9
0.5
1020
2.5
2
3
1500
%
%
%
mA
mV
nH
µF
mΩ
POWERTRAIN PROTECTIONS
Input Undervoltage Turn-ON
Input Undervoltage Turn-OFF
Input Overvoltage Turn-ON
Input Overvoltage Turn-OFF
Overcurrent (IF) and Input
Over/Undervoltage Blanking Time
Output Overvoltage Threshold
Thermal Shutdown Setpoint
Overtemperature, Output Overvoltage
and PC Shutdown Response Time
Short Circuit Vout Threshold
Short Circuit Vout Recovery Threshold
Short Circuit Vpr Threshold
Short Circuit Vpr Recovery Threshold
Short Circuit Timeout
Short Circuit Fault Recovery Time
Output Power Limit
VIN_UVLO+
VIN_UVLOVIN_OVLO+
VIN_OVLOTBLANK
VOUT_OVLO+
TJ_OTP
TPROT
VSC_VOUT
VSC_VOUTR
VSC_VPR
VSC_VPRR
TSC
TSCR
P PROT
Instantanous powertrain shutdown, latched after TBLANK
Instantanous powertrain shutdown, latched after TBLANK
Instantaneous, latched shutdown
Instantaneous, latched shutdown; guaranteed by design, not production tested; V TM = 4.03V
35.75
33.56
57.24
58.44
37.13
31.97
55.91
59.91
V
V
V
V
50
120
150
µs
55.25
130
56.57
59.04
V
ºC
2
3.0
4.0
7.2
7.1
20
0.1
Short Circuit fault latched after V SC_VOUT and V SC_VPR thresholds persist for this time
200
PRM® Regulator
Rev 1.1
vicorpower.com
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7/2015
800 927.9474
µs
V
V
V
V
ms
ms
W
PRM48BH480T200B00
3.0 SIGNAL CHARACTERISTICS
Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20 V to 55 V, unless otherwise
noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Primary Control
PC
• The PC pin enables and disables the PRM
• In PRM array configurations, PC pins should be connected in order to synchronize startup.
• It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a Short Circuit fault is latched.
Signal Type
State
Attribute
Symbol
Conditions / Notes
V PC
Regular
PC Voltage
Operation
IPC_OP
PC Available Current
Analog Output
IPC_EN
After TOFF
PC Source Current
Startup
TOFF
Minimum Time to Start
Section 5.0
VPC_EN
Startup
PC Enable Threshold
Digital Input / Output
VPC_DIS
PC Disable Threshold
Standby
RPC_EXT Max Resistance to SG required to disable the PRM
PC Resistance to disable
IPC_SC
Digital Output [Short Circuit Fault]
Fault
PC Sink Current to SG
Short circuit, PC Voltage 1 V or above
IPC_FAULT Temperature, Over- and Under-Voltage, Overcurrent
Digital Output [All other Faults]
Fault
PC Sink Current to ~1V
Min
4.7
Voltage Source
VS
• Intended to power feedback components and/or auxiliary circuits.
Signal Type
State
Attribute
VS Voltage
Regular
VS Available Current
Operation
Analog Output
VS Voltage Ripple
Transition
Signal Type
State
Regular
Operation
Transition
Control Node
PR
• Modulator control node input
• Sinks constant current when externally driven
• Sources current when pulled below active range
Signal Type
State
Analog Input
Attribute
CVS_EXT
TFR_VS
1.8
1.75
18.0
2.50
2.40
30.0
3.20
300
25
10
Conditions / Notes
Iout = 0A, Cvs_ext=0. Maximum specification
includes powertrain operation in burst mode.
mA
90
10.0
Min
8.55
5
Typ
9.00
100
From fault recognition to VS = 1.5 V
Unit
V
µA
ms
V
V
Ω
mA
µΑ
Max
9.45
Unit
V
mA
400
mV
0.04
µF
µs
Unit
30
Min
Typ
Max
V RE
3.0
3.3
3.6
V
RE Available Current
RE Regulation
RE Voltage Ripple
PC to RE Delay
RE Capacitance (External)
I RE
%RE
VRE_PP
TPC_RE
CRE_EXT
8.0
across load and temperature
includes powertrain in burst mode
Fault detected
0.1
mA
%
mV
µs
µF
VS to RE Delay
TVS_RE
VS = 8.1 V to RE high, V IN > VIN_UVLO-
RE Voltage
Analog Output
Regular
Operation
Attribute
PR Voltage Active Range
PR Source Current
PR Sink Current
PR Resistance to SG (Internal)
VVS_PP
Max
5.3
Reference Enable
RE
• RE signals successful startup and powertrain ready to operate
• Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor
VS Capacitance (External)
VS Fault Response Time
Symbol
V VS
IVS
Typ
Symbol
Symbol
V PR
IPR
IPR_Low
Conditions / Notes
Conditions / Notes
VPR ≤ 0.79V
VPR > 0.79V
±2.5
100
100
1
ms
Min
0.79
Typ
Max
7.40
Unit
V
2
mA
250
500
750
µA
RPR
93.3
kΩ
Current Feedback
IF
• A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp)
• Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLANK
Signal Type
Analog Input
PRM® Regulator
Page 3 of 22
State
Regular
Operation
Attribute
Current Limit (clamp) Threshold
Symbol
VIF_IL
Overcurrent Protection Threshold
VIF_OC
IF Input Impedance
Current Limit Bandwidth
RIF
BW IL
Conditions / Notes
VIN = 45 V; TJ = 25 °C
Not Production Tested; Guaranteed by Design;
TJ = 25 °C
Rev 1.1
vicorpower.com
7/2015
800 927. 9474
Min
1.90
Typ
2.00
Max
2.10
2.58
2.69
2.80
2.11
2.13
2
2.15
Unit
V
kΩ
kHz
PRM48BH480T200B00
Temperature Monitor
TM
• The TM pin monitors the internal temperature of the PRM analog control IC.
• "Power Good" flag to verify that the PRM is operating
Signal Type
State
Attribute
TM Voltage
TM Voltage reference
Analog Output
Regular
TM Voltage Ripple
Operation
TM Available Current
Digital Output [Fault Flag]
Min
2.12
Typ
Max
4.04
VTM_AMB
TJ = 27 °C
2.94
3.00
3.06
VVS_PP
I TM
TM Disabled Current
I TM_DIS
Signal Ground
SG
• All control signals must be referenced to this pin, with the exception of VC
• SG is internally connected to -IN and -OUT
Signal Type
State
Attribute
Analog Input / Output
Any
Maximum Allowable Current
Symbol
ISG
VTM Control
VC
• Pulsed voltage source used to power and synchronize start up of downstream VTM
• If not used, must be resistively terminated to -OUT
Signal Type
State
Attribute
VC Voltage
Symbol
VVC
Analog Output
Startup
VC Current Limit
VC duration
VC Slew Rate
Conditions / Notes
Full temperature range
powertrain in burst mode
IVC
TVC
dVC/dt
DC state with TM Voltage +/- 0.5V. This is a high
impedance state.
RVC = 68Ω
Unit
V
V
350
mV
µA
10
mV/°C
100
ATM
TM Gain
Fault or
Standby
Symbol
V TM
0.0
mA
Conditions / Notes
Min
-100
Typ
Max
100
Unit
mA
Conditions / Notes
Min
13
Typ
Max
Unit
V
200
7
500
10
16
VC = 14 V, VIN > 20 V
RVC = 1kΩ
PRM® Regulator
Rev 1.1
vicorpower.com
Page 4 of 22
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800 927. 9474
20
mA
ms
V/ µs
PRM48BH480T200B00
4.0 FUNCTIONAL BLOCK DIAGRAM
+Vin
Vcc
Vcc
3.3V
Linear
Regulator
Internal
Vcc
Regulator
PR Vout
PC
Cin
uC 8051
16V
9V
L
PR
8.2V
Cout
Q3
Q1
RE
+Vout
3.3V
-Vin
+Vout
Q4
Q2
-Vout
Output
Discharge
(OD)
Modulator
PR
93.3kW
100uA
Q
SET
Q
CLR
14V
VC
10ms
Fault Logic
Instant
latch
R
VTM Vc Start up pulse
TOFF
delay
S
2.5mA Min
Enable
Var. Vclamp
0.5m
A
Vcc
RE
Latch after
120us
RE
3.3V
R
Vout
(OV)
5V
2mA max
3V
Vin
(OV, UV)
Vs
9V
0.01uF
Enable
PC
10uA
VPC_EN
TM
PC
3 V @ 27°C
Temperature
dependent voltage
source
Overtemperature
Protection
Current Limit
Overcurrent
Protection
Vref
(130°C)
PRM® Regulator
Rev 1.1
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Page 5 of 22
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800 927. 9474
VIF_IL
SG
2130W
VIF_OC
IF
PRM48BH480T200B00
5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM
Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
Application of
Vin
PC HIGH
and
Toff expiry
Toff Timeout
PC: 90uA to HIGH
Powertrain Stopped
STANDBY
SEQUENCE
PC: 10uA to LOW
STARTUP
SEQUENCE
PC: 1.8mA to HIGH
Overtemp or Output
OVP
PC HIGH
and
Ton expiry
Fault
removed
TBLNK
expiry
Ton timeout;
VC Pulse;
Powertrain Active
Delayed RE
BLANKING
PC: 1.8mA to HIGH
TBLNK Timeout
Powertrain Paused
Input OVP,
Input UVP,
or
OverCurrent Prot
SUSTAINED
OPERATION
PC: 1.8mA to HIGH
Powertrain Active
Short Circuit:
Vout < VSC_Vout
and
Vpr > VSC_Vpr
PC
falling
edge
Vout < 1 V
And
TSCR expiry
Short Removed:
Vout > VSC_VOUTR
or
Vpr < VSC_VPR_R
OUTPUT DISCHARGE
PC: pulsed 25mA drive
LOW
TSC
expiry
TSCR Timeout
Powertrain Stopped
IOD Output Discharge
PRM® Regulator
Rev 1.1
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Page 6 of 22
7/2015
800 927. 9474
SHORT
CIRCUIT
PC: 1.8mA to HIGH
TSC Timeout
Powertrain Active
PC
falling
edge
PRM48BH480T200B00
6.0 TIMING DIAGRAMS
Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following:
Single PRM (no array)
VS powers error amplifier
RE powers voltage reference and output current transducer
IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load
2
1
Start up with
1.2V/ms < dVIN/dt < maximum
VIN
OV
TOFF
3
4
Input OV
recovery
Quick OC Input OV
(t 10dB : The closed loop gain should be
lower than -10dB where the phase crosses 0º.
3) Gain Slope = -20dB / decade : The closed loop gain
should have a slope of -20dB / decade at the crossover
frequency.
The compensation characteristics must be selected to
meet these stability criteria. Refer to Figure 27 for a local
sense, voltage-mode control example based on the
configuration in Figure 26. In this example, it is assumed
that the maximum crossover frequency (FCMAX) has been
selected to occur between B and C. Type-2 compensation
(Curve IJKL) is sufficient in this case.
The following data must be gathered in order to proceed:
Modulator Gain GPR: See Figures 17, 18, 19
Powertrain equivalent resistance rEQ: See Figures
17, 18, 19
1
F ≈
2 π⋅
rEQ _ OUT · RLOAD
rEQ _ OUT + RLOAD
Compensation
G MB = 20 log
R
Mid-Band
OUT
INT
+ COUT
[1]
R1
Zero:
1
F =
Gain:
3
Compensation
· (C
[2]
2 π⋅ R 3 ⋅ C1
Z1
Compensation
Pole:
1
FP 2 =
⋅C
2 π⋅ R3 ⋅ C1 2
C1 + C2
and for FP2>>FZ1 (C1 + C2 ≈ C1):
F
P2
≈
1
2π ⋅ R3 ⋅ C2
PRM® Regulator
Rev 1.1
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Page 17 of 22
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800 927. 9474
[3]
EXT
)
PRM48BH480T200B00
10.2.4 Midband
(R1,R3):
Gain
Design
10.2.5 Compensation Zero Design (C1):
With reference to Figure 27: curve ABC is the:
minimum output voltage in the application
maximum input voltage expected in the application
maximum load
PRM open loop response, and is where the maximum
crossover frequency occurs. In order for the maximum
crossover frequency to occur at the design choice FCMAX,
the compensation gain must be equal and opposite of the
powertrain gain at this frequency. For stability purposes,
the compensation should be in the Mid-band (J-K) at the
crossover. Using Equation [1], the mid-band gain can be
selected appropriately.
With reference to Figure 27: curve EFG is the:
maximum output voltage in the application
minimum input voltage expected in the application
minimum load in the application
PRM open loop response, and is where the minimum
crossover frequency FCMIN occurs. Based on stability
criteria, the compensation must be in the mid-band at the
minimum crossover frequency, therefore FCMIN will occur
where EFG is equal and opposite of GMB. C1 can be
selected using Equation [2] so that FZ1 occurs prior to
FCMIN.
C2
C1
R3
+
Vref
R2
R1
F1
+IN
VS
PR
RS
+OUT
CIN_EXT
CIN_INT
PRM
COUT_EXT
COUT_INT
-IN
IF RE
SG
-OUT
Vref
I sense
IC
Vref IC
Figure 26 – Control circuit example
PRM® Regulator
Rev 1.1
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PRM48BH480T200B00
Open Loop Gain vs. Frequency
80
60
I
Application's op-amp G·BW
Compensation Gain
40
Gain (dB)
20
F
E
PRM Open Loop Min Load
B
A
PRM Open Loop Max Load
J
K
FCMIN
0
L
FCMAX
-20
C
G
-40
Frequency, Log scale
(y-intercept is application specific)
Figure 27 – Reference asymptotic Bode plot for the considered system
10.2.6
High Frequency Pole Design (C2):
Using Equation [3], C2 should be selected so that FP2 is at
least one decade above FCMAX and prior to the gain
bandwidth product of the operational amplifier (10 MHz for
this example). For applications with a higher desired
crossover frequency the use of a high gain bandwidth
product amplifier may be necessary to ensure that the real
pole can be set at least one decade above the maximum
crossover frequency.
based on the ratio of the “kick” to “droop” (as defined in
Fig. 28).
k
Vout
d
10.2.7 Verifying
Stability:
The preferred method for verifying stability is to use a
network analyzer, measuring the closed loop response
across various lines and load conditions.
In the absence of a network analyzer, a load step transient
response can be used in order to estimate stability.
Figure 28 illustrates an example of a load step response.
Equation [4] can be used to predict the phase margin
time
Iou
t
time
Figure 28 – load step response example and “droop”
vs. “kick” definition
PRM® Regulator
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PRM48BH480T200B00
10.3
k2
ln
m 100
d2
k
+ 2
ln
d
Burst
Operation:
Figure 20 provides the effective internal capacitance of the
module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by
equation [5]:
[4]
ΔV =
Mode
QTO T
CINT
I
FL
⋅ 0.4
f SW
+ CEXT
[5]
At light loads, the PRM will operate in a burst mode due to
minimum timing constraints. An example burst operation
waveform is illustrated in Figure 29.
For very light loads, and also for higher input voltages, the
minimum time power switching cycle from the powertrain
will exceed the power required by the load. In this case the
external error amplifier will periodically drive PR below the
switching threshold in order to maintain regulation.
Switching will cease momentarily until the error amplifier
once again drives PR voltage above the threshold.
QTOT is the total input (Fig. 15) or output (Fig. 14) charge
per switching cycle at full load, while CINT is the module
internal effective capacitance at the considered voltage
(Fig. 20) and CEXT is the external effective capacitance at
the considered voltage.
10.5
Input filter stability
The PRM can provide very high dynamic transients. It is
therefore very important to verify that the voltage supply
source as well as the interconnecting line are stable and
do not oscillate. For this purpose, the converter dynamic
input impedance magnitude
rEQ _ IN
is provided in Figures
22, 23, 24. It is recommended to provide adequate design
margin with respect to the stability conditions illustrated in
10.5.1 and 10.5.2.
10.5.1 Inductive source and local, external input
decoupling capacitance with negligible ESR (i.e.: ceramic
type)
Figure 29 – light load burst mode of operation
Note that during the bursts of switching, the powertrain
frequency is constant, but the number of pulses as well as
the time between bursts is variable. The variability
depends on many factors including input voltage, output
voltages, load impedance, and external error amplifier
output impedance.
In burst mode, the gain of the PR input to the plant which
is modeled in the previous sections is time varying.
Therefore the small signal analysis can not be directly
applied to burst mode operation.
The voltage source impedance can be modeled as a
series RlineLline circuit. The high performance ceramic
decoupling capacitors will not significantly damp the
network because of their low ESR; therefore in order to
guarantee stability the following conditions must be
verified:
Rline >
(C
Lline
+C
IN INT
Rline RC
[8]
IN _ EXT
Lline
C IN _ EXT ⋅ RC
