PRM48BF480T400A00 (Formerly VIP0001TFJ)
PRM™ Regulator
FEATURES
45 V (38 to 55), non-isolated ZVS buck-boost regulator 5 to 55 V adjustable output range Building block for high efficiency DC-DC systems 400W output power in 1.1 in2 footprint 97% typical efficiency, at full load 1,360 W/in3 (83 W/cm3) Power Density Enables a 48 V to 1.5 V, 230 A isolated, regulated solution with total footprint of 3.3 in2 (21 cm2) Flexible “Remote Sense” architecture optimizes regulation / feedback loop design to fit application requirements Current feedback signal allows dynamic adjustment of current limit setpoint 3.61 MHrs MTBF (MIL-HDBK-217Plus Parts Count)
DESCRIPTION
The V•I Chip™ PRM™ Regulator is a high efficiency converter, operating from a 38 to 55 Vdc input to generate a regulated 5 to 55 Vdc output. The ZVS buck – boost topology enables high switching frequency (~1 MHz) operation with high conversion efficiency. High switching frequency reduces the size of reactive components enabling power density up to 1,360 W/in3. The full V•I Chip package is compatible with standard pickand-place and surface mount assembly processes with a planar thermal interface area and superior thermal conductivity. In a Factorized Power Architecture™ system, the PRM48BF480T400A00 and downstream VTM™ current multiplier minimize distribution and conversion losses in a high power solution. An external control loop and current sensor maintain regulation and enable flexibility both in the design of voltage and current compensation loops to control of output voltages and currents.
TYPICAL APPLICATIONS
High Efficiency Server Processor and Memory Power High Density ATE System DC-DC Power Telecom NPU and ASIC Core Power LED Drivers High Density Power Supply DC-DC Rail Outputs Non-isolated Power Converters
48 V to 1.5 V, 230A Voltage Regulator
Voltage Control Feedback
Enable/ Disable
PC +IN PR TM +OUT
Voltage Reference
PC +IN +OUT1 +OUT2
38 to 55 Vdc Input
-IN
PRMTM Regulator
IF RE -OUT SG VC
VTMTM Current Multiplier
-IN VC -OUT1 -OUT2
Load
Current Sense Constant Vc
PC +IN +OUT1 +OUT2
VTMTM Current Multiplier
-IN VC -OUT1 -OUT2
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1 12 / 2010 Page 1 of 22
PRM48BF480T400A00 (Formerly VIP0001TFJ)
1.0 ABSOLUTE MAXIMUM RATINGS The ABSOLUTE MAXIMUM ratings below are stress ratings only. Operation at or beyond these maximum ratings can cause permanent damage to device. Electrical specifications do not apply when operating beyond rated operating conditions. All voltages are specified relative to SG unless otherwise noted. Positive pin current represents current flowing out of the pin.
PR PC TM ……………………………………………………………………….. ……………………………………………………………………….. ……………………………………………………………………….. Min -0.3 -0.3 -0.3 -1 -0.5 Max 10.5 ±10 5.7 ±10 5.7 ±1 62 10.5 ±100 ±100 5.7 5 18 ±1.8 62 ±11 125 125 Unit V mA V mA V mA V V mA mA V V V A V A ºC ºC
+IN to –IN …………………………………………………………………………… VS ………………………………………………………………………..
SG …………………………………………………………………………… IF …………………………………………………………………………… RE …………………………………………………………………………… VC to –OUT +OUT to –OUT Output Current Operating Analog IC Junction Temperature Storage Temperature ……………………………………………………………………….. …………………………………………………………………………… …………………………………………………………………………… …………………………………………………………………………… ……………………………………………………………………………
-0.5 -0.3 -0.5 -1 -40 -40
2.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and output voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Attribute POWER INPUT SPECIFICATION Input Voltage Range VIN Slew Rate No Load Power Dissipation Input Quiescent Current Input Current Input Capacitance (Internal) Input Capacitance (Internal) ESR POWER OUTPUT SPECIFICATION Output Voltage Range Output Current Output Power Output Turn-ON Delay VOUT IOUT POUT TON 5 See Fig.16, SOA See Fig.16, SOA From VIN applied, PC floating From PC pin release, VIN applied, TOFF expired Equal input, output and PR voltage at full load; VIN = 45 V, VOUT = 48 V Equal input, output and PR voltage at full load; Over line and trim, with 25°C < TC < 100°C but negligible part-part temp mismatch Equal input, output and PR voltage at full load; Over line and trim, with 25°C < TC < 100°C and 50% load; over temperature Section 4.0 COUT_EXT = 0 F, IOUT = 8.33 A, VIN = 45 V, VOUT = 48 V, 20 MHz BW Frequency @ 1 MHz, Simulated J-Lead model Effective value, VOUT = 48 V (see Fig. 20) 48 55 8.33 400 V A W s ±10 ±24 ±35 96.5 94.8 90.0 97.4 % % % % % % mA mV nH F mΩ V V V V s V ºC s V V V V ms ms W VIN dVIN/dt PNL IQC IIN DC CIN INT RCin 0 < VIN < 18 V PC HIGH, VIN = 45 V PC LOW, VIN = 45 V IOUT = 8.33A, VIN = 38 V, VOUT = 48 V Effective value, VIN = 45 V (see Fig. 20) 38 0.001 45 2.4 4.5 10.9 4 1.5 55 1000 4 8.5 11.0 V V/ms W mA A F mΩ Symbol Conditions / Notes Min Typ Max Unit
20
Current Sharing Difference (exclusive of current limit)
IOUT_SHARE
Efficiency Output Discharge current Output Voltage Ripple Output Inductance (Parasitic) Output Capacitance (Internal) Output Capacitance (Internal) ESR POWERTRAIN PROTECTIONS Input Undervoltage Turn-ON Input Undervoltage Turn-OFF Input Overvoltage Turn-ON Input Overvoltage Turn-OFF Overcurrent (IF) and Input Over/Undervoltage Blanking Time Output Overvoltage Threshold Thermal Shutdown Setpoint Overtemperature, Output Overvoltage and PC Shutdown Response Time Short Circuit Vout Threshold
Short Circuit Vout Recovery Threshold
η
IOD VOUT PP LOUT PAR COUT INT RCout VIN UVLO+ VIN UVLOVIN OVLO+ VIN OVLOTBLNK VOUT OVLO+ TJ OTP TPROT VSC VOUT VSC VOUTR VSC VPR VSC VPRR TSC TSCR PPROT
13 960 1.9 4 1.5 35.75 33.56 57.24 58.44 120 56.57 2 3.0 4.0 7.2 7.1 20 0.1 400
1500
Instantanous powertrain shutdown, latched after TBLNK Instantanous powertrain shutdown, latched after TBLNK 31.97 55.91 50 Instantaneous, latched shutdown Instantaneous, latched shutdown; guaranteed by design, not production tested; VTM = 4.03V 55.25 130
37.13
59.91 150 59.04
Short Circuit Vpr Threshold Short Circuit Vpr Recovery Threshold Short Circuit Timeout Short Circuit Recovery Time Output Power Limit
Short circuit fault latched after VSC_VOUT and VSC_VPR thresholds persist for this time
V•I CHIP CORP. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200
Rev. 1.1 12 / 2010 Page 2 of 22
PRM48BF480T400A00 (Formerly VIP0001TFJ)
3.0 SIGNAL CHARACTERISTICS Specifications apply over all line and load conditions, TJ = 25 ºC and Output Voltage from 20V to 55V, unless otherwise noted. Boldface specifications apply over the temperature range of -40 ºC < TJ < 125 ºC (T-grade).
Primary Control PC • The PC pin enables and disables the PRM • In PRM array configurations, PC pins should be connected in order to synchronize startup. • It is a weak pull-down during any fault mode excluding short circuit. PC is a strong pull-down to SG if a short circuit fault is latched. Signal Type State Conditions / Notes Attribute Symbol VPC PC Voltage Regular Operation IPC_OP PC Available Current Analog Output After TOFF IPC_EN PC Source Current Startup TOFF Minimum Time to Start Section 5.0 VPC_EN Startup PC Enable Threshold VPC_DIS Digital Input / Output PC Disable Threshold Standby RPC_EXT Resistance to SG required to disable the PRM PC Resistance (External) IPC_SC Digital Output [Short Circuit Fault] Fault PC Sink Current to SG Short circuit, PC voltage 1 V or above IPC_FAULT Tempature, over- and undervoltage, overcurrent Digital Output [All other Faults] Fault PC Sink Current to ~1V
Min 4.7 1.8 10.0 1.75
Typ 5 90 18.0 2.50 2.40 25 10
Max 5.3
30.0 3.20 300
Unit V mA A ms V V Ω mA
Voltage Source VS • Intended to power feedback components and/or auxiliary circuits. • 9 V, 5mA regulated voltage source • With > 5% output load, VS ripple typically 100mV Signal Type State Attribute VS Voltage Regular VS Available Current Operation Analog Output VS Voltage Ripple Transition VS Capacitance (External) VS Fault Response Time
Symbol VVS IVS VVS_PP CVS_EXT TFR_VS
Conditions / Notes
Min 8.55 5
Typ 9.00 100 30
Max 9.45 400 0.04
Unit V mA mV F s
Iout = 0A, Cvs_ext=0. Maximum specification includes powertrain operation in burst mode. From fault recognition to VS = 1.5 V
Reference Enable RE • RE signals successful startup and a powertrain that is ready for operation • Regulated, delayed voltage source intended to power the feedback circuit voltage reference and current monitor Signal Type State Conditions / Notes Attribute Symbol VRE RE Voltage Regular IRE RE Available Current Operation %RE RE Regulation across load and temperature Analog Output Transition RE Voltage Ripple PC to RE Delay RE Capacitance (External) VS to RE Delay VRE_PP TPC_RE CRE_EXT TVS_RE in burst mode Fault detected VS = 8.1 V to RE high, VIN > VIN_UVLO-
Min 3.0 8.0
Typ 3.3 2.5 100 100
Max 3.6
Unit V mA % mV s F ms
0.1 1
Control Node PR • Modulator control node input • Sinks constant current when externally driven in active range • Sources current when pulled below active range Signal Type State Attribute PR Voltage Active Range PR Source Current Regular Analog Input Operation PR Sink Current PR Resistance to SG
Symbol VPR IPR IPR_Low RPR
Conditions / Notes VPR 0.79V VPR 0.79V
Min 0.79 250
Typ
Max 7.40 2 750
Unit V mA A kΩ
500 93.3
Current Feedback IF • A voltage proportional to the PRM output current must be supplied externally to the IF pin in order for the device to properly protect overcurrent events and to enable output current limit (clamp) • Overcurrent protection trip will cause instantaneous powertrain disable, latched after TBLNK Signal Type State Attribute Symbol Conditions / Notes Min Typ Max VIN = 45 V; TJ = 25 °C VIF_IL 1.90 2.00 2.10 Current Limit (clamp) Threshold Not Production Tested; Guaranted by Design; VIF_OC Regular Overcurrent Protection Threshold 2.58 2.69 2.80 TJ = 25 °C Analog Input Operation RIF 2.13 IF Input Impedance 2.11 2.15 BWIL 2 Current Limit Bandwidth
Unit V kΩ kHz
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Rev. 1.1 12 / 2010 Page 3 of 22
PRM48BF480T400A00 (Formerly VIP0001TFJ)
Temperature Monitor TM • The TM pin monitors the internal temperature of the PRM analog control IC. • "Power Good" flag to verify that the PRM is operating Signal Type State Attribute TM Voltage TM Voltage reference Regular Analog Output TM Voltage Ripple Operation TM Available Current TM Gain Digital Output [Fault Flag] Fault or Standby TM Disabled Current
Symbol VTM VTM_AMB VVS_PP ITM ATM ITM_DIS
Conditions / Notes Full temperature range TJ = 27 °C Powertrain in burst mode
Min 2.12 2.94 100
Typ 3.00 200 10
Max 4.04 3.06
Unit V V mV A
mV/°C
DC state with TM Voltage +/- 0.5V. This is a high impedance state.
0.0
mA
Signal Ground SG • All control signals must be referenced to this pin, with the exception of VC • SG is internally connected to -IN and -OUT Signal Type State Attribute Analog Input / Output Any Maximum Allowable Current
Symbol ISG
Conditions / Notes
Min -100
Typ
Max 100
Unit mA
VTM Control VC • Pulsed voltage source used to power and synchronize downstream VTM • If not used, must be resistively terminated to -OUT Signal Type State Attribute VC Voltage Analog Output Startup VC Available Current VC duration VC Slew Rate
Symbol VVC IVC TVC dVC/dt
Conditions / Notes RVC_EXT = 68 VC 20 V RVC = 1k
Min 13 200 7
Typ
Max
10 20
16
Unit V mA ms V/s
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
4.0 FUNCTIONAL BLOCK DIAGRAM
+Vin Vcc Vcc Internal Vcc Regulator 3.3V Linear Regulator 3.3V RE PC PR Vout Cin Q1 Q3 Cout +Vout
uC 8051
L
-Vin
16V
9V
+Vout Q2 Output Discharge (OD) Q4
-Vout
PR PR
93.3k
8.2V
Modulator
Var. Vclamp 2.5mA Min 0.5mA 14V 10ms Vcc 100uA
Q Q
SET
Enable VTM Vc Start up pulse
VC
S R
TOFF delay
Fault Logic
Instant latch Latch after 120us Vin (OV, UV)
RE 3.3V
RE
CLR
R 3V 5V 2mA max Vout (OV)
Vs 9V 0.01uF
PC 10uA PC
VPC_EN
Enable
Current Limit Overtemperature Protection VIF_IL Overcurrent Protection Vref (130°C) VIF_OC
SG
TM
Temperature dependent voltage source
IF
3 V @ 27°C
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
5.0 HIGH LEVEL FUNCTIONAL STATE DIAGRAM Conditions that cause state transitions are shown along arrows. Sub-sequence activities listed inside the state bubbles.
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
6.0 TIMING DIAGRAMS Module Inputs are shown in blue; Module Outputs are shown in brown; Timing diagrams assumes the following: Single PRM (no array) VS powers error amplifier RE powers voltage reference and output current transducer IOUT is sensed, scaled, and fed back to IF pin such that IF = 2.00 V at full load
1
Start up with 1.2V/ms < dVIN/dt < maximum
2
3
Quick OC Input OV (t 45º : for the closed loop response, the phase should be greater than 45º where the gain crosses 0dB. 2) Gain Margin > 10dB : The closed loop gain should be lower than -10dB where the phase crosses 0º. 3) Gain Slope = -20dB/decade : The closed loop gain should have a slope of -20dB/decade at the crossover frequency. The compensation characteristics must be selected to meet these stability criteria. Refer to Figure 27 for a local sense, voltage-mode control example based on the configuration in Figure 26. In this example, it is assumed that the maximum crossover frequency (FCMAX) has been selected to occur between B and C. Type-2 compensation (Curve IJKL) is sufficient in this case. The following data must be gathered in order to proceed: Modulator Gain GPR: See Figures 17, 18, 19 Powertrain equivalent resistance rEQ: See Figures 17, 18, 19
FP
1 2 π rEQ _ OUT RLOAD rEQ _ OUT RLOAD COUT _ INT COUT _ EXT
Compensation Mid-Band Gain:
G MB 20 log
R3 R1
[1]
Compensation Zero:
FZ1
1 2 π R 3 C1
[2]
Compensation Pole:
FP 2
1 R C C 2 π 3 1 2 C1 C2
and for FP2>>FZ1 (C1 + C2 ≈ C1):
FP 2
1 2 R3 C2
[3]
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
10.2.4 Midband Gain Design (R1,R3): With reference to Figure 27: curve ABC is the: minimum output voltage in the application maximum input voltage expected in the application maximum load PRM open loop response, and is where the maximum crossover frequency occurs. In order for the maximum crossover frequency to occur at the design choice FCMAX, the compensation gain must be equal and opposite of the powertrain gain at this frequency. For stability purposes, the compensation should be in the Mid-band (J-K) at the crossover. Using Equation [1], the mid-band gain can be selected appropriately. 10.2.5 Compensation Zero Design (C1): With reference to Figure 27: curve EFG is the: maximum output voltage in the application minimum input voltage expected in the application minimum load in the application PRM open loop response, and is where the minimum crossover frequency FCMIN occurs. Based on stability criteria, the compensation must be in the mid-band at the minimum crossover frequency, therefore FCMIN will occur where EFG is equal and opposite of GMB. C1 can be selected using Equation [2] so that FZ1 occurs prior to FCMIN.
PRM Regulator
TM
Figure 26 – Control circuit example
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
Open Loop Gain vs. Frequency
80
60
I
Application's op-amp G·BW Compensation Gain
40 Gain (dB)
F E PRM Open Loop Min Load A PRM Open Loop Max Load B J FCMIN FCMAX K L
20
0
-20 C -40 Frequency, Log scale (y-intercept is application specific) G
Figure 27 – Reference asymptotic Bode plot for the considered system
10.2.6
High Frequency Pole Design (C2):
based on the ratio of the “kick” to “droop” (as defined in Fig. 28).
Using Equation [3], C2 should be selected so that FP2 is at least one decade above FCMAX and prior to the gain bandwidth product of the operational amplifier (10MHz for this example). For applications with a higher desired crossover frequency the use of a high gain bandwidth product amplifier may be necessary to ensure that the real pole can be set at least one decade above the maximum crossover frequency. 10.2.7 Verifying Stability: The preferred method for verifying stability is to use a network analyzer, measuring the closed loop response across various lines and load conditions. In the absence of a network analyzer, a load step transient response can be used in order to estimate stability. Figure 28 illustrates an example of a load step response. Equation [4] can be used to predict the phase margin
Figure 28 – load step response example and “droop” vs. “kick” definition
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
k ln d m 100 2 k 2 ln d
10.3 Burst Mode Operation:
2
[4]
Figure 20 provides the effective internal capacitance of the module. A conservative estimate of input and output peakpeak voltage ripple at nominal line and trim is provided by equation [5]:
QTOT V CINT
I FL 0.4 f SW C EXT
[5]
At light loads, the PRM will operate in a burst mode due to minimum timing constraints. An example burst operation waveform is illustrated in Figure 29. For very light loads, and also for higher input voltages, the minimum time power switching cycle from the powertrain will exceed the power required by the load. In this case the external error amplifier will periodically drive PR below the switching threshold in order to maintain regulation. Switching will cease momentarily until the error amplifier once again drives PR voltage above the threshold.
QTOT is the total input (Fig. 15) or output (Fig. 14) charge per switching cycle at full load, while CINT is the module internal effective capacitance at the considered voltage (Fig. 20) and CEXT is the external effective capacitance at the considered voltage. 10.5 Input filter stability
The PRM can provide very high dynamic transients. It is therefore very important to verify that the voltage supply source as well as the interconnecting line are stable and do not oscillate. For this purpose, the converter dynamic input impedance magnitude rEQ _ IN is provided in Figures 22, 23, 24. It is recommended to provide adequate design margin with respect to the stability conditions illustrated in 10.5.1 and 10.5.2 . 10.5.1 Inductive source and local, external input decoupling capacitance with negligible ESR (i.e.: ceramic type) The voltage source impedance can be modeled as a series RlineLline circuit. The high performance ceramic decoupling capacitors will not significantly damp the network because of their low ESR; therefore in order to guarantee stability the following conditions must be verified:
Figure 29 – light load burst mode of operation
Note that during the bursts of switching, the powertrain frequency is constant, but the number of pulses as well as the time between bursts is variable. The variability depends on many factors including input voltage, output voltages, load impedance, and external error amplifier output impedance. In burst mode, the gain of the PR input to the plant which is modeled in the previous sections is time varying. Therefore the small signal analysis can not be directly applied to burst mode operation. 10.4 Input and Output filter design
Rline
(C IN _ INT
Lline C IN _ EXT ) rEQ _ IN
[6]
Rline rEQ _ IN
[7]
Figures 14 and 15 provide the total input and output charge per cycle, as well as switching frequency, of the PRM at full load under various input and output voltages conditions.
It is critical that the line source impedance be at least an octave lower than the converter’s dynamic input resistance, [7]. However, Rline cannot be made arbitrarily low otherwise equation [6] is violated and the system will show instability, due to under-damped RLC input network.
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
10.5.2 Inductive source and local, external input decoupling capacitance with significant RCIN_EXT ESR (i.e.: electrolytic type) In order to simplify the analysis in this case, the voltage source impedance can be modeled as a simple inductor Lline. Notice that, the high performance ceramic capacitors CIN_INT within the PRM should be included in the external electrolytic capacitance value for this purpose. The stability criteria will be current sharing accuracy specifications, but also temperature differences among PRMs, Vin variations, and error terms in the buffering of the error amplifier output to the PR pins. Control loop compensation procedures above will hold for an array, in general, although many parameters must be scaled against the number of PRMs in the system.
Please contact Vicor Applications for assistance. 10.7 Input Fuse Recommendations
rEQ _ IN RC IN _ EXT Lline rEQ _ IN C IN _ EXT RC IN _ EXT
[8]
[9]
Equation [9] shows that if the aggregate ESR is too small – for example by using very high quality input capacitors (CIN_EXT) – the system will be under-damped and may even become destabilized. Again, an octave of design margin in satisfying [8] should be considered the minimum. 10.6 Arrays
A fuse should be incorporated at the input to each PRM, in series with the +IN pin. A 15A or smaller input fuse (Littelfuse® NANO2® 451/453 Series, or equivalent) is required to safety agency conditions of acceptability. Always ascertain and observe the safety, regulatory, or other agency specifications that apply to your specific application. 10.8 Layout considerations
Application Note AN:005 details board layout using V•I Chip components. Additional consideration must be given to the external control circuit components. The current sense shunt signal voltage is highly sensitive to noise. As such, current sensing circuitry should be located close to the shunt to minimize the length of the sense signals. A Kelvined connection at the shunt is recommended for best results. The control signal from a remote voltage sense circuit to the PRM should be shielded. Avoid routing this, or other control signals directly underneath the PRM, if possible. Components that tie directly to the PRM should be located close to their respective pins. It is also critical that all control components be referenced to SG, and that SG not be tied to any other ground in the system, including –IN or –OUT of the PRM.
Up to ten PRMs of the same type may be placed in parallel to expand the power capacity of the system. The following high-level guidelines must be followed in order for the resultant system to start up and operate properly, and to avoid overstress or exceeding any absolute maximum ratings. –IN pins of all PRMs must be connected together. Both inductance and resistance from the common power source to each PRM should be minimized, and matched. Input voltage to all PRMs must be the same. Independent fuses for each PRM are recommended. PC pins must be connected together for synchronization and proper fault response. Reference supply to the control loop voltage reference and current sense circuitry must be enabled when all modules’ RE pins have reached their operational voltage levels. There must be one single external voltage control loop. The control loop must drive each PR pin relative to each modules’ SG pin, and the local PR voltage must be the same across all modules. Each PRM must have its own local current shunt and current sense circuitry to drive it’s IF pin. The number of PRMs required to achieve a given array capacity must consider all sources of mismatch to avoid overstress of any PRM in the array. Imbalances in sharing are not only due to
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PRM48BF480T400A00 (Formerly VIP0001TFJ)
Warranty
Vicor products are guaranteed for two years from date of shipment against defects in material or workmanship when in normal use and service. This warranty does not extend to products subjected to misuse, accident, or improper application or maintenance. Vicor shall not be liable for collateral or consequential damage. This warranty is extended to the original purchaser only. EXCEPT FOR THE FOREGOING EXPRESS WARRANTY, VICOR MAKES NO WARRANTY, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Vicor will repair or replace defective products in accordance with its own best judgment. For service under this warranty, the buyer must contact Vicor to obtain a Return Material Authorization (RMA) number and shipping instructions. Products returned without prior authorization will be returned to the buyer. The buyer will pay all charges incurred in returning the product to the factory. Vicor will pay all reshipment charges if the product was defective within the terms of this warranty. Information published by Vicor has been carefully checked and is believed to be accurate; however, no responsibility is assumed for inaccuracies. Vicor reserves the right to make changes to any products without further notice to improve reliability, function, or design. Vicor does not assume any liability arising out of the application or use of any product or circuit; neither does it convey any license under its patent rights nor the rights of others. Vicor general policy does not recommend the use of its components in life support applications wherein a failure or malfunction may directly threaten life or injury. Per Vicor Terms and Conditions of Sale, the user of Vicor components in life support applications assumes all risks of such use and indemnifies Vicor against all damages.
Vicor’s comprehensive line of power solutions includes high density AC-DC and DC-DC modules and accessory components, fully configurable AC-DC and DC-DC power supplies, and complete custom power systems.
Information furnished by Vicor is believed to be accurate and reliable. However, no responsibility is assumed by Vicor for its use. Vicor components are not designed to be used in applications, such as life support systems, wherein a failure or malfunction could result in injury or death. All sales are subject to Vicor’s Terms and Conditions of Sale, which are available upon request.
Specifications are subject to change without notice. Intellectual Property Notice
Vicor and its subsidiaries own Intellectual Property (including issued U.S. and Foreign Patents and pending patent applications) relating to the products described in this data sheet. Interested parties should contact Vicor's Intellectual Property Department. The products described on this data sheet are protected by the following U.S. Patents Numbers: 5,945,130; 6,403,009; 6,710,257; 6,911,848; 6,930,893; 6,934,166; 6,940,013; 6,969,909; 7,038,917; 7,145,186; 7,166,898; 7,187,263; 7,202,646; 7,361,844; D496,906; D505,114; D506,438; D509,472; and for use under 6,975,098 and 6,984,965. Vicor Corporation 25 Frontage Road Andover, MA, USA 01810 Tel: 800-735-6200 Fax: 978-475-6715 email Customer Service: custserv@vicorpower.com Technical Support: apps@vicorpower.com
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