VIB0010TFJ

VIB0010TFJ PRELIMINARY DATASHEET S C NRTL US BCM DC to DC Bus Converter Module TM FEATURES • 352 Vdc – 12.5 Vdc 300 W Bus Converter Module • High efficiency (>95%) reduces system power consumption • High power density (>1000 W/in3) reduces power system footprint by >40% • “Full Chip” V•I Chip package enables surface mount, low impedance interconnect to system board • Contains built-in protection features: undervoltage, overvoltage lockout, overcurrent protection, short circuit protection, overtemperature protection. DESCRIPTION The V•I Chip Bus Converter Module is a high efficiency (>95%) Sine Amplitude Converter (SAC)TM operating from a 330 to 365 Vdc primary bus to deliver an isolated 11.79 – 13.04 V nominal, unregulated secondary. The SAC offers a low AC impedance beyond the bandwidth of most downstream regulators, meaning that input capacitance normally located at the input of a regulator can be located at the input to the SAC. Since the K factor of the VIB0010TFJ is 1/28, that capacitance value can be reduced by a factor of 784x, resulting in savings of board area, materials and total system cost. The VIB0010TFJ is provided in a V•I Chip package compatible with standard pick-and-place and surface mount assembly processes. The V•I Chip package provides flexible thermal management through its low junction-to-case and junction-toboard thermal resistance. With high conversion efficiency the VIB0010TFJ increases overall system efficiency and lowers operating costs compared to conventional approaches. • Provides enable/disable control, internal temperature monitoring • ZVS/ZCS Resonant Sine Amplitude Converter topology • Can be paralleled to create multi-kW arrays TYPICAL APPLICATIONS VIN = 330 – 365 V VOUT = 11.79 – 13.04 V (NO LOAD) POUT = 300 W(NOM) K = 1/28 • High End Computing Systems • Automated Test Equipment • High Density Power Supplies • • TYPICAL APPLICATION enable / disable switch SW1 F1 PC TM POL BCM +In +Out VOUT -In -Out C1 1 µF POL POL POL (8) VIN V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 1 of 16 VIB0010TFJ PRELIMINARY DATASHEET ABSOLUTE MAXIMUM RATINGS +IN to –IN . . . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc – +400 Vdc PC to –IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +20 Vdc TM to –IN . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 Vdc – +7 Vdc +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 4242 V (Hi Pot) +IN/-IN to +OUT/-OUT . . . . . . . . . . . . . . . . . . . 500 V (working) +OUT to –OUT . . . . . . . . . . . . . . . . . . . . . . -1.0 Vdc - +16 Vdc Temperature during reflow . . . . . . . . . . . . . . . . . 225°C (MSL5) PACKAGE ORDERING INFORMATION CONTROL PIN SPECIFICATIONS See section 5.0 for further application details and guidelines. PC (V•I Chip BCM Primary Control) The PC pin can enable and disable the BCM. When held below VPC_DIS the BCM shall be disabled. When allowed to float with an impedance to –IN of greater than 50 kΩ the module will start. When connected to another BCM PC pin, the BCMs will start simultaneously when enabled. The PC pin is capable of being driven high by an either external logic signal or internal pull up to 5 V (operating). TM (V•I Chip BCM Temperature Monitor) The TM pin monitors the internal temperature of the BCM within an accuracy of +5/-5°C. It has a room temperature setpoint of ~3.0 V and an approximate gain of 10 mV/°C. It can source up to 100 µA and may also be used as a “Power Good” flag to verify that the BCM is operating. 4 A 3 2 1 A B C D E +Out B C D E +In -Out F G H H J J K K TM RSV PC +Out L M N P L M N P R T -In -Out R T Bottom View Signal Name +In –In TM RSV PC +Out –Out Designation A1-E1, A2-E2 L1-T1, L2-T2 H1, H2 J1, J2 K1, K2 A3-D3, A4-D4, J3-M3, J4-M4 E3-H3, E4-H4, N3-T3, N4-T4 PART NUMBER VIB0010TFJ DESCRIPTION -40°C – 125°C TJ, J lead V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 2 of 16 VIB0010TFJ PRELIMINARY DATASHEET 1.0 ELECTRICAL CHARACTERISTICS Specifications apply over all line and load conditions unless otherwise noted; Boldface specifications apply over the temperature range of -40°C < TJ < 125°C (T-Grade); All other specifications are at TJ = 25ºC unless otherwise noted ATTRIBUTE Voltage range dV/dt Quiescent power No load power dissipation Inrush Current Peak DC Input Current K Factor SYMBOL VIN dVIN /dt PQ PNL IINR_P IIN_DC K POUT POUT_P VOUT IOUT η η η ROUT ROUT ROUT COUT FSW FSW_RP VOUT_PP TON1 VIN = 352 VDC; See Figure 14 VIN = 330 – 365 VDC; See Figure 14 VIN = 352 VDC Average POUT < = 300 W, Tpeak < 10 ms Section 3.0 No load Pout < = 300 W VIN = 352 V, POUT = 300 W VIN = 330 V to 365 V, POUT = 300 W VIN = 352 V, TJ = 100° C,POUT = 300 W 60 W < POUT < 300 W Max TJ = 25° C TJ = 125° C TJ = -40° C CONDITIONS / NOTES MIN 330 PC connected to -IN VIN = 352 V VIN = 330 to 365 V VIN = 365 V COUT = 1000 µF, POUT = 300 W POUT = 300 W TYP 352 230 7.1 2 MAX 365 1 370 10 15 4.5 1 1/28 300 282 450 11.79 94.2 94 93.3 90 10 14 7 2.13 4.26 COUT = 0 µF, POUT = 300 W, VIN = 352 V, Section 8.0 VIN = 352 V, CPC = 0; See Figure 16 12.5 16.5 10 2.25 4.5 200 460 390 18 25 14 1000 2.37 4.74 400 620 95.3 94.6 13.04 26 W W V A % % % mΩ mΩ mΩ uF MHz MHz mV ms UNIT Vdc V/µs mW W A A () VOUT VIN Output Power (Average) Output Power (Peak) Output Voltage Output Current (Average) Efficiency (Ambient) Efficiency (Hot) Minimum Efficiency (Over Load Range) Output Resistance (Ambient) Output Resistance (Hot) Output Resistance (Cold) Load Capacitance Switching Frequency Ripple Frequency Output Voltage Ripple VIN to VOUT (Application of VIN) PC PC Voltage (Operating) PC Voltage (Enable) PC Voltage (Disable) PC Source Current (Startup) PC Source Current (Operating) PC Internal Resistance PC Capacitance (Internal) PC Capacitance (External) External PC Resistance PC External Toggle Rate PC to VOUT with PC Released PC to VOUT, Disable PC VPC VPC_EN VPC_DIS IPC_EN IPC_OP RPC_SNK CPC_INT CPC_EXT RPC FPC_TOG Ton2 TPC_DIS 4.7 2 50 2 50 5 2.5 100 3.5 150 Internal pull down resistor Section 5.0 External capacitance delays PC enable time Connected to –VIN VIN = 352 V, Pre-applied CPC = 0, COUT = 0; See Figure 16 VIN = 352 V, Pre-applied CPC = 0, COUT = 0; See Figure 16 5.3 3 10 A/us; See Figure 11 IOUT_STEP = 25 A to 0 A, ISLEW > 10 A/us; See Figure 12 TYP 7.1 2 95.3 94.6 10 12.5 16.5 200 380 380 60 4.62 47 3 UNIT W A % % mΩ mΩ mΩ mV mV mV µs ms µs V V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 5 of 16 VIB0010TFJ No Load Power Dissipation 12 96.0 95.5 PRELIMINARY DATASHEET Full Load Efficiency vs. Temperature Power Dissipation (W) 10 8 6 4 2 0 330 335 340 345 350 355 360 365 Efficiency (%) 95.0 94.5 94.0 93.5 93.0 -40 -20 0 330 20 352 40 365 60 80 100 Input Voltage (V) -40 25 100 Case Temperature (°C) Figure 1 – No load power dissipation vs. VIN; TCASE Figure 2 – Full load efficiency vs. temperature; VIN Efficiency & Power Dissipation -40°C Case 98 94 90 21 98 Efficiency & Power Dissipation 25°C Case 19 Power Dissipation (W) 94 Efficiency (%) Efficiency (%) 86 82 78 74 70 66 62 0 330 5 352 10 15 365 20 330 25 352 30 17 15 92 90 88 86 84 82 80 78 0 5 330 η PD 15 13 11 9 7 5 10 352 15 365 20 330 25 352 30 PD 13 11 9 7 Output Load (A) 365 Output Load (A) 365 Figure 3 – Efficiency and power dissipation at -40°C (case); VIN Figure 4 – Efficiency and power dissipation at 25°C (case); VIN Efficiency & Power Dissipation 100°C Case 98 96 94 21 18 Rout vs. Case Temperature Power Dissipation (W) 17 16 15 14 13 12 11 10 9 8 -40 365 -20 0 20 2.6 A 40 26 A 60 80 100 Efficiency (%) 90 88 86 84 82 80 78 0 330 5 352 10 15 365 20 330 25 352 30 15 13 PD 11 9 7 5 Rout (mΩ) 92 η 19 17 Output Load (A) Temperature (°C) Figure 5 – Efficiency and power dissipation at 100°C (case); VIN Figure 6 – ROUT vs. temperature vs. IOUT V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 6 of 16 Power Dissipation (W) η 19 96 17 VIB0010TFJ PRELIMINARY DATASHEET Output Voltage Ripple at 25°C vs. Iout 250 200 Vripple (mV) 150 100 50 0 0 5 10 15 20 25 30 Iout(A) Peak To Peak Figure 7 – Vripple vs. IOUT ; 352 Vin, no external capacitance Figure 8 – PC to VOUT startup waveform Figure 9 – VIN to VOUT startup waveform Figure 10 – Output voltage and input current ripple, 352 Vin, 300 W no COUT Figure 11 – Positive load transient (0 – 25 A) Figure 12 – Negative load transient (25 A – 0 A) V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 7 of 16 VIB0010TFJ PRELIMINARY DATASHEET Safe Operating Area 500 450 400 350 300 250 200 150 100 50 0 11.40 11.90 12.40 12.90 Output Power (W) Output Voltage (V) Steady State 450 W 10 mS Figure 13 – PC disable waveform, 352 VIN, 1000 µF COUT full load Figure 14 – Safe Operating Area vs. VOUT 2.0 PACKAGE/MECHANICAL SPECIFICATIONS All specifications are at TJ = 25ºC unless otherwise noted. See associated figures for general trend data. ATTRIBUTE Length Width Height Volume Footprint Power Density Weight Lead Finish Operating Temperature Storage Temperature Thermal Capacity Peak Compressive Force Applied to Case (Z-axis) Moisture Sensitivity Level ESD Rating Peak Temperature During Reflow Peak Time Above 183°C Peak Heating Rate During Reflow Peak Cooling Rate Post Reflow Thermal Impedance [a] [b] SYMBOL L W H Vol F PD W CONDITIONS / NOTES MIN 32.4 / 1.27 21.7 / 0.85 6.48 / 0.255 TYP 32.5 / 1.28 22.0 / 0.87 6.73 / 0.265 4.81 / 0.295 7.3 / 1.1 1017 62 0.5/14 MAX 32.6 / 1.29 22.3 / 0.89 6.98 / 0.275 UNIT mm/in mm/in mm/in cm3/in3 cm2/in2 W/in3 W/cm3 oz/g µm No Heatsink No Heatsink No Heatsink Nickel (0.51-2.03 µm) Palladium (0.02-0.15 µm) Gold (0.003-0.05 µm) TJ TST No J-lead support ESDHBM ESDMM MSL Level 5 Human Body Model[a] Machine Model[b] -40 -40 9 5 5 1500 400 125 125 6 °C °C Ws/°C lbs VDC 225 150 3 6 1.5 °C s °C/s °C/s °CW ØJC Min Board Heatsinking 1.5 1.5 1.1 JEDEC JESD 22-A114C.01 JEDED JESD 22-A115-A V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 8 of 16 VIB0010TFJ 2.1 MECHANICAL DRAWING PRELIMINARY DATASHEET BOTTOM VIEW TOP VIEW ( COMPONENT SIDE ) NOTES: mm 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com 2.2 RECOMMENDED LAND PATTERN RECOMMENDED LAND PATTERN ( COMPONENT SIDE SH OWN ) NOTES: mm 1. DIMENSIONS ARE inch . 2. UNLESS OTHERWISE SPECIFIED, TOLERANCES ARE: .X / [.XX] = +/-0.25 / [.01]; .XX / [.XXX] = +/-0.13 / [.005] 3. PRODUCT MARKING ON TOP SURFACE DXF and PDF files are available on vicorpower.com V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 9 of 16 VIB0010TFJ PRELIMINARY DATASHEET 3.0 POWER, VOLTAGE, EFFICIENCY RELATIONSHIPS Because of the high frequency, fully resonant SAC topology, power dissipation and overall conversion efficiency of BCM converters can be estimated as shown below. Key relationships to be considered are the following: 1. Transfer Function a. No load condition VOUT = VIN • K Eq. 1 Figure 15 – Power transfer diagram P R OUT P NL INPUT POWER OUTPUT POWER Where K (transformer turns ratio) is constant for each part number b. Loaded condition VOUT = Vin • K – IOUT • ROUT Eq. 2 2. Dissipated Power The two main terms of power losses in the BCM module are: - No load power dissipation (PNL) defined as the power used to power up the module with an enabled power train at no load. - Resistive loss (ROUT) refers to the power loss across the BCM modeled as pure resistive impedance. ~ PDISSIPATED ~ PNL + PROUT Eq. 3 Therefore, with reference to the diagram shown in Figure 15 POUT = PIN – PDISSIPATED = PIN – PNL – PROUT Eq. 4 Notice that ROUT is temperature and input voltage dependent and PNL is temperature dependent (See Figure 15). The above relations can be combined to calculate the overall module efficiency: η= POUT PIN = PIN – PNL – PROUT PIN = VIN • IIN – PNL – (IOUT)2 • ROUT VIN • IIN =1– ( PNL + (IOUT)2 • ROUT VIN • IIN ) Eq. 5 V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 10 of 16 4.0 OPERATING VOVLO+ VOVLO– 1 2 3 5 4 6 Figure 16 – Timing diagram v i c o r p o w e r. c o m C B VIN NL VUVLO+ VUVLO– PC 5V 3V 3V 5V 2.5 V C 500mS before retrial Vout G D A E F LL • K IOUT ISSP IOCP H VIB0010TFJ TM 3 V @ 27°C V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 0.4 V Notes: A: TON1 B: TOVLO* C: Max recovery time D:TUVLO E: TON2 F: TOCP G: TPC–DIS H: TSSP** 1: Controller start 2: Controller turn off 3: PC release 4: PC pulled low 5: PC released on output SC 6: SC removed – Timing and voltage is not to scale – Error pulse width is load dependent *Min value switching off **From detection of error to power train shutdown PRELIMINARY DATASHEET Page 11 of 16 Rev. 1.1 9/2009 VIB0010TFJ 5.0 USING THE CONTROL SIGNALS TM AND PC The PC control pin can be used to accomplish the following functions: • Delayed start: At start-up, PC pin will source a constant 100 uA current to the internal RC network. Adding an external capacitor will allow further delay in reaching the 2.5 V threshold for module start. • Synchronized start up: In a parallel module array, PC pins shall be connected in order to ensure synchronous start of all the units. While every controller has a calibrated 2.5 V reference on PC comparator, many factors might cause different timing in turning on the 100 uA current source on each module, i.e.: – Different VIN slew rate – Statistical component value distribution By connecting all PC pins, the charging transient will be shared and all the modules will be enabled synchronously. • Auxiliary voltage source: Once enabled in regular operational conditions (no fault), each BCM PC provides a regulated 5 V, 2 mA voltage source. • Output Disable: PC pin can be actively pulled down in order to disable module operations. Pull down impedance shall be lower than 400 Ω and toggle rate lower than 1 Hz. • Fault detection flag: The PC 5 V voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and PC voltage is re-enabled. For system monitoring purposes (microcontroller interface) faults are detected on falling edges of PC signal. It is important to notice that PC doesn’t have current sink capability (only 150 kΩ typical pull down is present), therefore, in an array, PC line will not be capable of disabling all the modules if a fault occurs on one of them. The temperature monitor (TM) pin provides a voltage proportional to the absolute temperature of the converter control IC. It can be used to accomplish the following functions: • Monitor the control IC temperature: The temperature in Kelvin is equal to the voltage on the TM pin scaled by x100. (i.e. 3.0 V = 300 K = 27ºC). It is important to remember that V•I chips are multi-chip modules, whose temperature distribution greatly vary for each part number as well with input/output conditions, thermal management and environmental conditions. Therefore, TM cannot be used to thermally protect the system. • Fault detection flag: The TM voltage source is internally turned off as soon as a fault is detected. After a minimum disable time, the module tries to re-start, and TM voltage is re-enabled. PRELIMINARY DATASHEET 6.0 FUSE SELECTION V•I Chips are not internally fused in order to provide flexibility in configuring power systems. Input line fusing of V•I Chips is recommended at system level, in order to provide thermal protection in case of catastrophic failure. The fuse shall be selected by closely matching system requirements with the following characteristics: • Current rating (usually greater than maximum BCM current) • Maximum voltage rating (usually greater than the maximum possible input voltage) • Ambient temperature • Nominal melting I2t • Recommended fuse: ≤2.5 A Bussmann PC-Tron or SOC type 36CFA. V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 12 of 16 VIB0010TFJ 7.0 CURRENT SHARING The SAC topology bases its performance on efficient transfer of energy through a transformer, without the need of closed loop control. For this reason, the transfer characteristic can be approximated by an ideal transformer with some resistive drop and positive temperature coefficient. This type of characteristic is close to the impedance characteristic of a DC power distribution system, both in behavior (AC dynamic) and absolute value (DC dynamic). When connected in an array (with same K factor), the BCM module will inherently share the load current with parallel units, according to the equivalent impedance divider that the system implements from the power source to the point of load. PRELIMINARY DATASHEET It is important to notice that, when successfully started, BCMs are capable of bidirectional operations (reverse power transfer is enabled if the BCM input falls within its operating range and the BCM is otherwise enabled). In parallel arrays, because of the resistive behavior, circulating currents are never experienced (energy conservation law). General recommendations to achieve matched array impedances are (see also AN016 for further details): • to dedicate common copper planes within the PCB to deliver and return the current to the modules • to make the PCB layout as symmetric as possible • to apply same input/output filters (if present) to each unit Figure 17 – BCM Array V•I CHIP INC. (A VICOR COMPANY) 25 FRONTAGE RD. ANDOVER, MA 01810 800-735-6200 v i c o r p o w e r. c o m Rev. 1.1 9/2009 Page 13 of 16 VIB0010TFJ 8.0 INPUT AND OUTPUT FILTER DESIGN A major advantage of SAC systems versus conventional PWM converters is that the transformers do not require large functional filters. The resonant LC tank, operated at extreme high frequency, is amplitude modulated as a function of input voltage and output current, and efficiently transfers charge through the isolation transformer. A small amount of capacitance, embedded in the input and output stages of the module, is sufficient for full functionality and is key to achieve power density. This paradigm shift requires system design to carefully evaluate external filters in order to: 1. Guarantee low source impedance: To take full advantage of the BCM dynamic response, the impedance presented to its input terminals must be low from DC to approximately 5 MHz. The connection of the V•I Chip to its power source should be implemented with minimal distribution inductance. If the interconnect inductance exceeds 100 nH, the input should be bypassed with a RC damper to retain low source impedance and stable operation. With an interconnect inductance of 200 nH, the RC damper may be as high as 1 µF in series with 0.3 Ω. A single electrolytic or equivalent low-Q capacitor may be used in place of the series RC bypass. 2. Further reduce input and/or output voltage ripple without sacrificing dynamic response: Given the wide bandwidth of the BCM, the source response is generally the limiting factor in the overall system response. Anomalies in the response of the source will appear at the output of the BCM multiplied by its K factor. This is illustrated in Figures 11 and 12. 3. Protect the module from overvoltage transients imposed by the system that would exceed maximum ratings and cause failures: The V•I Chip input/output voltage ranges shall not be exceeded. An internal overvoltage lockout function prevents operation outside of the normal operating input range. Even during this condition, the powertrain is exposed to the applied voltage and power MOSFETs must withstand it. A criterion for protection is the maximum amount of energy that the input or output switches can tolerate if avalanched. PRELIMINARY DATASHEET Total load capacitance at the output of the BCM shall not exceed the specified maximum. Owing to the wide bandwidth and low output impedance of the BCM, low frequency bypass capacitance and significant energy storage may be more densely and efficiently provided by adding capacitance at the input of the BCM. At frequencies