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SPICE Device Model Si9926BDY Vishay Siliconix Dual N-Channel 2.5-V (G-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72413 01-Jun-04 www.vishay.com 1 SPICE Device Model Si9926BDY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 0.96 394 0.015 0.022 26 0.80 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 8.2 A VGS = 2.5 V, ID = 3.3 A VDS = 15 V, ID = 8.2 A IS = 1.7 A, VGS = 0 V V A 0.016 0.024 29 0.80 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Forward Voltagea Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = 10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω VDS = 10 V, VGS = 4.5 V, ID = 8.2 A 10 2.5 3.2 50 32 24 14 11 2.5 3.2 35 50 31 15 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72413 01-Jun-04 SPICE Device Model Si9926BDY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72413 01-Jun-04 www.vishay.com 3