AN207

AN207 Vishay Siliconix 12-ns DG611 Switch Family Combines Benefits of CMOS and DMOS Technologies The DG611, DG612, and DG613 are extremely low-power, high-speed analog switches designed to optimize circuit performance in high-speed switching applications. Each of these devices integrates low-power CMOS drivers with high-speed DMOS FETs. The resulting switches boast some remarkable features: high speed, low power, low on-resistance, low leakage, low charge injection and low channel capacitance, all on the same device. Circuit Description Each device has four independently controlled switches. The DG611 and DG612 respond to opposite control logic. The DG611 has a normally closed (NC) function while the DG612 is a normally open (NO) device. The DG613 offers a complementary function. It contains two NO and two NC switches. This versatile device can be configured as two single-pole single-throw (SPDT), one double-pole double-throw (DPDT), a “T” switch, two “L” switches, and so forth. As illustrated in Figure 2, each analog switch channel consists of an input stage, followed by a level translator, a driver stage, and an n-channel MOSFET. The input stage is a CMOS inverter powered from VL. VL is the logic power supply voltage (normally +5 V). As with any classic CMOS inverter, control input pin impedance is very high and essentially equivalent to the logic input pin capacitance (approximately 5 pF). This pin does not draw current (except for leakage) when in a steady state. To change states it is necessary to charge or discharge this input capacitance, which requires a short current pulse from the control logic gate. By combining both CMOS and DMOS technologies on a single chip, the DG61X family avoids the tradeoffs inherent in other high-speed analog switches, such as high power consumption, high on-resistance, and high channel capacitance. The DG61X family is likewise superior to DMOS FETs, which are fast but highly sensitive to electrostatic discharge, as well as requiring external drivers built with a number of external discrete components. This application note describes the new DG61X devices in detail and provides a series of application hints which will help you take full advantage of this fast new family in your designs. S1, 4 D1, 4 IN1, 4 S1-4 D1-4 S1-4 D1-4 S2, 3 D2, 3 IN1-4 IN1-4 IN2, 3 DG611 Normally Closed DG612 Normally Open DG613 Complementary All Switches Shown for Logic “0” Inputs. FIGURE 1. Functional Diagrams (Typical Switch) Document Number: 70605 03-Aug-99 www.vishay.com S FaxBack 408-970-5600 6-1 AN207 Vishay Siliconix VL V+ S V– D IN DMOS Switch Driver V– Input Logic Level Translator FIGURE 2. Typical Channel Block Diagram The level translator provides level shifting of the 0 to 5 V logic input to the V+ to V– voltage excursions needed to control the MOSFET switch. The driver stage acts as a buffer and provides current amplification to quickly charge/discharge the MOSFET gate, thus quickly turning the switch ON or OFF. The switching element is an n-channel double-diffused enhancement-mode MOSFET. DMOS FETs achieve very low inter-electrode capacitance and high speed, thanks to their lateral construction. To turn the switch ON, a voltage equal to V+ is applied to the FET’s gate. This enhances the channel into conduction. The source and Drain terminals can stand up to 16 V with respect to the substrate voltage (V–). ESD protection diode pairs are connected from each logic input, source, and drain pin to the V+ and V- power supply rails. becomes a challenge. ATE limitations (lead inductances/capacitances, generator’s rise and fall times) conspire to slow things down. This is why the tON/tOFF specifications on the data sheet are so loose (35 ns max). A typical device in a typical application is much faster than the data-sheet specifications would indicate. A bench test circuit reduced test fixture parasitics, while a low capacitance (3 pF) FET probe was used to monitor the output voltage. Figure 3 shows that before the output starts to change there was a propagation delay through the driver of about 8 ns. Once the FET starts to turn on, the output voltage rises very fast. The rise time was approximately 2 ns. Total tON (50% Vin to 90% Vout) was approximately 12 ns. Similarly at turn-off the driver’s propagation delay appeared to be about 8 ns, the fall time was about 5 ns. tOFF (50% VIN to 90% VOUT) was about 7 ns. Reduced Switching Transients By adding two dynamic compensation capacitors to the output driver stage, charge injection glitches have been virtually eliminated. For comparison purposes, Figure 4 illustrates the typical charge injection characteristics for two Vishay Siliconix’ high-speed analog switches: DG271 and DG611. Note how flat the DG611 characteristic is. This guarantees low charge injection regardless of analog signal voltage. Charge injection causes switching glitches both at turn-on and at turn-off times. To evaluate and compare the switching glitches produced by the DG611, the test circuit of Figure 5 was built. A 4-Vp-p triangular bipolar wave form was fed to the switch input. On this wave form we wanted to cut some 0-V notches as commanded by a pulse train. 100-ns pulses were used to interrupt signal flow twice in every period letting the output voltage to fall to 0 V. Document Number: 70605 03-Aug-99 Optimized Characteristics The DG611 family was designed to optimize the parameters which are most important in high-speed applications. Switching Speed Discrete DMOS FETs such as the SD210 or SD5000 are well known for their fast switching speeds. In fact, both specify a td(on) of 1 ns max. The DG611 family combines fast DMOS switching elements with a low-power CMOS driver. These devices are so fast that measuring their speed at final test www.vishay.com S FaxBack 408-970-5600 6-2 AN207 Vishay Siliconix S +2 V D VOUT VIN 300 W CL = 3 pF 50 W Test Circuit VIN VOUT FIGURE 3. Bench Test Switching Times Are Faster Than Data Sheet Limits As seen in Figure 6, there were significant differences between the DG271 and the DG611 output wave forms. First, the DG611 considerably reduced switching glitches. Some spikes went from 1 V to 0.2 V, a fivefold improvement. Second, the faster DG611 reduced output delays and produced more consistent notch widths. On-Resistance A low on-resistance switch reduces measurement errors and helps to achieve fast settling times in test equipment and data acquisition systems. It is also useful in reducing insertion loss when switching RF or video signals. The DG611 family specifies a typical rDS(on) of 18 Ω . This is one of the lowest values among high-speed analog switches. In order to reduce parasitic capacitances, the DG611 uses an n-channel enhancement mode MOSFET for the switch element. Consequently, its on-resistance increases as the channel voltage increases. Eventually, as VS approaches V+ the n-channel MOSFET loses its enhancement voltage (V+) -VS and turns off. For general purpose switches, it is customary to assume that all charge injection is due to capacitive coupling from the output driver into the analog channel. At the low Qinj levels achieved by the DG61X family, even the spurious capacitance (due to pin proximity from the logic control pin to the adjacent drain pin) will contribute a significant amount of charge. For this reason, it is possible to get minimal glitches by applying the input signal to the drain pin and using the source pin for the output. Document Number: 70605 03-Aug-99 www.vishay.com S FaxBack 408-970-5600 6-3 AN207 Vishay Siliconix 80 60 40 a) DG271 20 0 –20 –40 –60 –15 –10 –5 0 5 10 15 CL = 1000 pF 50 W b) DG611 50 W a) V+ = 15 V, V– = –15 V b) V+ = 15 V, V– = –3 V VS DG271 or DG611 VOUT Charge Injection (pC) 1 kW Ideal (0 pC) VIN VS – Source Voltage (V) FIGURE 4. The DG611 Charge Injection Characteristic Shows a Dramatic Improvement Over That of the DG271 FIGURE 5. Switching Spikes Evaluation Circuit VS VIN VOUT a) Using DG271 a) Using DG611 FIGURE 6. The DG611 Significantly Improves the Output Wave Form www.vishay.com S FaxBack 408-970-5600 6-4 Document Number: 70605 03-Aug-99 AN207 Vishay Siliconix 600 +5 V 500 a) 400 r DS(on) ( W ) GND V– 300 IN D S 200 a) V+ = 5 V b) V+ = 12 V c) V+ = 12 V, ISD = 10 mA b) c) VL V+ ISD V+ V+ VS 100 V– V– 0 0 2 4 6 8 10 12 14 16 18 20 VS – Source Voltage (V) FIGURE 7. Typical rDS(on) Characteristics FIGURE 8. ESD Protection Diodes are Located at all Control and Switch Pins Figure 7 illustrates typical on-resistance curves. Curve (a) represents single 5-V operation. Assuming a maximum acceptable rDS(on) value of 200 Ω , the usable analog signal range goes from 0 V to slightly over 2 V. Curve (b) shows operation with V+ = 12 V. Now the usable signal range has increased to 8 V. If you want to operate in the flat, low-resistance part of the curve, you may want to limit your analog signal to no more than 6 V. Curve (c) was generated using a –10-mA ID current. Note that when VS = 12 V, it still shows an rDS(on) = 480 Ω . To sink 10 mA, VD has gone down to 7.2 V, and this creates a partial channel enhancement. High-Speed 8-Channel Analog Multiplexer If you are designing a high-speed data acquisition system, then you will need a very fast analog multiplexer. A fast multiplexer like the DG408 specifies a typical transition time of 160 ns. By using the DG611 to make the multiplexer shown in Figure 9, you will achieve transition times in the 30-ns range, a sixfold speed improvement. This added speed will allow you to achieve sampling rates in excess of 3 MHz, as demonstrated below. ESDS (ESD Sensitivity) By incorporating a CMOS driver in front of the DMOS FET, direct access to the DMOS gate has been eliminated. By itself, this goes a long way to reduce ESD sensitivity. Additional ESD protection diodes have been added to the source and drain pins. Nevertheless, to maintain high speed, a compromise between ESD protection, speed, on-resistance, and on-capacitance had to be reached. This means that the protection diodes are relatively small and protect only up to about 500 V. To prevent damage from high-energy electrostatic fields, anti-static handling precautions must be observed at all times. For an 8-channel multiplexer the maximum sampling rate is given by: fS + 8 1 (t SETTLING ) tTRANS) rDS(on) C(on) (1) where tSETTLING = N (2) for an accuracy of 0.01% (12 bits) N = 9. For small signals, let us assume that typical rDS(on) = 18 Ω Applications The output node capacitance is given by: Following is a collection of practical application hints and design ideas intended to help you design with the DG61X family. Document Number: 70605 03-Aug-99 C(on) = 1 CD(on) + 7 CD(off) = 10 pF + 7 2 pF = 24 pF www.vishay.com S FaxBack 408-970-5600 6-5 AN207 Vishay Siliconix DG611 S1 S2 S3 S4 VOUT E3 X L Inputs Enable E2 X X H L L L L L L L L E1 H X X L L L L L L L L X X X L L L L H H H H Address A2 A1 X X X L L H H L L H H A0 X X X L H L H L H L H On O Switch None None None 1 2 3 4 5 6 7 8 DG611 S5 S6 S7 S8 X H H H H H H Y0 Y1 Y2 Y3 CD74HC138 Y4 Y5 Y6 Y7 H H H = High Level, L = Low Level X = Don’t Care A0 A1 A2 E1 E2 E3 FIGURE 9. High-Speed 8-Channel Multiplexer Capable of 3-MHz Sampling Rates +5 V Input Buffer +12 V Output Buffer Analog Input CLC111 S D LF356 "4 V Output to A/D Sample/Hold IN 1/ 2 DG611 CHOLD 650 pF Polystyrene –5 V FIGURE 10. High-Speed Open-Loop Sample-and-Hold Replacing into equation (1): Sample-and-Hold Circuits Data acquisition systems use sample-and-holds to “freeze” fast changing analog signals so they can be presented to an A/D converter for digitization. Accurately acquiring and holding the signal amplitude is critical to system performance. Figure 10 shows a basic open-loop sample-and-hold circuit. When the switch opens, a sample is stored on the hold capacitor. fS + 8(9 18 W 1 + 3.7 MHz 24 pF ) 30 ns) An added benefit of this circuit is its improvement of overall accuracy by isolating the analog and (usually noisy) digital grounds. This is because the DG611 CMOS input stage has a high noise immunity, allowing for differences of up to "1 V between the analog and digital grounds. www.vishay.com S FaxBack 408-970-5600 6-6 Document Number: 70605 03-Aug-99 AN207 Vishay Siliconix Aperature Error Analog Input Aperature Uncertainty (Jitter) Hold Step Slew Rate Analog Output Feedthrough Aperature Delay Aquisition Time Droop Rate = dV/dt Control Sample Hold FIGURE 11. Error Sources in Sample-and-Hold Circuits Because of non-ideal component characteristics, there are many sources of error in a sample-and-hold circuit. Figure 11 illustrates the most important ones. Table 1 lists these error sources and shows how the DG611 characteristics reduce those errors and improve overall circuit performance. Switched-Capacitor Filters Switched-capacitor filters (SCFs) offer high accuracy and excellent temperature stability. In addition, their cutoff frequencies are programmable over a wide range by simply changing the clock frequency. Figure 12 shows a closed loop sample-and-hold circuit. When SW1 and SW2 are closed, the output buffer is forced to track the analog input with a high degree of accuracy. SW3 improves acquisition time by letting the input buffer follow the input signal even during the hold periods. This circuit achieves high speed and high accuracy. Highly efficient audio frequency SCFs have been commercially available for several years, but since their sampling clocks need to be 25 to 100 times the signal frequency, they have been limited to applications in the 30- to 50-kHz range. TABLE 1 Programmable Low-Pass Filter Error Source Acquisition Time DG611 Parameter rDS(on) = 18 W t(on) = 12 ns t(off) = 8 ns t(off) = 8 ns DQ = 3 pC Off Isolation = 74 dB @ 5 MHz ID(off) = 0.25 nA Benefit Faster sampling,settling times Minimal turn-off delay Consistent propagation delay Minimal switching glitches Low capacitive coupling Guaranteed low leakages Many active filter implementations can be made programmable by using analog switches to select different component values into the circuit. Figure 13 illustrates a low-pass filter where a single DG613 is used to change the corner frequencies from 300 kHz to 400 kHz by selecting one of two resistor pairs. Keeping the input and feedback resistor values equal maintains unity gain. The DG613s low parasitic capacitances improve frequency response and permit operation at higher frequencies. Document Number: 70605 03-Aug-99 Aperature Delay Aperature Uncertainty Hold Step Feed Through Droop Rate www.vishay.com S FaxBack 408-970-5600 6-7 AN207 Vishay Siliconix SW2 SW3 SW1 Analog Input VOUT CH S/H DG613 FIGURE 12. Fast and Accurate Closed-Loop Sample-and-Hold Thanks to its high speed, low rDS(on) and low capacitances, the DG611 family makes it possible to implement SCFs with cutoff frequencies in the 1-MHz range. These higher frequencies are suitable for applications in the radio IF range (400-500 kHz). Using high-speed Op Amps and chip resistors it is possible to implement these SCFs in small hybrids. The advantage of an RF SCF is that the filter’s characteristics can be digitally controlled to adapt to the instantaneous bandwidth of the desired signal. Figure 14(a) illustrates a simple low pass filter and its frequency response 14(b). Figure 14(c) is an SCF implementation that uses an inverting switched-capacitor integrator approach. Video Overlaying An inexpensive NTSC video titler can be implemented by superimposing the output of a character generator on a standard composite video background. A high-speed switch like the DG613 is used to select certain pixel groups from one of the two available sources during each horizontal line sweep. The same principle can be used to combine two video signals into a single image (i.e. blue background.) Both video sources must be sync-locked. An advantage of the DG61X family is that its low charge injection eliminates switching noise that could appear as halos or shadows around the superimposed image. It is worth noting that if you disregard the propagation delay in the driver stages, the effective switching transition time from one video signal to the other is well below 5 ns! 100 pF DG613 fSELECT 400 W 400 W 300 W Figure 15 illustrates a basic pixel-rate switch circuit. Each incoming signal arrives to its own 75-Ω termination resistor. The DG613 is configured for a single-pole double-throw function and selects one of the two signals at a time. The CLC410 amplifier drives a 75-Ω back- terminated output line. VOUT VIN 300 W LF356A f –3dB + 1 2pRC A back-terminated line provides impedance matching and eliminates any reflections caused by possible impedance disturbances on the transmission line. Connectors, transitions from coax cable to PC board traces, and transitions from board traces to IC package lead will cause slight impedance mismatches. FIGURE 13. Programmable Low-Pass Filter The output amplifier must have a gain of 2 (6 dB) since the back-termination resistor will introduce a 6-dB loss. Document Number: 70605 03-Aug-99 www.vishay.com S FaxBack 408-970-5600 6-8 AN207 Vishay Siliconix C Av Rf Rf Ri Ri VIN VOUT 1 R fC w a) Active Low Pass Filter C b) Frequency Response DG613 fCLK VIN VOUT Ci c) SCF Implementation Ri + 1 Ci fCLK Rf + 1 C f CLK FIGURE 14. Low Pass Switched-Capacitor Filter Video DC Restoration Sending video signals over long cable runs often causes dc offsets and may add power-line hum. When this is the case, a back porch clamp (or dc restorer) is used to return the waveform to its proper dc reference level. The same principle is used for picture brightness adjustments. the GHz region when, as shown in Figure 15, it is used to drive GaAs FET switches. This circuit benefits from the DG613s high speed, low capacitances, and low power characteristics. DAC Deglitcher GaAs Driver The DG611 family is capable of switching RF signals up into the UHF frequencies. The DG613 is ideal for switching RF in Document Number: 70605 03-Aug-99 All DACs produce output glitches when the digital input data changes. The worst spikes occur when the MSB changes state, and at one-fourth and three-fourths of full scale. A deglitcher circuit as shown in Figure 18 acts as a track-and-hold and removes the output glitches. The DG611 is ideal because of its low charge injection and high speed. www.vishay.com S FaxBack 408-970-5600 6-9 AN207 Vishay Siliconix +5 V +12 V Output Buffer Background 75 W 1/ 2 S1 D1 + CLC410 75 W Composite Output CLC114 S2 D2 – 250 W 250 W Titles 75 W 5 V Control 1/ 2 DG613 –5 V FIGURE 15. Pixel-Rate Switch Creates Video Overlays Video In 10 mF 75 W 75 W 10 kW CLC410 Video Out Clamp Gate DG611 250 W 250 W Clamp Level 1 mF FIGURE 16. Fast Switch Restores Back Porch to Proper dc Level +5 V GaAs S1 IN1 VL V+ D1 RF IN RF OUT 1/ 2 DG613 D2 S2 IN2 Control GND V– –8 V FIGURE 17. High-Speed GaAs FET Driver Saves Power www.vishay.com S FaxBack 408-970-5600 Document Number: 70605 03-Aug-99 6-10 AN207 Vishay Siliconix Ref RFB DAC IOUT VOUT VOUT T/H T/H 1/ 2 DG613 Deglitched VOUT FIGURE 18. DAC Deglitcher DG612 R V1 V2 V3 V4 VOUT RF a) On-State "1 pA rDS(on) S 18 W CS(on) 10 pF D ID(on) b) Off-State "1 pA VOUT + – RF R (V1 ) ... ) V4) S IS(off) CSD(off) "1 pA ID(off) D 0.5 pF CS(off) 3 pF CD(off) 2 pF FIGURE 19. Low Distortion Audio Mixer Eliminates Switching Noise FIGURE 20. Static Switch Models Audio Mixer Switching audio inputs at the summing junction of an op amp eliminates audio distortion due to on-resistance modulation. This is because when turned on, the analog switch channel stays at a constant 0 V. Unfortunately, any charge injection Document Number: 70605 03-Aug-99 present during switching at the high impedance Op Amp input gets amplified and can cause large output spikes. These switching spikes usually cause clicking and/or popping noises. Thanks to its low charge injection properties, the DG61X family virtually eliminates this type of switching noise. A small snubber network connected across the op amp inputs further reduces any high-speed glitches. www.vishay.com S FaxBack 408-970-5600 6-11 AN207 Vishay Siliconix Switch Models The following static models are useful for analyzing circuit performance when the switch is fully on or fully off. For the dynamic parameters such as switching times and charge injection it is better to refer to the typical characteristic curves provided in the data sheet. The on-state model shown in Figure 20 uses typical parameter values for room temperature. The channel-on capacitance (CD(on)) and channel-on leakage (ID(on)) are placed on the output side to simulate the worst case possible. In reality, both parameters are distributed along the channel. If you would like to refine the model you may want to divide these lumped parameters into two or three fractions. Single-Supply Operation Disk drives and other computer peripherals may only have +12-V and +5-V power supplies or even just a single +5-V power supply. It is perfectly possible to operate the DG611 with the power-supply configurations shown in Figure 21. In case (c) the logic has to be 12-V CMOS. In (b), the switch on-resistance will be high and the analog dynamic range will be reduced to about 0 to 2 V, due to the limited channel enhancement voltage available. (See Figure 7.) Conclusion By integrating fast DMOS FETs with high-speed CMOS drivers, the DG611 family of monolithic analog switches improves reliability and reduces part count. These fast analog switches simultaneously establish new records for high speed, low charge injection, and low power. These significant performance achievements bring considerable benefits to many dynamic switching applications. References: Vishay Siliconix, DG611 Data Sheet (FaxBack document number 70057). Analog Devices, 1986. Data Acquisition Handbook. National Semiconductor, 1985. Switched-Capacitor Filter Handbook. +5 V +5 V +12 V +12 V VL V+ VL V+ VL V+ DG611 DG612 DG613 GND V– GND V– GND V– a) b) c) FIGURE 21. Unipolar Supply Configurations www.vishay.com S FaxBack 408-970-5600 6-12 Document Number: 70605 03-Aug-99