AN605

AN605 Vishay Siliconix Power MOSFET Basics: Understanding MOSFET Characteristics Associated With The Figure of Merit Jess Brown, Guy Moxey INTRODUCTION Power MOSFETs have become the standard choice as the main switching device for low-voltage (200 million cells/inch2) are achievable. It is beneficial to have incremental steps up to this level of cell density, thereby creating a family of devices balancing ultra-low on-resistance, gate characteristics, and cost. However, the increase in die per wafer, which improves cost benefits, and reduction in rDS(on), which improves performance, remain the two most compelling advantages. Figure 3 shows a cross-section of the MOSFET Trench die at a density of 178 million cells/inch2. This is a slice through the actual ultra-high-density cell wafer in an area that demonstrates the high-density cell scaling. To achieve such a cell figure, the focus has been placed on both the lateral and vertical cell scaling, optimizing not only the rDS(on) but also the gate characteristics. Along with advances in lateral scaling designed to increase the cell density, there also have been improvements in the associated capacitance, Figure 3b, to enhance fast switching, which is essential for high-frequency operation (>400 kHz). Also at light current loads, the gate drive losses become a significant contributing factor to the overall system efficiency, so the gate capacitances must be taken into consideration. The vertical scaling improvements have achieved lower capacitance, resulting in lower merit values of rDS(on) x Qg of