FC40SA50FK

FC40SA50FKP Vishay Semiconductors Power MOSFET, 40 A FEATURES • Low gate charge Qg results in simple drive requirement • Improved gate, avalanche and dynamic dV/dt ruggedness • Fully characterized capacitance and avalanche voltage and current SOT-227 • Low RDS(on) • Fully insulated package • UL pending PRODUCT SUMMARY VDSS RDS(on) (typical) ID Type Package 500 V 0.084 Ω 40 A Modules - MOSFET SOT-227 • Compliant to RoHS directive 2002/95/EC • Designed and qualified for industrial level APPLICATIONS • Switch mode power supply (SMPS) • Uninterruptible power supply • High speed power switching • Hard switched and high frequency circuits ABSOLUTE MAXIMUM RATINGS PARAMETER Continuous drain current, VGS at 10 V Pulsed drain current Power dissipation Linear derating factor Gate to source voltage Peak diode recovery dV/dt Operating junction and storage temperature range VGS dV/dt (2) TJ, TStg SYMBOL ID IDM (1) PD TC = 25 °C TEST CONDITIONS TC = 25 °C TC = 100 °C MAX. 40 26 160 430 3.45 ± 30 9.0 - 55 to + 150 W W/°C V V/ns °C A UNITS Notes (1) Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) (2) I SD ≤ 40 A, dI/dt ≤ 150 A/μs, VDD ≤ V(BR)DSS, TJ ≤ 150 °C AVALANCHE CHARACTERISTICS PARAMETER Single pulse avalanche energy Avalanche current Repetitive avalanche energy SYMBOL EAS (1) IAR (2) TYP. - MAX. 1240 40 43 UNITS mJ A mJ EAR (2) Notes (1) Starting T = 25 °C, L = 1.55 mH, R = 25 Ω, I J g AS = 40 A, dV/dt = 5.5 V/ns (see fig. 12a) (2) Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) Document Number: 94542 Revision: 12-May-10 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com www.vishay.com 1 FC40SA50FKP Vishay Semiconductors THERMAL RESISTANCE PARAMETER Junction to case Case to sink, flat, greased surface SYMBOL RthJC RthCS TYP. 0.05 MAX. 0.29 UNITS °C/W Power MOSFET, 40 A STATIC CHARACTERISTICS (TJ = 25 °C unless otherwise noted) PARAMETER Drain to source breakdown voltage SYMBOL V(BR)DSS RDS(on) (1) TEST CONDITIONS VGS = 0 V, ID = 250 μA Reference to 25 °C, ID = 1 mA VGS = 10 V, ID = 24 A VDS = VGS, ID = 250 μA VDS = 500 V, VGS = 0 V VDS = 400 V, VGS = 0 V, TJ = 125 °C VGS = 30 V VGS = - 30 V MIN. 500 3.0 - TYP. 0.60 0.084 - MAX. 0.10 5.0 50 250 250 - 250 UNITS V V/°C Ω V μA Breakdown voltage temperature coefficient ΔV(BR)DSS/ΔTJ Static drain to source on-resistance Gate threshold voltage Drain to source leakage current Gate to source forward leakage Gate to source reverse leakage Note (1) Pulse width ≤ 300 μs; duty cycle ≤ 2 % VGS(th) IDSS IGSS nA DYNAMIC CHARACTERISTICS (TJ = 25 °C unless otherwise noted) PARAMETER Forward transconductance Total gate charge Gate to source charge Gate to drain ("Miller") charge Turn-on delay time Rise time Turn-off delay time Fall time Input capacitance Output capacitance Reverse transfer capacitance Output capacitance Effective output capacitance (1) SYMBOL gfs Qg Qgd tr (1) TEST CONDITIONS VDS = 50 V, ID = 28 A ID = 40 A VDS = 400 V VGS = 10 V; see fig. 6 and 13 VDD = 250 V ID = 40 A Rg = 1.0 Ω VGS = 10 V, see fig. 10 VGS = 0 V VDS = 25 V f = 1.0 MHz, see fig. 5 VGS = 0 V, VDS = 1.0 V, f = 1.0 MHz VGS = 0 V, VDS = 480 V, f = 1.0 MHz VGS = 0 V, VDS = 0 V to 480 V MIN. 23 - TYP. 25 140 55 74 8310 960 120 10 170 240 440 MAX. 270 84 130 - UNITS S Qgs (1) (1) nC td(on) (1) (1) td(off) (1) tf (1) Ciss Coss Crss Coss Coss eff. (2) ns pF Notes Pulse width ≤ 300 μs; duty cycle ≤ 2 % (2) C oss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDSS www.vishay.com 2 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com Document Number: 94542 Revision: 12-May-10 FC40SA50FKP Power MOSFET, 40 A Vishay Semiconductors DIODE CHARACTERISTICS PARAMETER Continuous source current (body diode) Pulsed source current (body diode) Diode forward voltage Reverse recovery time Reverse recovery charge Reverse recovery current Forward turn-on time SYMBOL IS ISM (1) VSD (2) trr (2) TEST CONDITIONS D MIN. S TYP. 620 14 38 MAX. 40 UNITS MOSFET symbol showing the integral reverse p-n junction diode TJ = 25 °C, IS = 40 A, VGS = 0 V A G 160 1 940 21 V ns μC A - Qrr IRRM ton TJ = 25 °C, IF = 47 A; dI/dt = 100 A/μs TJ = 25 °C Intrinsic turn-on time is negligible (turn-on is dominated by LS + LD) Notes (1) Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) (2) Pulse width ≤ 300 μs; duty cycle ≤ 2 % 1000 VGS 15 10 8.0 7.0 6.0 5.5 B O TTO M 5.0 TO P 1000 ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) 100 100 TJ =150°C 10 10 1 5V TJ =25°C 1 V DS =20V 20μs PULSE WIDTH 0.1 0.1 20 μs PULSE WIDTH TJ=25°C 0.01 0.1 1 10 100 VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics 4 5 6 7 8 9 10 11 12 V GS , Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics 1000 VG S 3.5 15 10 8.0 7.0 6.0 5.5 5.0 B O TTO M 4.5 TO P 100 RDS(on), Drain-to-Source On Resistance (Normalized) 3.0 ID=24A ID, Drain-to-Source Current (A) 2.5 2.0 10 1.5 1 4.5 V 20 μs PULSE WIDTH T 150°C 1.0 V GS =10V 0.5 0.1 0.1 1 0.0 10 100 -60 -40 -20 0 20 40 60 80 100 120 140 160 VDS, Drain-to-Source Voltage (V) TJ , Junction Temperature (°C) Fig. 2 - Typical Output Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 94542 Revision: 12-May-10 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com www.vishay.com 3 FC40SA50FKP Vishay Semiconductors 100000 VGS Ciss C rss Coss = 0V, f = 1 MHZ = Cgs + C gd, Cds SHORTED =C gd = Cds + C gd Power MOSFET, 40 A 1000 OPERATION IN THIS AREA LIMITED BY RDS(on) ID, Drain Current (A) 10000 C, Capacitance(pF) Ciss 100 1000 100us 10 TC = 25°C TJ = 150°C Single Pulse 1 1ms 10ms Coss 100 Crss 10 1 10 100 1000 10 100 V DS, Drain-to-Source Voltage (V) 1000 VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain to Source Voltage 20 ID =40A Fig. 8 - Maximum Safe Operating Area 40 VGS, Gate-to-Source Voltage (V) 15 10 ID, Drain Current (A) 0 100 200 300 30 20 5 10 0 0 25 50 75 100 125 150 QG, Total Gate Charge (nC) TC, Case Temperature (°C) Fig. 6 - Typical Gate Charge vs. Gate to Source Voltage 1000 Fig. 9 - Maximum Drain Current vs. Case Temperature ISD, Reverse Drain Current (A) 100 TJ=150°C 10 TJ=25°C 1 VDS VGS RG RD D.U.T. + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % VGS=0 0.1 0.2 0.7 1.2 1.7 VSD, Source-to-Drain Voltage (V) Fig. 7 - Typical Source Drain Diode Forward Voltage Fig. 10a - Switching Time Test Circuit www.vishay.com 4 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com Document Number: 94542 Revision: 12-May-10 FC40SA50FKP Power MOSFET, 40 A Vishay Semiconductors VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 10b - Switching Time Waveforms 1.000 Thermal Response ( ZthJC 0.100 D = 0.50 0.30 0.10  R1 R1 J R2 R2 R3 R3  C  J 0.010 0.05 0.02 0.01 SINGLE PULSE (THERMAL RESPONSE)   Ri (°C/W) 0.161 0.210 0.147 τi (sec) 0.000759 0.017991 0.06094 1   1 2   2 3  3 Ci=  i Ri Ci i Ri Notes: 1. Duty factor D = t1/t2 2. Peak TJ=PDM x ZthJC + TC 0.01 0.1 1 0.001 0.00001 0.0001 0.001 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction to Case 3000 EAS, Single Pulse Avalanche Energy (mJ) TOP 2500 BOTTOM ID ... 18A 26A 40A 15 V 2000 1500 VDS 1000 L Driver RG 500 20 V D.U.T IAS tp 25 50 75 100 125 150 S tarting TJ, Junction Tem perature (°C) + - VDD A 0 0.01 Ω Fig. 12a - Maximum Avalanche Energy vs. Drain Current Fig. 12b - Unclamped Inductive Test Circuit Document Number: 94542 Revision: 12-May-10 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com www.vishay.com 5 FC40SA50FKP Vishay Semiconductors Power MOSFET, 40 A V(BR)DSS tp RL + VGS D.U .T. - VDS 1 mA IAS ID Fig. 12c - Unclamped Inductive Waveforms Fig. 13a - Gate Charge Test Circuit QG VGS V QGS QGD VG Charge Fig. 13b - Basic Gate Charge Waveform D.U.T. + 3 Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + 2 - - 4 + 1 RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - Device under test + VDD Fig. 13c - Peak Diode Recovery dV/dt Test Circuit www.vishay.com 6 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com Document Number: 94542 Revision: 12-May-10 FC40SA50FKP Power MOSFET, 40 A Vishay Semiconductors Driver Gate Drive P.W. Period D= P.W. Period VGS=10V * D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt VDD Re-Applied Voltage Inductor Curent Body Diode Forward Drop Ripple ≤ 5% ISD * VGS = 5V for Logic Level Devices Fig. 14 - For N-Channel Power MOSFETs ORDERING INFORMATION TABLE Device code F 1 1 2 3 4 5 6 7 8 - C 2 40 3 S 4 A 5 50 6 FK 7 P 8 Power MOSFET Generation 6.2/6.3 MOSFET silicon DBC construction Current rating (40 = 40 A) Single switch (see Circuit Configuration table) SOT-227 Voltage rating (50 = 500 V) MOSFET K speed None = Standard production P = Lead (Pb)-free Document Number: 94542 Revision: 12-May-10 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com www.vishay.com 7 FC40SA50FKP Vishay Semiconductors CIRCUIT CONFIGURATION CIRCUIT CIRCUIT CONFIGURATION CODE CIRCUIT DRAWING Lead assignment S D 3 2 S G Power MOSFET, 40 A D (3) Single switch no diode S G (2) 4 1 S (1-4) LINKS TO RELATED DOCUMENTS Dimensions Packaging information www.vishay.com/doc?95036 www.vishay.com/doc?95037 www.vishay.com 8 For technical questions within your region, please contact one of the following: DiodesAmericas@vishay.com, DiodesAsia@vishay.com, DiodesEurope@vishay.com Document Number: 94542 Revision: 12-May-10 Outline Dimensions Vishay Semiconductors SOT-227 DIMENSIONS in millimeters (inches) 38.30 (1.508) 37.80 (1.488) Ø 4.40 (0.173) Ø 4.20 (0.165) 4 4 x M4 nuts -A3 6.25 (0.246) 12.50 (0.492) 1 7.50 (0.295) 15.00 (0.590) 30.20 (1.189) 29.80 (1.173) 8.10 (0.319) 4x 7.70 (0.303) 2.10 (0.082) 1.90 (0.075) 2 R full 25.70 (1.012) 25.20 (0.992) -BChamfer 2.00 (0.079) x 45° 0.25 (0.010) M C A M B M 2.10 (0.082) 1.90 (0.075) -C0.12 (0.005) 12.30 (0.484) 11.80 (0.464) Notes • Dimensioning and tolerancing per ANSI Y14.5M-1982 • Controlling dimension: millimeter Document Number: 95036 Revision: 28-Aug-07 For technical questions, contact: indmodules@vishay.com www.vishay.com 1 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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