IRF730A, SiHF730A
Vishay Siliconix
Power MOSFET
PRODUCT SUMMARY
VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 10 V 22 5.8 9.3 Single
D
FEATURES
400 5.5
• Low Gate Charge Qg results in Simple Drive Requirement • Improved Gate, Avalanche and Dynamic dV/dt Ruggedness • Fully Characterized Capacitance Avalanche Voltage and Current • Effective Coss Specified (See AN1001) • Lead (Pb)-free Available and
Available
RoHS*
COMPLIANT
TO-220
APPLICATIONS
• Switch Mode Power Supply (SMPS)
G
• Uninterruptible Power Supply • High Speed Power Switching
S G D S N-Channel MOSFET
TYPICAL SMPS TOPOLOGIES
• Single Transistor Flyback Xfmr. Reset • Single Transistor Forward Xfmr. Reset (Both US Line Input Only)
ORDERING INFORMATION
Package Lead (Pb)-free SnPb TO-220 IRF730APbF SiHF730A-E3 IRF730A SiHF730A
ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted
PARAMETER Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Repetitive Avalanche Currenta Repetitive Avalanche Energya Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque for 10 s 6-32 or M3 screw TC = 25 °C EAS IAR EAR PD dV/dt TJ, Tstg VGS at 10 V TC = 25 °C TC = 100 °C SYMBOL VGS ID IDM LIMIT ± 30 5.5 3.5 22 0.6 290 5.5 7.4 74 4.6 - 55 to + 150 300d 10 1.1 W/°C mJ A mJ W V/ns °C lbf · in N·m A UNIT V
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Starting TJ = 25 °C, L = 19 mH, RG = 25 Ω, IAS = 5.5 A (see fig. 12). c. ISD ≤ 5.5 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 91045 S-Pending-Rev. A, 19-Jun-08 www.vishay.com 1
WORK-IN-PROGRESS
IRF730A, SiHF730A
Vishay Siliconix
THERMAL RESISTANCE RATINGS
PARAMETER Maximum Junction-to-Case (Drain) Case-to-Sink, Flat, Greased Surface Maximum Junction-to-Ambient SYMBOL RthJC RthCS RthJA TYP. 0.50 MAX. 1.70 62 °C/W UNIT
SPECIFICATIONS TJ = 25 °C, unless otherwise noted
PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Effective Output Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode
D
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS ΔVDS/TJ VGS(th) IGSS IDSS RDS(on) gfs
VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 30 V VDS = 400 V, VGS = 0 V VDS = 320 V, VGS = 0 V, TJ = 125 °C VGS = 10 V ID = 3.3 Ab VDS = 50 V, ID = 3.3 A VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 VDS = 1.0 V, f = 1.0 MHz VGS = 0 V VDS = 320 V, f = 1.0 MHz VDS = 0 V to 320 Vc
400 2.0 3.1
0.5 -
4.5 ± 100 25 250 1.0 -
V V/°C V nA µA Ω S
Ciss Coss Crss Coss Coss eff. Qg Qgs Qgd td(on) tr td(off) tf VGS = 10 V
-
600 103 4.0 890 30 45 10 22 20 16
22 5.8 9.3 ns nC pF
ID = 3.5 A, VDS = 320 V see fig. 6 and 13b
-
VDD = 200 V, ID = 3.5 A RG = 12 Ω, RD = 57 Ω, see fig. 10b
-
-
370 1.6
5.5 A 22 1.6 550 2.4 V ns µC
G
S
TJ = 25 °C, IS = 5.5 A, VGS = 0
Vb
TJ = 25 °C, IF = 3.5 A, dI/dt = 100 A/µsb
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. c. COSS eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS.
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Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
IRF730A, SiHF730A
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
100
100
VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V BOTTOM 4.5 V TOP
ID, Drain-to-Source Current (A)
10
ID, Drain-to-Source Current (A)
10
TJ = 150 °C
1
1
TJ = 25 °C
0.1
4.5 V
20 µs PULSE WIDTH TJ = 25 °C 1 10
VDS = 50 V 20 µs PULSE WIDTH
0.01 0.1
100
0.1 4.0
5.0
6.0
7.0
8.0
9.0
10.0
VDS, Drain-to-Source Voltage (V) Fig. 1 - Typical Output Characteristics
VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics
100
RDS(on), Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current (A)
10
VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V BOTTOM 4.5 V TOP
2.5
ID = 5.5 A
2.0
1.5
1
4.5 V
0.1
1.0
0.5
0.01 0.1
20 µs PULSE WIDTH TJ = 25 °C
1
10
100
0.0 -60 -40 -20
VGS = 10 V
0 20 40 60 80 100 120 140 160
VDS, Drain-to-Source Voltage (V)
Fig. 2 - Typical Output Characteristics
TJ, Junction Temperature (°C) Fig. 4 - Normalized On-Resistance vs. Temperature
Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
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IRF730A, SiHF730A
Vishay Siliconix
100000
100
C, Capacitance (pF)
10000
ISD, Reverse Drain Current (A)
VGS = 0 V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
10
TJ = 150 °C
1000
Ciss Coss
100
1
TJ = 25 °C
10
Crss
1 1 10 100 1000
0.1 0.4
VGS = 0 V 0.6
0.8
1.0
1.2
VDS, Drain-to-Source Voltage (V) Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage
VSD, Source-to-Drain Voltage (V)
Fig. 7 - Typical Source-Drain Diode Forward Voltage
20
ID = 5.5 A
100
VDS = 320 V VDS = 200 V VDS = 80 V
OPERATION IN THIS AREA LIMITED BY RDS(on)
VGS, Gate-to-Source Voltage (V)
16
ID, Drain Current (A)
10 us 10 100 us
12
8
1 ms 1 10 ms
4
FOR TEST CIRCUIT SEE FIGURE 13
TC = 25 °C TJ = 150 °C Single Pulse
0
0
5
10
15
20
25
0.1 10
100
1000
QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage
VDS, Drain-to-Source Voltage (V)
Fig. 8 - Maximum Safe Operating Area
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Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
IRF730A, SiHF730A
Vishay Siliconix
RD VDS VGS D.U.T. + - VDD 10 V
Pulse width ≤ 1 µs Duty factor ≤ 0.1 %
6.0
5.0
RG
ID, Drain Current (A)
4.0
3.0
Fig. 10a - Switching Time Test Circuit
2.0
VDS 90 %
1.0
0.0
25
50
75
100
125
150
TC, Case Temperature
(°C)
10 % VGS td(on) tr td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b - Switching Time Waveforms
10
Thermal Response (ZthJC)
1
D = 0.50 0.20 0.10
0.1
0.05 0.02 0.01
PDM t1
SINGLE PULSE (THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t1 / t2 2. Peak TJ = PDM x ZthJC + TC
0.01 0.00001
0.0001
0.001
0.01
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
VDS
L
Driver
RG 20 V tp
D.U.T. IAS 0.01 Ω
+ A - VDD
IAS
Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5
IRF730A, SiHF730A
Vishay Siliconix
700
EAS, Single Pulse Avalanche Energy (mJ)
600 500 400 300 200 100 0 25
VDSav, Avalanche Voltage (V)
ID 2.5 A 3.5 A BOTTOM 5.5 A TOP
610 600 590 580 570 560 550 540
50
75
100
125
150
0.0
1.0
Starting TJ, Junction Temperature (°C) Fig. 12c - Maximum Avalanche Energy vs. Drain Current
2.0 3.0 4.0 Iav, Avalanche Current (A)
5.0
6.0
Fig. 12d - Typical Drain Source Voltage vs. Avalanche Current
Current regulator Same type as D.U.T. QG
12 V
10 V QGS
50 kΩ 0.2 µF 0.3 µF
QGD
+
D.U.T.
-
VDS
VG
VGS
3 mA
Charge
IG ID Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
Fig. 13b - Gate Charge Test Circuit
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Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
IRF730A, SiHF730A
Vishay Siliconix
Peak Diode Recovery dV/dt Test Circuit
D.U.T.
+
Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer
+ +
-
RG
• • • •
dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test
+ VDD
Driver gate drive P.W. Period D=
P.W. Period VGS = 10 V*
D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt
VDD
Re-applied voltage Inductor current
Body diode
forward drop
Ripple ≤ 5 %
I SD
* VGS = 5 V for logic level devices
Fig. 14 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?91045.
Document Number: 91045 S-Pending-Rev. A, 19-Jun-08
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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