IRLIZ24G

IRLIZ24G, SiHLIZ24G Vishay Siliconix Power MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) Qg (Max.) (nC) Qgs (nC) Qgd (nC) Configuration VGS = 5.0 V 18 4.5 12 Single 60 0.10 FEATURES • Isolated Package • High Voltage Isolation = 2.5 kVRMS (t = 60 s; f = 60 Hz) • Sink to Lead Creepage Distance = 4.8 mm • Logic-Level Gate Drive • RDS(on) Specified at VGS = 4 V and 5 V • Fast Switching • Ease of Paralleling • Lead (Pb)-free RoHS COMPLIANT TO-220 FULLPAK D DESCRIPTION Third generation Power MOSFETs from Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The TO-220 FULLPAK eliminates the need for additional insulating hardware in commercial-industrial applications. The molding compound used provides a high isolation capability and a low thermal resistance between the tab and external heatsink. This isolation is equivalent to using a 100 micron mica barrier with standard TO-220 product. The FULLPAK is mounted to a heatsink using a single clip or by a single screw fixing. G S GDS N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free TO-220 FULLPAK IRLIZ24GPbF SiHLIZ24G-E3 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Drain-Source Voltage Gate-Source Voltage Continuous Drain Current Pulsed Drain Currenta Linear Derating Factor Single Pulse Avalanche Energyb Maximum Power Dissipation Peak Diode Recovery dV/dtc Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) Mounting Torque Notes a. b. c. d. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). VDD = 25 V, starting TJ = 25 °C, L = 595 µH, RG = 25 Ω, IAS = 14 A (see fig. 12c). ISD ≤ 17 A, dI/dt ≤ 140 A/µs, VDD ≤ VDS, TJ ≤ 175 °C. 1.6 mm from case. for 10 s 6-32 or M3 screw TC = 25 °C EAS PD dV/dt TJ, Tstg VGS at 5.0 V TC = 25 °C TC = 100 °C SYMBOL VDS VGS ID IDM LIMIT 60 ± 10 14 10 56 0.24 100 37 4.5 - 55 to + 175 300d 10 1.1 W/°C mJ W V/ns °C lbf · in N·m A UNIT V Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 www.vishay.com 1 IRLIZ24G, SiHLIZ24G Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER Maximum Junction-to-Ambient Maximum Junction-to-Case (Drain) SYMBOL RthJA RthJC TYP. MAX. 65 4.1 UNIT °C/W SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current VDS ΔVDS/TJ VGS(th) IGSS IDSS VGS = 0 V, ID = 250 µA Reference to 25 °C, ID = 1 mA VDS = VGS, ID = 250 µA VGS = ± 10 V VDS = 60 V, VGS = 0 V VDS = 48 V, VGS = 0 V, TJ = 150 °C VGS = 5.0 V VGS = 4.0 V ID = 8.4 Ab ID = 7.0 Ab 60 1.0 7.3 0.065 2.0 ± 100 25 250 0.10 0.14 V V/°C V nA µA Ω Ω S SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Drain-Source On-State Resistance Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Drain to Sink Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Internal Drain Inductance Internal Source Inductance Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Currenta Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Forward Turn-On Time RDS(on) gfs VDS = 25 V, ID = 8.4 Ab Ciss Coss Crss C Qg Qgs Qgd td(on) tr td(off) tf LD LS VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 f = 1.0 MHz ID = 17 A, VDS = 48 V, see fig. 6 and 13b - 870 360 53 12 11 110 23 41 4.5 7.5 18 4.5 12 nH ns nC pF VGS = 5.0 V - VDD = 30 V, ID = 17 A, RG = 9.0 Ω, RD= 1.7 Ω, see fig. 10b - Between lead, 6 mm (0.25") from package and center of die contact D - G S IS ISM VSD trr Qrr ton MOSFET symbol showing the integral reverse p - n junction diode D - 130 0.75 14 A 56 1.5 260 1.5 V ns µC G S TJ = 25 °C, IS = 14 A, VGS = 0 Vb TJ = 25 °C, IF = 17 A, dI/dt = 100 A/µsb Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. www.vishay.com 2 Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 IRLIZ24G, SiHLIZ24G Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics Fig. 2 - Typical Output Characteristics, TC = 175 °C Fig. 4 - Normalized On-Resistance vs. Temperature Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 www.vishay.com 3 IRLIZ24G, SiHLIZ24G Vishay Siliconix Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area www.vishay.com 4 Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 IRLIZ24G, SiHLIZ24G Vishay Siliconix RD VDS VGS RG D.U.T. + - VDD 5.0 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) tr td(off) tf Fig. 9 - Maximum Drain Current vs. Case Temperature Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS RG VDS tp VDD D.U.T. I AS 5.0 V tp 0.01 Ω IAS Fig. 12b - Unclamped Inductive Waveforms www.vishay.com 5 VDS + - V DD VDS Fig. 12a - Unclamped Inductive Test Circuit Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 IRLIZ24G, SiHLIZ24G Vishay Siliconix Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ 12 V 0.2 µF 0.3 µF 5V QGS QG QGD D.U.T. + - VDS VG VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit www.vishay.com 6 Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 IRLIZ24G, SiHLIZ24G Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit D.U.T. + Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + + - RG • dV/dt controlled by RG • ISD controlled by duty factor "D" • D.U.T. - device under test + VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt VDD Re-applied voltage Inductor current Body diode forward drop Ripple ≤ 5 % ISD * VGS = 5 V for logic level 3 V drive devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91316. Document Number: 91316 S09-0037-Rev. A, 19-Jan-09 www.vishay.com 7 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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