SI1058X

SPICE Device Model Si1058X Vishay Siliconix N-Channel 20-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 4.5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74200 1 S-62686Rev. A, 01-Jan-07 www.vishay.com SPICE Device Model Si1058X Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 1.1 34 0.079 0.115 4.7 0.71 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = 250 µA VDS = 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 1.3 A VGS = 2.5 V, ID = 1.1 A VDS = 10 V, ID = 1.3A IS = 1 A V A 0.076 0.103 5.5 0.80 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Forward Voltagea b Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = 10 V, VGS = 5 V, ID = 1.3 A VDS = 10 V, VGS = 0 V, f = 1 MHz 471 65 30 3.4 3.1 VDS = 10 V, VGS = 4.5 V, ID = 1.3 A 0.82 0.61 380 75 45 3.9 3.51 0.82 0.61 nC pF Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74200 S-62686Rev. A, 01-Jan-07 SPICE Device Model Si1058X Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74200 S-62686Rev. A, 01-Jan-07 www.vishay.com 3