SI1902CDL

Si1902CDL Vishay Siliconix Dual N-Channel 20 V (D-S) MOSFET PRODUCT SUMMARY VDS (V) 20 RDS(on) () 0.235 at VGS = 4.5 V 0.306 at VGS = 2.5 V ID (A)a 1.1 1 Qg (Typ.) 0.9 FEATURES • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS SOT-363 SC-70 (6-LEADS) S1 1 6 D1 Marking Code PE XX YY G1 2 5 G2 • Load Switch and DC/DC Converter for Portable Devices • High Speed Switching D1 D2 D2 3 4 S2 Lot Traceability and Date Code Part # Code G1 G2 Top View Ordering Information: Si1902CDL-T1-E3 (Lead (Pb)-free) S1 N-Channel MOSFET S2 N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage TC = 25 °C Continuous Drain Current (TJ = 150 °C) TC = 70 °C TA = 25 °C TA = 70 °C Pulsed Drain Current (t = 300 µs) Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C TC = 25 °C Maximum Power Dissipation TC = 70 °C TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range TJ, Tstg PD IDM IS ID Symbol VDS VGS Limit 20 ± 12 1.1 0.9 1b, c 0.8b, c 2 0.35 0.25b, c 0.42 0.27 0.30b, c 0.23b, c - 55 to 150 °C W A Unit V THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambient Maximum Junction-to-Foot (Drain) Notes: a. Based on TC = 25 °C. b. Surface mounted on 1" x 1" FR4 board. c. t = 5 s. d. Maximum under steady state conditions is 410 °C/W. Document Number: 67876 S11-0867-Rev. A, 02-May-11 www.vishay.com 1 b, d Symbol t 5 s Steady State RthJA RthJF Typical 290 250 Maximum 350 300 Unit °C/W This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902CDL Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductance Dynamic Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off DelayTime Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Fall Time Reverse Recovery Rise Time Currenta b Symbol VDS VDS/TJ VGS(th)/TJ VGS(th) IGSS IDSS ID(on) RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd Rg td(on) tr td(off) tf td(on) tr td(off) tf IS ISM VSD trr Qrr ta tb Test Conditions VGS = 0 V, ID = 250 µA ID = 250 µA VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 12 V VDS = 20 V, VGS = 0 V VDS = 20 V, VGS = 0 V, TJ = 85 °C VDS  5 V, VGS = 4.5 V VGS = 4.5 V, ID = 1 A VGS = 2.5 V, ID = 0.3 A VDS = 10 V, ID = 1 A Min. 20 Typ. Max. Unit V 25 - 2.6 0.6 1.5 ± 100 1 10 0.195 0.255 3 62 20 7 2 0.9 0.2 0.2 12 4 13 11 9 6 16 13 10 0.235 0.306 mV/°C V nA µA A  ms 2 VDS = 10 V, VGS = 0 V, f = 1 MHz VDS = 10 V, VGS = 10 V, ID = 1 A VDS = 10 V, VGS = 4.5 V, ID = 1 A f = 1 MHz VDD = 10 V, RL = 12.5  ID  0.8 A, VGEN = 10 V, Rg = 1  2.4 pF 3 1.4 nC  VDD = 10 V, RL = 12.5  ID  0.8 A, VGEN = 4.5 V, Rg = 1  24 8 20 20 18 12 24 20 20 0.35 2 1.2 4 16 ns TC = 25 °C IS = 0.8 A IF = 0.8 A, dI/dt = 100 A/µs 0.8 2 8 5 3 A V nC ns Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. www.vishay.com 2 Document Number: 67876 S11-0867-Rev. A, 02-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902CDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 2 VGS = 5 V thru 2.5 V 0.8 2 ID - Drain Current (A) ID - Drain Current (A) 0.6 1.0 VGS = 2 V 1 0.4 TC = 25 °C 1 0.2 VGS = 1.5 V 0 0 0.5 1 1.5 2 VDS - Drain-to-Source Voltage (V) 0 0 0.5 1 1.5 2 VGS - Gate-to-Source Voltage (V) TC = 125 °C TC = - 55 °C Output Characteristics 0.40 80 Transfer Characteristics 0.34 RDS(on) - On-Resistance (Ω) Ciss 60 C - Capacitance (pF) 0.28 VGS = 2.5 V 40 0.22 VGS = 4.5 V 20 0.16 Coss Crss 0.10 0 0.5 1 ID - Drain Current (A) 1.5 2 0 0 5 10 15 VDS - Drain-to-Source Voltage (V) 20 On-Resistance vs. Drain Current and Gate Voltage 10 Capacitance 1.8 RDS(on) - On-Resistance (Normalized) ID = 1 A VGS - Gate-to-Source Voltage (V) 8 VDS = 10 V ID = 1 A VGS = 4.5 V 1.5 6 VDS = 5 V 4 VDS = 16 V 1.2 VGS = 2.5 V 0.9 2 0 0 0.5 1 1.5 2 Qg - Total Gate Charge (nC) 0.6 - 50 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature Document Number: 67876 S11-0867-Rev. A, 02-May-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902CDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 10 0.5 ID = 1 A RDS(on) - On-Resistance (Ω) IS - Source Current (A) 0.4 TJ = 125 °C 0.3 TJ = 150 °C 1 TJ = 25 °C 0.2 TJ = 25 °C 0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 VSD - Source-to-Drain Voltage (V) 0.1 1.8 2.6 3.4 4.2 5 VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage 1.20 10 On-Resistance vs. Gate-to-Source Voltage 8 1.05 ID = 250 μA 0.90 Power (W) VGS(th) (V) 6 4 0.75 2 0.60 - 50 - 25 0 25 50 75 100 125 150 0 0.001 0.01 TJ - Temperature (°C) 0.1 Time (s) 1 10 Threshold Voltage 10 Single Pulse Power (Junction-to-Ambient) Limited by RDS(on)* ID - Drain Current (A) 100 μs 1 1 ms 10 ms 0.1 100 ms TC = 25 °C Single Pulse 0.01 0.1 DC, 10s, 1s 100 BVDSS Limited 1 10 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient www.vishay.com 4 Document Number: 67876 S11-0867-Rev. A, 02-May-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902CDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1.2 0.9 ID - Drain Current (A) 0.6 0.3 0 0 25 50 75 100 125 150 TC - Case Temperature (°C) Current Derating* 0.5 0.4 0.4 0.3 0.3 Power (W) Power (W) 0.2 0.2 0.1 0.1 0 0 25 50 75 100 125 150 TC - Case Temperature (°C) 0.0 0 25 50 75 100 125 150 TA - Ambient Temperature (°C) Power Derating, Junction-to-Foot Power Derating, Junction-to-Ambient * The power dissipation PD is based on TJ(max.) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. Document Number: 67876 S11-0867-Rev. A, 02-May-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si1902CDL Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 Square Wave Pulse Duration (s) 1 10 100 Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 0.0001 0.001 0.01 0.1 Square Wave Pulse Duration (s) 1 10 100 Normalized Thermal Transient Impedance, Junction-to-Foot Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?67876. www.vishay.com 6 Document Number: 67876 S11-0867-Rev. A, 02-May-11 Package Information Vishay Siliconix SC 70: 6 LEADS MILLIMETERS 6 5 4 E1 E 1 2 3 -Be e1 D -Ac A2 A L A1 b INCHES Min 0.035 – 0.031 0.006 0.004 0.071 0.071 0.045 Dim A A1 A2 b c D E E1 e e1 L Min 0.90 – 0.80 0.15 0.10 1.80 1.80 1.15 Nom – – – – – 2.00 2.10 1.25 0.65BSC Max 1.10 0.10 1.00 0.30 0.25 2.20 2.40 1.35 Nom – – – – – 0.079 0.083 0.049 0.026BSC Max 0.043 0.004 0.039 0.012 0.010 0.087 0.094 0.053 1.20 0.10 1.30 0.20 7_Nom 1.40 0.30 0.047 0.004 0.051 0.008 7_Nom 0.055 0.012 ECN: S-03946—Rev. B, 09-Jul-01 DWG: 5550 Document Number: 71154 06-Jul-01 www.vishay.com 1 AN814 Vishay Siliconix Dual-Channel LITTLE FOOTR SC-70 6-Pin MOSFET Recommended Pad Pattern and Thermal Performance INTRODUCTION This technical note discusses the pin-outs, package outlines, pad patterns, evaluation board layout, and thermal performance for dual-channel LITTLE FOOT power MOSFETs in the SC-70 package. These new Vishay Siliconix devices are intended for small-signal applications where a miniaturized package is needed and low levels of current (around 250 mA) need to be switched, either directly or by using a level shift configuration. Vishay provides these devices with a range of on-resistance specifications in 6-pin versions. The new 6-pin SC-70 package enables improved on-resistance values and enhanced thermal performance. applications for which this package is intended. For the 6-pin device, increasing the pad patterns yields a reduction in thermal resistance on the order of 20% when using a 1-inch square with full copper on both sides of the printed circuit board (PCB). EVALUATION BOARDS FOR THE DUAL SC70-6 The 6-pin SC-70 evaluation board (EVB) measures 0.6 inches by 0.5 inches. The copper pad traces are the same as described in the previous section, Basic Pad Patterns. The board allows interrogation from the outer pins to 6-pin DIP connections permitting test sockets to be used in evaluation testing. The thermal performance of the dual SC-70 has been measured on the EVB with the results shown below. The minimum recommended footprint on the evaluation board was compared with the industry standard 1-inch square FR4 PCB with copper on both sides of the board. PIN-OUT Figure 1 shows the pin-out description and Pin 1 identification for the dual-channel SC-70 device in the 6-pin configuration. SOT-363 SC-70 (6-LEADS) S1 G1 D2 1 6 5 D1 THERMAL PERFORMANCE 2 G2 S2 3 4 Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the dual SC-70 6-pin package measured as junction-to-foot thermal resistance is 300_C/W typical, 350_C/W maximum. The “foot” is the drain lead of the device as it connects with the body. Note that these numbers are somewhat higher than other LITTLE FOOT devices due to the limited thermal performance of the Alloy 42 lead-frame compared with a standard copper lead-frame. Junction-to-Ambient Thermal Resistance (dependent on PCB size) Top View FIGURE 1. For package dimensions see outline drawing SC-70 (6-Leads) (http://www.vishay.com/doc?71154) BASIC PAD PATTERNS See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286) for the 6-pin SC-70. This basic pad pattern is sufficient for the low-power The typical RθJA for the dual 6-pin SC-70 is 400_C/W steady state. Maximum ratings are 460_C/W for the dual. All figures based on the 1-inch square FR4 test board. The following example shows how the thermal resistance impacts power dissipation for the dual 6-pin SC-70 package at two different ambient temperatures. Document Number: 71237 12-Dec-03 www.vishay.com 1 AN814 Vishay Siliconix SC-70 (6-PIN) Room Ambient 25 _C PD + TJ(max) * TA Rq JA 500 Elevated Ambient 60 _C PD + Rq JA Thermal Resistance (C/W) Dual EVB 400 TJ(max) * TA o* o PD + 150 Co 25 C 400 C W o* o PD + 150 Co 60 C 400 C W 300 PD + 312 mW PD + 225 mW 200 NOTE: Although they are intended for low-power applications, devices in the 6-pin SC-70 will handle power dissipation in excess of 0.2 W. Testing To aid comparison further, Figure 2 illustrates the dual-channel SC-70 thermal performance on two different board sizes and two different pad patterns. The results display the thermal performance out to steady state. The measured steady state values of RθJA for the dual 6-pin SC-70 are as follows: 100 1” Square FR4 PCB 0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs) FIGURE 2. Comparison of Dual SC70-6 on EVB and 1” Square FR4 PCB. LITTLE FOOT SC-70 (6-PIN) 1) Minimum recommended pad pattern (see Figure 2) on the EVB of 0.5 inches x 0.6 inches. 2) Industry standard 1” square PCB with maximum copper both sides. 518_C/W 413_C/W The results show that if the board area can be increased and maximum copper traces are added, the thermal resistance reduction is limited to 20%. This fact confirms that the power dissipation is restricted with the package size and the Alloy 42 leadframe. ASSOCIATED DOCUMENT Single-Channel LITTLE FOOT SC-70 6-Pin MOSFET Copper Leadframe Version, REcommended Pad Pattern and Thermal Performance, AN815, (http://www.vishay.com/doc?71334). www.vishay.com 2 Document Number: 71237 12-Dec-03 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SC-70: 6-Lead 0.067 (1.702) (2.438) 0.016 (0.406) 0.026 (0.648) 0.010 (0.241) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE www.vishay.com 18 (1.143) 0.096 0.045 (0.648) 0.026 Document Number: 72602 Revision: 21-Jan-08 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1