SI1907DL

SPICE Device Model Si1907DL Vishay Siliconix Dual P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71526 S-50232Rev. B, 28-Feb-05 www.vishay.com 1 SPICE Device Model Si1907DL Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 0.78 5.8 0.54 0.77 1.05 1.19 −0.76 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −4.5 V VGS = −4.5 V, ID = −0.53 A V A 0.57 0.80 1.25 1.1 −0.80 S V Ω Drain-Source On-State Resistance a rDS(on) VGS = −2.5 V, ID = −0.44 A VGS = −1.8 V, ID = −0.20 A Forward Transconductance a Diode Forward Voltage a gfs VSD VDS = −10 V, ID = −0.53 A IS = −0.23 A, VGS = 0 V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = −0.23 A, di/dt = 100 µs VDD = −6 V, RL = 12 Ω ID ≅ −0.50 A, VGEN = −4.5 V, RG = 6 Ω VDS = −6 V, VGS = −4.5 V, ID = −0.53 A 0.72 0.14 0.12 6 7 23 7 15 1.5 0.40 0.25 6 20 10 10 20 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71526 S-50232Rev. B, 28-Feb-05 SPICE Device Model Si1907DL Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71526 S-50232Rev. B, 28-Feb-05 www.vishay.com 3