SI2329DS

SPICE Device Model Si2329DS Vishay Siliconix P-Channel 8 V (D-S) MOSFET DESCRIPTION The attached SPICE model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the - 55 °C to + 125 °C temperature ranges under the pulsed 0 V to 5 V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the - 55 °C to + 125 °C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics SUBCIRCUIT MODEL SCHEMATIC D CGD M2 G RG Gy +– ETCV Gx CGS M1 R1 3 DBD S Note • This document is intended as a SPICE modeling guideline and does not constitute a commercial product datasheet. Designers should refer to the appropriate datasheet of the same number for guaranteed specification limits. Document Number: 63225 S11-1274-Rev. A, 04-Jul-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model Si2329DS Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER Static Gate-Source Threshold Voltage Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss VDS = - 4 V, VGS = - 4.5 V, ID = - 5.3 A Qg Qgs Qgd VDS = - 4 V, VGS = - 2.5 V, ID = - 5.3 A VDS = - 10 V, VGS = 0 V, f = 1 MHz 1480 481 438 17 11 1.7 6.2 1485 480 435 19.3 11.8 1.7 6.2 nC pF VGS(th) RDS(on) gfs VSD VDS = VGS, ID = - 250 μA VGS = - 4.5 V, ID = - 5.3 A VGS = - 2.5 V, ID = - 4.8 A VDS = - 4 V, ID = - 5.3 A IS = - 4.2 A 0.5 0.024 0.028 19 - 0.72 0.025 0.030 20 - 0.80 V  S V SYMBOL TEST CONDITIONS SIMULATED MEASURED DATA DATA UNIT Notes a. Pulse test; pulse width  300 μs, duty cycle  2 %. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 63225 S11-1274-Rev. A, 04-Jul-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 SPICE Device Model Si2329DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ = 25 °C, unless otherwise noted) 20 VGS = 5 V, 3 V, 2.5 V, 2 V 4 5 TJ = 125 °C 15 ID - Drain Current (A) ID - Drain Current (A) 3 TJ = - 55 °C 2 10 VGS = 1.5 V 5 1 VGS = 1 V TJ = 25 °C 0 0 0.0 0.5 1.0 1.5 2.0 VDS - Drain-to-Source Voltage (V) 0.0 0.3 0.6 0.9 1.2 1.5 VGS - Gate-to-Source Voltage (V) 0.090 2800 0.075 RDS(on) - On-Resistance (Ω) 2100 C - Capacitance (pF) 0.060 Ciss 1400 0.045 VGS = 2.5 V 0.030 700 Crss Coss 0.015 0 VGS = 4.5 V 5 10 ID - Drain Current (A) 15 20 0 0 2 4 6 8 VDS - Drain-to-Source Voltage (V) 5 ID = 5.3 A 10 VGS - Gate-to-Source Voltage (V) 4 VDS = 4 V 3 TJ = 150 °C TJ = 25 °C IS - Source Current (A) 0 5 10 15 20 1 2 1 0 0.1 0 0.2 0.4 0.6 0.8 1 Qg - Total Gate Charge (nC) VSD - Source-to-Drain Voltage (V) Note • Dots and squares represent measured data. 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