SI2331DS

SPICE Device Model Si2331DS Vishay Siliconix P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 72307 30-Apr-04 www.vishay.com 1 SPICE Device Model Si2331DS Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −4.5 V VGS = −4.5 V, ID = −3.6 A 0.72 94 0.035 0.046 0.062 14 −0.80 0.038 0.049 0.070 3 V A Drain-Source On-State Resistance a rDS(on) VGS = −2.5 V, ID = −3.2 Α VGS = −1.8 V, ID = −2.7 Α Ω Forward Transconductance Diode Forward Voltage a a gfs VSD VDS = −5 V, ID = − 3.6 A IS = −1.6 V, VGS = 0 V S V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Qg Qgs Qgd td(on) tr td(off) tf VDD = −6 V, RL = 6 Ω ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω VDS = −6 V, VGS = −4.5 V, ID = −3.6 A 8.2 1.3 2.5 20 21 66 15 9 1.3 2.5 20 35 65 50 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 72307 30-Apr-04 SPICE Device Model Si2331DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 72307 30-Apr-04 www.vishay.com 3