SI2337DS

SPICE Device Model Si2337DS Vishay Siliconix P-Channel 80-V (D-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74139 S-52290Rev. A, 31-Oct-05 www.vishay.com 1 SPICE Device Model Si2337DS Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 3.1 25 0.192 0.215 4 −0.74 Measured Data Unit VGS(th) ID(on) rDS(on) gfs VSD VDS = VGS, ID = −250 µA VDS = −5 V, VGS = −10 V VGS = −10 V, ID = −1.2 A VGS = −6 V, ID = −1.1 A VDS = −15 V, ID = −1.2 A IS = −0.63 A V A 0.216 0.242 4.3 −0.80 Ω S V Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltagea Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = −40 V, VGS = −10 V, ID = −1.2 A VDS = −40 V, VGS = −6 V, ID = −1.2 A VDS = −40 V, VGS = 0 V, f = 1 MHz 636 39 25 10 6 2.1 3.2 500 40 25 11 7 2.1 3.2 nC pF Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74139 S-52290Rev. A, 31-Oct-05 SPICE Device Model Si2337DS Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74139 S-52290Rev. A, 31-Oct-05 www.vishay.com 3