SI4532ADY

SPICE Device Model Si4532ADY Vishay Siliconix N- and P-Channel 30-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 70551 16-May-04 www.vishay.com 1 SPICE Device Model Si4532ADY Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA VDS = VGS, ID = −250 µA VDS ≥ 5 V, VGS = 10 V VDS ≤ −5 V, VGS = −10 V VGS = 10 V, ID = 4.9 A Drain-Source On-State Resistance a Symbol Test Conditions Simulated Data Measured Data Unit N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 1.8 V 2.2 110 A 62 0.042 0.071 0.057 0.120 9.2 5 0.70 −0.80 0.044 0.062 0.062 0.105 11 S 5 0.80 −0.82 V Ω On-State Drain Current a ID(on) rDS(on) VGS = −10 V, ID = −3.9 A VGS = 4.5 V, ID = 4.1 A VGS = −4.5 V, ID = −3 A Forward Transconductance a gfs VDS = 15 V, ID = 4.9 A VDS = −15 V, ID = −2.5 A IS = 1.7 A, VGS = 0 V IS = −1.7 A, VGS = 0 V Diode Forward Voltage a VSD Dynamicb Total Gate Charge Qg N-Channel VDS = 10 V, VGS = 10 V, ID = 4.9 A P-Channel VDS = −10 V, VGS = −10 V, ID = −3.9 A N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch Turn-On Delay Time td(on) N-Channel VDD =10 V, RL = 10 Ω ID ≅ 1 A, VGEN = 10 V, RG = 6 Ω P-Channel VDD = −10 V, RL = 10 Ω ID ≅ −1 A, VGEN = −10 V, RG = 6 Ω N-Ch P-Ch Rise Time tr N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch Source-Drain Reverse Recovery Time trr IS = 1.7 A, di/dt = 100 A/µs IS = −1.7 A, di/dt = 100 A/µs N-Ch P-Ch 7.4 9.6 1.4 2 1.2 1.9 8 12 10 14 13 16 17 22 24 30 8 10 1.4 2 1.2 1.9 12 8 10 9 23 21 8 10 25 27 Ns Nc Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-Off Delay Time td(off) Fall Time tf Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 70551 16-May-04 SPICE Device Model Si4532ADY Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 70551 16-May-04 www.vishay.com 3 SPICE Device Model Si4532ADY Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 70551 16-May-04