SI4724

Si4724 Vishay Siliconix N-Channel Synchronous MOSFETs With Break-Before-Make DESCRIPTION The Si4724CY N-Channel synchronous MOSFET with break-before-make (BBM) is a high speed driver designed to operate in high frequency DC/DC switchmode power supplies. It’s purpose is to simplify the use of N-Channel MOSFETs in high frequency buck regulators. This device is designed to be used with any single output PWM IC or ASIC to produce a highly efficient low cost synchronous rectifier converter. A synchronous enable pin (disable = low, enable = high) controls the synchronous function for light load conditions. The Si4724CY is packaged in Vishay Siliconix’s high performance LITTLE FOOT® SO-16 package. FEATURES • • • • • • • • • 0 V to 30 V operation Driver impedance-3 Undervoltage lockout Fast switching times 30 V MOSFETs High side: 0.0375 at VDD = 4.5 V Low side: 0.029 at VDD = 4.5 V Switching frequency: 250 kHz to 1 MHz Integrated schottky FUNCTIONAL BLOCK DIAGRAM VDD BOOT D1 Level Shift Undervoltage Lockout VDD IN SYNC EN Q1 S1 D2 Q2 + - S2 VREF GND Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Logic Supply Logic Inputs Drain Voltage Bootstrap Voltage Synchronous pin Voltage TA = 25 °C Continuous Drain Current TA = 70 °C TA = 25 °C TA = 70 °C Maximum Power Dissipation a Symbol VDD VIN VD1 VBOOT VSYNC ID1 ID2 PD Driver MOSFETs TJ, Tstg Steady State 7 - 0.7 to VDD + 0.3 30 VS1 + 7 - 0.7 to VDD + 0.3 5.1 4.09 6.5 5.2 1.2 - 65 to 125 - 65 to 150 Unit V A W °C Operating Junction and Storage Temperature Range Notes: a. Surface mounted on 1" x 1" FR4 board, full copper two sides. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic High Voltage Input Logic Low Voltage Bootstrap Capacitor Ambient Temperature Symbol VD1 VDD VIH VIL CBOOT TA Steady State 0 to 30 4.5 to 5.5 0.7 x VDD to VDD - 0.3 to 0.3 x VDD 0.1 to 1 - 40 to 85 µ °C V Unit THERMAL RESISTANCE RATINGS Parameter Highside Junction-to-Ambienta b Symbol RthJA1 Steady State RthJA2 RthJF1 RthJF2 Typical 85 68 28 19 Maximum 105 85 35 24 Unit Lowside Junction-to-Ambienta Highside Junction-to-Foot (Drain) Lowside Junction-to-Foot (Drain)b °C/W Notes: a. Surface mounted on 1" x 1" FR4 board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix SPECIFICATIONS Parameter Power Supplies Logic Voltage Logic Current Logic Input Logic Input Voltage (VIN) Protection Break-Before-Make Reference Undervoltage Lockout Undervoltage Lockout Hysteresis MOSFET Drivers Driver Impedance MOSFETs Drain-Source Voltage Drain Source On State Resistancea Diode Forward Voltagea VDS RDS(on)1 RDS(on)2 VSD1 VSD2 ID = 250 µA VDD = 4.5 V, ID = 5 A TA = 25 °C IS = 2 A, VGS = 0 Q1 Q2 Q1 Q2 30 30 24 0.7 0.7 37.5 29 1.1 1.1 V m V RDR1 RDR2 VDD = 4.5 V Driver 1 Driver 2 3 2 V VBBM VUVLO VH VDD = 5.5 SYNC = 4.5 3.75 2.4 4 0.4 4.25 V High Low VIH VIL VDD = 4.5 - 40 °C TA  85 °C 3.15 - 0.3 2.3 2.25 0.8 V VDD IDD(EN) IDD(DIS) VDD = 4.5 V, VIN = 4.5 V VDD = 4.5 V, VIN = 0 V 4.5 280 220 5.5 500 500 V µA Symbol Test Conditions Unless Specified TA = 25 °C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 30 V Limits Min. Typ. Max. Unit Dynamicb (Unless Specified-Fs = 250 kHz, VIN = 12 V. VDD = 5 V, I = 5 A, Refer to Switching Test Setup) Turn Off Delay t Source-Drain Reverse Recovery Time-Q2 td(off)1 td(off)2 t1-2 t2-1 tfrr See Timing Diagram VIN to G1 VIN to G2 G 1 to G 2 G 2 to G 1 IF 2.7 A, di/dt = 100 A/µs 28 17 16 38 50 56 40 32 80 80 ns Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 %. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. SCHOTTKY SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Forward Voltage Drop Symbol VF Test Conditions IF = 1 A IF = 1 A, TJ = 125 °C V r = 30 V Maximum Reverse Leakage Current Junction Capacitance Irm CT Vr = 30 V, TJ = 100 °C Vr = - 30 V, TJ = 125 °C V r = 10 V Min Typ 0.47 0.36 0.004 0.7 3 50 Max 0.50 0.42 0.100 10 20 pF mA Unit V Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix APPLICATION CIRCUIT 0 V to 30 V 5V VDD Si4724 CBOOT D1 Q1 MOSFET Drive Circuitry with Break-BeforeMake S1 D2 CBOOT VOUT + SYNC EN DC-DC Controller IN GND Q2 S2 GND GND Power Up Sequence: Ensure VDD is within spec before allowing IN or SYNC EN to be set high. Power Down Sequence: Ensure IN and SYNC EN are low before turning VDD off. Figure 1. PIN CONFIGURATION TRUTH TABLE Sync EN H CLK H L H L Q1 ON OFF ON OFF Q2 OFF ON OFF OFF SO-16 D1 D1 GND IN SYNC EN S2 S2 S2 1 2 3 4 5 6 7 8 Top View 16 15 14 13 12 11 10 9 S1 S1 CBOOT VDD D2 D2 D2 D2 H L L PIN DESCRIPTION Pin Number 1, 2 3 4 5 6, 7, 8 9, 10, 11, 12 13 Symbol D1 GND IN S2 D2 VDD CBOOT S1 Description Highside MOSFET Drain Ground Input Logic Signal Lowside MOSFET Source Lowside MOSFET Drain Logic Supply, decoupling to GND with a cap is strongly recommended. Bootstrap Capacitor for Upper MOSFET Highside MOSFET Source SYNC EN Synchronous Enable Ordering Information: Si4724CY-T1 Si4724CY-T1-E3 (Lead (Pb)-free) 14 15, 16 www.vishay.com 4 Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix TIMING DIAGRAM IN IN G1 G2 G2 G1 td(off) output (S1/D2, not to scale)  t1- 2 td(off)  t2-1 output (S1/D2, not to scale) Figure 2. t1-2 Figure 3. t2-1 SWITCHING TEST SET-UP 12 V C VDD 5V D1 C G1 CBOOT MOSFET Drive Circuitry with Break-BeforeMake S1 G2 D2 S1/D2 CL S2 GND + RL L CBOOT SYNC EN IN Signal Input GND GND Figure 4. Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C unless noted) 80 800 700 r DS(on) - On-Resistance (M) 60 600 C oss (pF) 8 10 500 400 300 ID = 5 A 40 20 200 100 0 0 2 4 6 VGS - Gate-to-Source Voltage (V) 0 0 6 12 18 24 30 VDS - Drain-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage (Q1) 1.6 ID = 5 A VGS = 4.5 V Output Capacitance vs. Drain Voltage (Q1 and Q2) 16 14 12 VIN = 12 V VDD = 5 V DC = 25 % BOOT = 0.1 µF ILOAD = 1 A 1.4 rDS(on) - On-Resistance (Normalized) 1.2 10 1.0 I CC (mA) - 25 0 25 50 75 100 125 150 8 6 4 0.6 2 0.4 - 50 0 0 0.8 200 400 600 800 1000 TA - Ambient Temperature (°C) Frequency (kHz) On-Resistance vs. Ambient Temperature ICC vs. Frequency 350 10 300 I S - Source Current (A) IDDQ at IN = H (A) I DDQ 250 200 IDDQ at IN = L 150 TJ = 150 °C TJ = 25 °C 100 - 50 - 25 0 25 50 75 100 125 150 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 TJ - Junction Temperature (°C) VSD - Source-to-Drain Voltage (V) Input Current vs. Junction Temperature Source-Drain Diode Forward Voltage www.vishay.com 6 Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C unless noted) 50 50 40 40 Power (W) Power (W) 0.1 1 10 Pulse (S) 100 1000 30 30 20 20 10 10 0 0.01 0 0.01 0.1 1 10 Time (sec) 100 1000 Single Pulse Power, Junction-to-Foot (Q1) Single Pulse Power, Junction-to-Ambient (Q1) 50 50 40 40 Power (W) 30 Power (W) 0.1 1 10 Pulse (S) 100 1000 30 20 20 10 10 0 0.01 0 0.01 0.1 1 10 Time (sec) 100 1000 Single Pulse Power, Junction-to-Foot (Q2) 2 1 Single Pulse Power, Junction-to-Ambient (Q2) Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 85 °C/W 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 10 100 600 Square Wave Pulse Duration (sec) Normalized Thermal Transient Impedance, Junction-to-Ambient (Q1) Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si4724 Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C unless noted) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (sec) 10 100 1000 Normalized Thermal Transient Impedance, Junction-to-Foot (Q1) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = R thJA = 68 °C/W 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (sec) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient (Q2) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (sec) 10 100 1000 Normalized Thermal Transient Impedance, Junction-to-Foot (Q2) Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?71863. www.vishay.com 8 Document Number: 71863 S11-1185-Rev. F, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix SOIC (NARROW): 16 LEAD JEDEC Part Number: MS-012 MILLIMETERS Dim A A1 B C D E e H L Min 1.35 0.10 0.38 0.18 9.80 3.80 INCHES Min 0.053 0.004 0.015 0.007 0.385 0.149 Max 1.75 0.20 0.51 0.23 10.00 4.00 Max 0.069 0.008 0.020 0.009 0.393 0.157 16 15 14 13 12 11 10 9 E 1.27 BSC 5.80 0.50 0_ 6.20 0.93 8_ 0.050 BSC 0.228 0.020 0_ 0.244 0.037 8_ 1 2 3 4 5 6 7 8 ECN: S-03946—Rev. F, 09-Jul-01 DWG: 5300 D H C All Leads e B A1 0.101 mm L 0.004 IN Document Number: 71194 02-Jul-01 www.vishay.com 1 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR SO-16 RECOMMENDED MINIMUM PADS FOR SO-16 0.372 (9.449) 0.047 (1.194) (6.248) 0.022 (0.559) 0.050 (1.270) 0.028 (0.711) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE www.vishay.com 24 Document Number: 72608 Revision: 21-Jan-08 (3.861) 0.246 0.152 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1