SI4728CY

Si4728CY Vishay Siliconix N-Channel Synchronous MOSFETs with Break-Before-Make FEATURES D D D D 4.5- to 30-V Operation Driver Impedance—3 W Undervoltage Lockout Fast Switching Times (30 ns typ.) D D D D 30-V MOSFETs High Side: 0.018 W @ VDD = 4.5 V Low Side: 0.0105 W @ VDD = 4.5 V Switching Frequency: 250 kHz to 1 MHz DESCRIPTION The Si4728CY n-channel synchronous MOSFET with break-before-make (BBM) is a high speed driver designed to operate in high frequency dc-dc switchmode power supplies. It’s purpose is to simplify the use of n-channel MOSFETs in high frequency buck regulators. This device is design to be used with any single output PWM IC or ASIC to produce a highly efficient low cost synchronous rectifier converter. A synchronous enable pin (disable = low, enable = high) controls the synchronous function for light load conditions. The Si4728CY is packaged in Vishay Siliconix’s high performance LITTLE FOOTR SO-16 package. FUNCTIONAL BLOCK DIAGRAM 4.5 V to 30 V 5V VDD Si4728 CBOOT D1 Q1 MOSFET Drive Circuitry with Break-BeforeMake S1 D2 CBOOT VOUT + SYNC EN DC-DC Controller IN GND Q2 S2 GND GND Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 1 Si4728CY Vishay Siliconix ABSOLUTE MAXIMUM RATINGS (TA = 25_C UNLESS OTHERWISE NOTED) Parameter Logic Supply Logic Inputs Drain-Source Voltage Bootstrap Voltage Synchronous Pin Voltage Maximum Power Dissipationa Driver Operating Junction and Storage Temperature Range MOSFETs Tj, Tstg Symbol VDD VIN VDS VBOOT VSYNC PD Steady State 7 - 0.7 to VDD + 0.3 - 1.0 to 30 7 - 0.7 to VDD +0.3 4 - 65 to 125 - 65 to 150 Unit V W _C Notes a. Surface mounted on 1” x1” FR4 board, full copper two sides. b. Pulse test: pulse width v300 mS, duty cycle v2%. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING CONDITIONS Parameter Drain Voltage Logic Supply Input Logic High Voltage Input Logic Low Voltage Bootstrap Capacitor Ambient Temperature Symbol VD1 VDD VIH VIL CBOOT TA Steady State 4.5 to 30 4.5 to 5.5 0.7 VDD to VDD VDD Unit V - 0.3 to 0.3 100 n to 1 m - 40 to 85 F _C THERMAL RESISTANCE RATINGS Parameter Highside Junction-to-Ambienta Lowside Junction-to-Ambienta Highside Junction-to-Foot (Drain)b Steady State Symbol RthJA1 RthJA2 RthJF1 RthJF2 Typical 85 68 24 16 Maximum 105 85 30 20 Unit _C/W Lowside Junction-to-Foot (Drain)b Notes a. Surface Mounted on 1” x 1” FR4 Board. b. Junction-to-foot thermal impedance represents the effective thermal impedance of all heat carrying leads in parallel and is intended for use in conjunction with the thermal impedance of the PC board pads to ambient (RthJA = RthJF + RthPCB-A). It can also be used to estimate chip temperature if power dissipation and the lead temperature of a heat carrying (drain) lead is known. www.vishay.com 2 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix SPECIFICATIONS Test Conditions Unless Specified Parameter Power Supplies Logic Voltage Logic Current VDD IDD(EN) IDD(DIS) VDD = 4.5 V, VIN = 4.5 V VDD = 4.5 V, VIN = 0 V 4.5 280 220 5.5 500 500 V mA Limits Min Typ Max Unit Symbol TJ = 25_C 4.5 V < VDD < 5.5 V, 4.5 V < VD1 < 30 V Logic Input High Logic Input Voltage (VIN) Low VIH VIL 3.15 VDD = 4.5 V - 0.3 2.3 2.25 0.8 V Protection Break-Before-Make Reference Undervoltage Lockout Undervoltage Lockout Hysteresis VBBM VUVLO VH VDD = 5.5 V SYNC = 4.5 V 3.75 2.4 4 0.4 4.25 V MOSFET Drivers Driver Impedance RDR1 RDR2 Driver 1 VDD = 4.5 V Driver 2 3.6 2 W MOSFETs Drain-Source Voltage Drain-Source On-State Resistancea Diode Forward Voltagea VDS rDS(on)1 rDS(on)2 VSD1 VSD2 ID = 250 mA VDD = 4.5 V, ID = 10 A TJ = 25_C IS = 2 A, VGS = 0 V Q1 Q2 Q1 Q2 30 13 8 0.7 0.7 18 10.5 1.1 1.1 V V mW Dynamicb (Unless Specified—Fs = 250 kHz, dc = 10%. VDD = 5 V, I = 10 A, Refer to Switching Test Setup) Rise Time trdr1 trdr2 tfdr1 tfdr2 td(off)1 td(off)2 Dt1-2 Dt2-1 tr tf tfr2 10% - 90% 90% - 10% IF 2.7 A, di/dt = 100 A/ms See Timing Diagram Driver 1 10% - 90% Driver 2 Driver 1 90% - 10% Driver 2 VIN to G1 VIN to G2 G1 to G2 G2 to G1 S1/D2 S1/D2 31 23 9 15 50 27 19 38 29 10 50 60 40 20 40 100 60 40 80 60 20 80 ns Fall Time Turn-Off Delay Dt Rise Time Fall Time Source-Drain Reverse Recovery Time—Q2 Notes a. Pulse test: pulse width v300 ms; duty cycle v 2%. b. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 3 Si4728CY Vishay Siliconix DETAILED BLOCK DIAGRAM VDD CBOOT VDC VOUTH Level Shift VS Undervoltage Lockout VDD IN SYNC EN VOUTL S1 D2 Q1 Q2 + GND VBBM FIGURE 1. PIN CONFIGURATION SO-16 D1 D1 GND IN SYNC EN S2 S2 S2 1 2 3 4 5 6 7 8 Top View Order Number: Si4728CY 16 15 14 13 12 11 10 9 S1 S1 CBOOT VDD D2 D2 D2 D2 TRUTH TABLE Sync EN H H L L VIN H L H L Q1 ON OFF ON OFF Q2 OFF ON OFF OFF PIN DESCRIPTION Pin Number 1, 2 3 4 5 6, 7, 8 9, 10, 11, 12 13 14 15, 16 www.vishay.com Symbol D1 GND IN SYNC EN S2 D2 VDD CBOOT S1 Ground Description Highside MOSFET Drain Input Logic Signal Synchronous Enable Lowside MOSFET Source Lowside MOSFET Drain Logic Supply Bootstrap Capacitor For Upper MOSFET Highside MOSFET Source Document Number: 71286 S-03075—Rev. C, 03-Feb-03 4 Si4728CY Vishay Siliconix TIMING DIAGRAM VIN VIN G1 G2 G2 G1 td(off) output (S1/D2, not to scale) dt1- 2 td(off) dt2-1 output (S1/D2, not to scale) FIGURE 2. Dt1-2 FIGURE 3. Dt2-1 SWITCHING TEST SETUP 20 V C VDD 5V D1 C G1 CBOOT MOSFET Drive Circuitry with Break-BeforeMake S1 G2 D2 S1/D2 CL S2 GND + RL L CBOOT SYNC EN IN Signal Input GND GND FIGURE 4. Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 5 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) On-Resistance vs. Gate-to-Source Voltage (Q1) 100 80 On-Resistance vs. Gate-to-Source Voltage (Q2) r DS(on) - On-Resistance (M W ) 80 r DS(on) - On-Resistance (M W ) 60 ID = 10 A 40 60 ID = 10 A 40 20 20 0 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) 0 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) Output Capacitance vs. Drain Voltage (Q1) 2000 3000 1600 2400 C oss (pF) 1200 C oss (pF) Output Capacitance vs. Drain Voltage (Q2) 1800 800 1200 400 600 0 0 6 12 18 24 30 0 0 6 12 18 24 30 VDS - Drain-to-Source Voltage (V) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Junction Temperature 1.6 VGS = 4.5 V ID = 10 A Q2 2.30 Q1 2.25 Input V IH (V) 1.2 2.20 2.15 2.10 0.6 2.05 2.00 - 50 2.35 Input VIH vs. Junction Temperature VDD = 4.5 V r DS(on) - On-Resistance (W ) (Normalized) 1.4 1.0 0.8 0.4 - 50 - 25 0 25 50 75 100 125 150 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (_C) TJ - Junction Temperature (_C) www.vishay.com 6 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Input Current vs. Junction Temperature 350 10 Source-Drain Diode Forward Voltage 300 ( mA) IDDQ @ IN = H 250 I S - Source Current (A) I DDQ 200 IDDQ @ IN = L 150 TJ = 150_C TJ = 25_C 100 - 50 - 25 0 25 50 75 100 125 150 1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 TJ - Junction Temperature (_C) VSD - Source-to-Drain Voltage (V) Single Pulse Power, Junction-to-Foot (Q1) 50 50 Single Pulse Power, Junction-to-Ambient (Q1) 40 40 Power (W) 20 Power (W) 30 30 20 10 10 0 0.01 0.1 1 10 100 1000 0 0.01 0.1 1 10 100 1000 Time (sec) Time (sec) Single Pulse Power, Junction-to-Foot (Q2) 50 50 Single Pulse Power, Junction-to-Ambient (Q2) 40 40 Power (W) 20 Power (W) 30 30 20 10 10 0 0.01 0.1 1 10 100 1000 0 0.01 0.1 1 10 100 1000 Time (sec) Time (sec) Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 7 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Normalized Thermal Transient Impedance, Junction-to-Ambient (Q1) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = 2. Per Unit Base = RthJA = 85_C/W t1 t2 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Normalized Thermal Transient Impedance, Junction-to-Foot (Q1) 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 Square Wave Pulse Duration (sec) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 Normalized Thermal Transient Impedance, Junction-to-Ambient (Q2) 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 68_C/W 3. TJM - TA = PDMZthJA(t) 4. Surface Mounted Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (sec) 10 100 600 www.vishay.com 8 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 Si4728CY Vishay Siliconix TYPICAL CHARACTERISTICS (25_C UNLESS NOTED) Normalized Thermal Transient Impedance, Junction-to-Foot (Q2) 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10 -4 10 -3 10 -2 10 -1 1 10 Document Number: 71286 S-03075—Rev. C, 03-Feb-03 www.vishay.com 9