Si5402BDC
Vishay Siliconix
N-Channel 30-V (D-S) MOSFET
PRODUCT SUMMARY
VDS (V) 30 RDS(on) (Ω) 0.035 at VGS = 10 V 0.042 at VGS = 4.5 V ID (A) 6.7 6.1
FEATURES
• Halogen-free According to IEC 61249-2-21 Available • TrenchFET® Power MOSFET
1206-8 ChipFET®
D 1
D D D D S D D G
Marking Code AD XXX Lot Traceability and Date Code Part # Code
G
Bottom View
S Ordering Information: Si5402BDC-T1-E3 (Lead (Pb)-free) Si5402BDC-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET
ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted´
Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C)a Pulsed Drain Current Continuous Source Current (Diode Conduction)a Maximum Power Dissipationa Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)b, c TA = 25 °C TA = 85 °C TA = 25 °C TA = 85 °C Symbol VDS VGS ID IDM IS PD TJ, Tstg 2.1 2.5 1.3 - 55 to 150 260 6.7 4.8 20 1.1 1.3 0.7 W °C 5s 30 ± 20 4.9 3.5 A Steady State Unit V
THERMAL RESISTANCE RATINGS
Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot (Drain) t≤5s Steady State Steady State Symbol RthJA RthJF Typical 45 80 18 Maximum 50 95 22 °C/W Unit
Notes: a. Surface Mounted on 1" x 1" FR4 board. b. See Reliability Manual for profile. The ChipFET is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 73051 S-83054-Rev. B, 29-Dec-08
www.vishay.com 1
Si5402BDC
Vishay Siliconix
SPECIFICATIONS
Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd Rg td(on) tr td(off) tf trr IF = 1.1 A, dI/dt = 100 A/µs VDD = 15 V, RL = 15 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω f = 1 MHz VDS = 15 V, VGS = 10 V, ID = 4.9 A 10 1.9 1.6 14 10 10 27 10 20 15 15 40 15 60 ns Ω 20 nC
a
Symbol VGS(th) IGSS IDSS ID(on) RDS(on) gfs VSD
Test Conditions VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 30 V, VGS = 0 V VDS = 30 V, VGS = 0 V, TJ = 85 °C VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 4.9 A VGS = 4.5 V, ID = 4.4 A VDS = 10 V, ID = 4.9 A IS = 1.1 A, VGS = 0 V
Min. 1.0
Typ.
Max. 3.0 ± 100 1 5
Unit V nA µA A
20 0.029 0.035 19 0.8 1.2 0.035 0.042
Ω S V
Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS TJ = 25 °C, unless otherwise noted
20 VGS = 10 thru 4 V 16 ID - Drain Current (A) ID - Drain Current (A) 16 20
12
12
8
8 TC = 125 °C 4 25 °C - 55 °C 0 0.0
4 3V 0 0.0
0.5
1.0
1.5
2.0
2.5
3.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
VDS - Drain-to-Source Voltage (V)
VGS - Gate-to-Source Voltage (V)
Output Characteristics
Transfer Characteristics
www.vishay.com 2
Document Number: 73051 S-83054-Rev. B, 29-Dec-08
Si5402BDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.05 800 700 RDS(on) - On-Resistance (Ω) 0.04 C - Capacitance (pF) VGS = 4.5 V 0.03 600 500 400 300 200 0.01 100 0.00 0 4 8 12 16 20 0 0 5 10 15 20 25 30 Coss Crss Ciss
0.02
VGS = 10 V
ID - Drain Current (A)
VDS - Drain-to-Source Voltage (V)
On-Resistance vs. Drain Current
10 ID = 4.9 A VGS - Gate-to-Source Voltage (V) 8 RDS(on) - On-Resistance (Normalized) VDS = 15 V 6 1.4 1.6 ID = 4.9 A
Capacitance
VGS = 10 V 1.2
4
1.0
2
0.8
0 0 2 4 6 8 10 Qg - Total Gate Charge (nC)
0.6 - 50
- 25
0
25
50
75
100
125
150
TJ - Junction Temperature (°C)
Gate Charge
20 TJ = 150 °C 10 IS - Source Current (A) R DS(on) - On-Resistance (Ω) 0.08 0.10
On-Resistance vs. Junction Temperature
ID = 4.9 A
0.06
0.04
TJ = 25 °C
0.02
1 0.0
0.00 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 0 2 4 6 8 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V)
Source-Drain Diode Forward Voltage
On-Resistance vs. Gate-to-Source Voltage
Document Number: 73051 S-83054-Rev. B, 29-Dec-08
www.vishay.com 3
Si5402BDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
0.6 0.4 40 0.2 V GS(th) Variance (V) 0.0 - 0.2 - 0.4 - 0.6 10 - 0.8 - 1.0 - 50 0 10-2 ID = 250 µA Power (W) 30 50
20
- 25
0
25
50
75
100
125
150
10-1
1 Time (s) T
10
100
600
TJ - Temperature (°C)
Threshold Voltage
100 IDM Limited Limited by R DS(on)* 10 I D - Drain Current (A)
Single Pulse Power
P(t) = 0.0001
1
ID(on) Limited
P(t) = 0.001 P(t) = 0.01 P(t) = 0.1 P(t) = 1 P(t) = 10 DC BVDSS Limited
0.1
TA = 25 °C Single Pulse
0.01 0.1
1
10
100
VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified
Safe Operating Area
2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5
0.2
Notes:
0.1 0.1 0.05
t1 PDM
0.02
t2 1. Duty Cycle, D =
2. Per Unit Base = R thJA = 80 °C/W
t1 t2
Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s)
3. T JM - TA = PDMZthJA(t) 4. Surface Mounted
10
100
600
Normalized Thermal Transient Impedance, Junction-to-Ambient
www.vishay.com 4
Document Number: 73051 S-83054-Rev. B, 29-Dec-08
Si5402BDC
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted
2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5
0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) 1 10
Normalized Thermal Transient Impedance, Junction-to-Foot
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73051.
Document Number: 73051 S-83054-Rev. B, 29-Dec-08
www.vishay.com 5
Package Information
Vishay Siliconix
1206-8 ChipFETR
4 D 8 7 6 5 5 4 E1 E 4 1 2 3 4 3 2 1 6 7 8
L
S
e
b
c
x
Backside View
2X 0.10/0.13 R
A C1 DETAIL X NOTES: 1. 2. 3. 4. 5. All dimensions are in millimeaters. Mold gate burrs shall not exceed 0.13 mm per side. Leadframe to molded body offset is horizontal and vertical shall not exceed 0.08 mm. Dimensions exclusive of mold gate burrs. No mold flash allowed on the top and bottom lead surface.
MILLIMETERS Dim A b c c1 D E E1 e L S Min
1.00 0.25 0.1 0 2.95 1.825 1.55 0.28
INCHES Min
0.039 0.010 0.004 0 0.116 0.072 0.061 0.011
Nom
− 0.30 0.15 − 3.05 1.90 1.65 0.65 BSC − 0.55 BSC 5_Nom
Max
1.10 0.35 0.20 0.038 3.10 1.975 1.70 0.42
Nom
− 0.012 0.006 − 0.120 0.075 0.065 0.0256 BSC − 0.022 BSC 5_Nom
Max
0.043 0.014 0.008 0.0015 0.122 0.078 0.067 0.017
ECN: C-03528—Rev. F, 19-Jan-04 DWG: 5547 Document Number: 71151 15-Jan-04 www.vishay.com
1
AN811
Vishay Siliconix
Single-Channel 1206-8 ChipFETr Power MOSFET Recommended Pad Pattern and Thermal Performance
INTRODUCTION
New Vishay Siliconix ChipFETs in the leadless 1206-8 package feature the same outline as popular 1206-8 resistors and capacitors but provide all the performance of true power semiconductor devices. The 1206-8 ChipFET has the same footprint as the body of the LITTLE FOOTR TSOP-6, and can be thought of as a leadless TSOP-6 for purposes of visualizing board area, but its thermal performance bears comparison with the much larger SO-8. This technical note discusses the single-channel ChipFET 1206-8 pin-out, package outline, pad patterns, evaluation board layout, and thermal performance.
28 mil 80 mil
68 mil
PIN-OUT
Figure 1 shows the pin-out description and Pin 1 identification for the single-channel 1206-8 ChipFET device. The pin-out is similar to the TSOP-6 configuration, with two additional drain pins to enhance power dissipation and thermal performance. The legs of the device are very short, again helping to reduce the thermal path to the external heatsink/pcb and allowing a larger die to be fitted in the device if necessary.
Single 1206-8 ChipFET
1
D D D D S D D G
26 mil
FIGURE 2. Footprint With Copper Spreading
The pad pattern with copper spreading shown in Figure 2 improves the thermal area of the drain connections (pins 1,2,3,6.7,8) while remaining within the confines of the basic footprint. The drain copper area is 0.0054 sq. in. or 3.51 sq. mm). This will assist the power dissipation path away from the device (through the copper leadframe) and into the board and exterior chassis (if applicable) for the single device. The addition of a further copper area and/or the addition of vias to other board layers will enhance the performance still further. An example of this method is implemented on the Vishay Siliconix Evaluation Board described in the next section (Figure 3).
THE VISHAY SILICONIX EVALUATION BOARD FOR THE SINGLE 1206-8
The ChipFET 1206-08 evaluation board measures 0.6 in by 0.5 in. Its copper pad pattern consists of an increased pad area around the six drain leads on the top-side—approximately 0.0482 sq. in. 31.1 sq. mm—and vias added through to the underside of the board, again with a maximized copper pad area of approximately the board-size dimensions. The outer package outline is for the 8-pin DIP, which will allow test sockets to be used to assist in testing. The thermal performance of the 1206-8 on this board has been measured with the results following on the next page. The testing included comparison with the minimum recommended footprint on the evaluation board-size pcb and the industry standard one-inch square FR4 pcb with copper on both sides of the board.
www.vishay.com
Bottom View
FIGURE 1.
For package dimensions see the 1206-8 ChipFET package outline drawing (http://www.vishay.com/doc?71151).
BASIC PAD PATTERNS
The basic pad layout with dimensions is shown in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286). This is sufficient for low power dissipation MOSFET applications, but power semiconductor performance requires a greater copper pad area, particularly for the drain leads.
Document Number: 71126 12-Dec-03
1
AN811
Vishay Siliconix
Front of Board Back of Board
ChipFETr
vishay.com
FIGURE 3.
THERMAL PERFORMANCE
Junction-to-Foot Thermal Resistance (the Package Performance) Thermal performance for the 1206-8 ChipFET measured as junction-to-foot thermal resistance is 15_C/W typical, 20_C/W maximum for the single device. The “foot” is the drain lead of the device as it connects with the body. This is identical to the SO-8 package RQjf performance, a feat made possible by shortening the leads to the point where they become only a small part of the total footprint area. Junction-to-Ambient Thermal Resistance (dependent on pcb size) The typical RQja for the single-channel 1206-8 ChipFET is 80_C/W steady state, compared with 68_C/W for the SO-8. Maximum ratings are 95_C/W for the 1206-8 versus 80_C/W for the SO-8. Testing To aid comparison further, Figure 4 illustrates ChipFET 1206-8 thermal performance on two different board sizes and three different pad patterns. The results display the thermal performance out to steady state and produce a graphic account of how an increased copper pad area for the drain connections can enhance thermal performance. The measured steady state values of RQja for the single 1206-8 ChipFET are : 1) Minimum recommended pad pattern (see Figure 2) on the evaluation board size of 0.5 in x 0.6 in. 2) The evaluation board with the pad pattern described on Figure 3. 3) Industry standard 1” square pcb with maximum copper both sides.
www.vishay.com
The results show that a major reduction can be made in the thermal resistance by increasing the copper drain area. In this example, a 45_C/W reduction was achieved without having to increase the size of the board. If increasing board size is an option, a further 33_C/W reduction was obtained by maximizing the copper from the drain on the larger 1” square pcb.
160
Thermal Resistance (C/W)
120 Min. Footprint
Single EVB
80
40
1” Square PCB
0 10-5 10-4 10-3 10-2 10-1 1 10 100 1000 Time (Secs)
FIGURE 4. Single 1206−8 ChipFET
SUMMARY
The thermal results for the single-channel 1206-8 ChipFET package display similar power dissipation performance to the SO-8 with a footprint reduction of 80%. Careful design of the package has allowed for this performance to be achieved. The short leads allow the die size to be maximized and thermal resistance to be reduced within the confines of the TSOP-6 body size.
156_C/W
111_C/W 78_C/W
ASSOCIATED DOCUMENT
1206-8 ChipFET Dual Thermal performance, AN812 (http://www.vishay.com/doc?71127).
Document Number: 71126 12-Dec-03
2
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR 1206-8 ChipFET®
0.093 (2.357)
(2.032)
0.026 (0.650)
0.016 (0.406)
0.010 (0.244)
Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index
Return to Index
APPLICATION NOTE
www.vishay.com 2
(0.559)
0.022
(0.914)
0.080
0.036
Document Number: 72593 Revision: 21-Jan-08
Legal Disclaimer Notice
Vishay
Disclaimer
ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. Statements regarding the suitability of products for certain types of applications are based on Vishay’s knowledge of typical requirements that are often placed on Vishay products in generic applications. Such statements are not binding statements about the suitability of products for a particular application. It is the customer’s responsibility to validate that a particular product with the properties described in the product specification is suitable for use in a particular application. Parameters provided in datasheets and/or specifications may vary in different applications and performance may vary over time. All operating parameters, including typical parameters, must be validated for each customer application by the customer’s technical experts. Product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein. Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 11-Mar-11
www.vishay.com 1
