SI5509DC

SPICE Device Model Si5509DC Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 4.5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74166 S-60411Rev. A, 20-Mar-06 www.vishay.com 1 SPICE Device Model Si5509DC Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 µA VDS = VGS, ID = −250 µA VDS ≤ 5 V, VGS = 4.5 V VDS ≤ −5 V, VGS = −4.5 V VGS = 4.5 V, ID = 5 A Drain-Source On-State Resistancea rDS(on) VGS = −4.5 V, ID = −3.9 A VGS = 2.5 V, ID = 3.9 A VGS = −2.5 V, ID = −2.9 A Forward Transconductancea gfs VDS = 10 V, ID = 5 A VDS = − 10 V, ID = −3.9 A IS = 2.4 A, VGS = 0 V IS = −1.5 A, VGS = 0 V N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 1.2 1.1 46 40 0.041 0.066 0.072 0.111 12 12 0.73 0.80 0.043 0.074 0.068 0.128 10.4 8.2 0.80 - 0.80 S Ω V Symbol Test Condition Simulated Data Measured Data Unit On-State Drain Currenta ID(on) A Diode Forward Voltagea VSD V Dynamicb Input Capacitance Ciss N-Channel VDS = 10 V, VGS = 0 V, f = 1 MHz P-Channel VDS = − 10 V, VGS = 0 V, f = 1 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch VDS = 10V, VGS = 5V, ID = 4 A Total Gate Charge Qg VDS = −10V, VGS = −5V, ID = −3.9 A N-Ch P-Ch N-Ch N-Channel VDS = 10 V, VGS = 4.5V, ID = 4 A P-Channel VDS = −10V, VGS = −4.5V, ID = −3.9 A P-Ch N-Ch P-Ch N-Ch P-Ch 506 377 80 92 28 61 4.2 3.6 3.8 3.3 0.9 0.7 0.95 1.25 455 300 85 95 50 65 4.4 4.1 3.8 3.9 0.9 0.7 0.95 1.25 nC pF Output Capacitance Coss Reverse Transfer Capacitance Crss Gate-Source Charge Qgs Gate-Source Charge Qgs Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74166 S-60411Rev. A, 20-Mar-06 SPICE Device Model Si5509DC Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 74166 S-60411Rev. A, 20-Mar-06 www.vishay.com 3 SPICE Device Model Si5509DC Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 74166 S-60411Rev. A, 20-Mar-06