SI5517DU

SPICE Device Model Si5517DU Vishay Siliconix N- and P-Channel 20-V (D-S) MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 10-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 www.vishay.com 1 SPICE Device Model Si5517DU Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA VDS = VGS, ID = −250 μA VDS < 5 V, VGS = 4.5 V VDS < −5 V, VGS = −4.5 V VGS = 4.5 V, ID = 4.4 A VGS = −4.5 V, ID = −3.3 A Drain-Source On-State Resistancea rDS(on) VGS = 2.5 V, ID = 4.1 A VGS = −2.5 V, ID = −2.8 A VGS = 1.8 V, ID = 1.8 A VGS = −1.8 V, ID = −0.76 A Forward Transconductancea gfs VDS = 10 V, ID = 4.4 A VDS = −10 V, ID = −3.3 A IS = 1.2 A IS = −1A N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 0.50 0.80 117 60 0.032 0.063 0.038 0.082 0.046 0.107 23 11 0.72 0.78 0.032 0.060 0.037 0.083 0.046 0.108 22 9 0.80 - 080 V S Ω A Symbol Test Condition Simulated Data Measured Data Unit On-State Drain Currenta ID(on) Diode Forward Voltagea VSD Dynamicb Input Capacitance Ciss N-Channel VDS = 10 V, VGS = 0 V, f = 1 MHz P-Channel VDS = −10 V, VGS = 0 V, f = 1 MHz N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch VDS = 10 V, VGS = 8 V, ID = 4.4 A Total Gate Charge Qg VDS = − 10 V, VGS = −8 V, ID = −4.6 A N-Ch P-Ch N-Ch N-Channel VDS = 10 V, VGS = 4.5 V, ID = 4.4 A P-Channel VDS = −10 V, VGS = −4.5 V, ID = −1.8 A P-Ch N-Ch P-Ch N-Ch P-Ch Notes a. Pulse test; pulse width ≤ 300 μs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. 605 589 96 103 62 57 8.1 8.4 5 5 0.91 0.75 0.70 1.5 520 455 100 105 60 65 10.5 9.1 6 5.5 0.91 0.75 0.70 1.5 nC pF Output Capacitance Coss Reverse Transfer Capacitance Crss Gate-Source Charge Qgs Gate-Source Charge Qgs www.vishay.com 2 Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 SPICE Device Model Si5517DU Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-Channel MOSFET Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05 www.vishay.com 3 SPICE Device Model Si5517DU Vishay Siliconix P-Channel MOSFET www.vishay.com 4 Document Number: 74130 S-52018⎯Rev. A, 03-Oct-05