SI6801DQ

Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model Si6801DQ Vishay Siliconix N- and P-Channel Dual Enhancement-Mode MOSFET CHARACTERISTICS • N- and P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n- and p-channel vertical DMOS. The model subcircuit is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC a This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71023 22-May-04 www.vishay.com 1 Click Here & Upgrade PDF Complete SPICE Device Model Si6801DQ Vishay Siliconix Documents Parameter Static Gate Threshold Voltage Expanded Features Unlimited Pages SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Symbol Test Conditions VDS = V, VGS, ID = 250 µA VDS = V, VGS, ID = −250 µA VDS 5 V, VGS = 4.5 V VDS = −5 V, VGS = −4.5 V VGS = 4.5 V, ID = 1.9 A Drain-Source On-State Resistance a Typical Unit N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch 1.02 V 1.15 23 A 18 0.112 0.154 0.149 0.217 5 S 4.1 0.77 −0.77 V Ω VGS(th) On-State Drain Current a ID(on) rDS(on) VGS = −4.5 V, ID = −1.7 A VGS = 3 V, ID = 1.5 A VGS = −3 V, ID = −1.3 A Forward Transconductance a gfs VDS = 15 V, ID = 1.9 A VDS = −15 V, ID = −1.7 A IS = 1 A, VGS = 0 V IS = −1 V, VGS = 0 V Diode Forward Voltage a VSD Dynamicb Total Gate Charge Qg N-Channel VDS = 3.5 V, VGS = 4.5 V, ID = 0.3 A P-Channel VDS = −3.5 V, VGS = −4.5 V, ID = −0.3 A N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch Turn-On Delay Time td(on) N-Channel VDD = 3.5 V, RL = 11.5 Ω ID ≅ 0.3 A, VGEN = 4.5 V, RG = 6 Ω P-Channel VDD = −3.5 V, RL = 11.5 Ω ID ≅ −0.3 A, VGEN = −4.5 V, RG = 6 Ω N-Ch P-Ch Rise Time tr N-Ch P-Ch N-Ch P-Ch N-Ch P-Ch Source-Drain Reverse Recovery Time trr IF = 1 A, di/dt = 100 A/µs IF = −1 A, di/dt = 100 A/µs N-Ch P-Ch 1.6 3 0.41 0.76 0.26 0.70 5.2 6 6.2 10 9 ns 11 15 22 31 30 nC Gate-Source Charge Qgs Gate-Drain Charge Qgd Turn-Off Delay Time td(off) Fall Time tf Notes a. Guaranteed by design, not subject to production testing. b. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. www.vishay.com 2 Document Number: 71023 22-May-04 Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model Si6801DQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) N-CHANNEL MOSFET Document Number: 71023 22-May-04 www.vishay.com 3 Click Here & Upgrade PDF Complete SPICE Device Model Si6801DQ Vishay Siliconix Documents P-CHANNEL MOSFET Expanded Features Unlimited Pages www.vishay.com 4 Document Number: 71023 22-May-04