SI6933DQ

SPICE Device Model Si6933DQ Vishay Siliconix Dual P-Channel Enhancement-Mode MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit mode is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71734 12-Oct-01 www.vishay.com 1 SPICE Device Model Si6933DQ Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 2.13 132 0.034 0.054 9.6 - 0.78 Measured Data Unit VGS(th) ID(on) a VDS = VGS, ID = − 250µA VDS > − 5V, VGS = − 10V VGS = − 10V, ID = − 3.5A VGS = − 4.5V, ID = − 2.5A VDS = − 15V, ID = − 3.5A IS = − 1.25A, VGS = 0V V A 0.035 0.062 7.2 - 0.77 Ω S V Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltagea a rDS(on) gfs VSD Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = − 1.25A, di/dt = 100A/µs VDD = − 15V, RL = 15Ω ID ≅ − 1A, VGEN = − 10V, RG = 6Ω VDS = − 15V, VGS = − 10V, ID = − 3.5A 18 4.4 3.1 14 7.8 21 11 30 17 4.4 3.1 13 10 33 10 30 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71734 12-Oct-01 SPICE Device Model Si6933DQ Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71734 12-Oct-01 www.vishay.com 3