SI7216DN-T1-E3

Si7216DN Vishay Siliconix Dual N-Channel 40-V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 40 RDS(on) () 0.032 at VGS = 10 V 0.039 at VGS = 4.5 V ID (A) 6e 5e Qg (Typ.) 5.5 nC • Halogen-free According to IEC 61249-2-21 Available • TrenchFET® Power MOSFET • Low Thermal Resistance PowerPAK® Package with Small Size and Low 1.07 mm Profile • 100 % Rg and UIS tested • Compliant to RoHS Directive 2002/95/EC APPLICATIONS • Primary Side Switch • Synchronus Rectification PowerPAK 1212-8 3.30 mm S1 D1 3.30 mm G1 D2 1 2 S2 3 4 D1 G2 8 7 D1 D2 G1 6 5 G2 D2 Bottom View S1 S2 N-Channel MOSFET Ordering Information: Si7216DN-T1-E3 (Lead (Pb)-free) Si7216DN-T1-GE3 (Lead (Pb)-free and Halogen-free) N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS (TA = 25 °C, unless otherwise noted) Parameter Drain-Source Voltage Gate-Source Voltage TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C TC = 25 °C TA = 25 °C L = 0.1 mH TC = 25 °C TC = 70 °C TA = 25 °C TA = 70 °C Symbol VDS VGS ID IDM IS IAS EAS PD TJ, Tstg Limit 40 ± 20 6 5e 6.5a, b 5.2a, b 20 6e 2a, b 10 5 20.8 13.3 2.5a, b 1.6a, b - 50 to 150 260 e Unit V Continuous Drain Current (TJ = 150 °C) Pulsed Drain Current Continuous Source-Drain Diode Current Avalanche Current Single-Pulse Avalanche Energy A mJ Maximum Power Dissipation W Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature)c, d °C Notes: a. Surface Mounted on 1" x 1" FR4 board. b. t = 10 s. c. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequade bottom side solder interconnection. d. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. e. Package limited. Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 www.vishay.com 1 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter t  10 s Maximum Junction-to-Ambienta, b Maximum Junction-to-Case (Drain) Steady State Notes: a. Surface mounted on 1" x 1" FR4 board. b. Maximum under steady state conditions is 94 °C/W. Symbol RthJA RthJC Typical 38 4.5 Maximum 50 6 Unit °C/W SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Dynamic b Symbol VDS VDS/TJ VGS(th)/TJ VGS(th) IGSS IDSS ID(on) RDS(on) gfs Ciss Coss Crss Qg Qgs Qgd Rg td(on) tr td(off) tf td(on) tr td(off) tf Test Conditions VGS = 0, ID = 250 µA ID = 250 µA VDS = VGS , ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 40 V, VGS = 0 V VDS = 40 V, VGS = 0 V, TJ = 55 °C VDS 5 V, VGS = 10 V VGS 10 V, ID = 5 A VGS 4.5 V, ID = 4 A VDS = 15 V, ID = 5 A Min. 40 Typ. Max. Unit V 43 - 5.8 1 3 ± 100 1 10 10 0.025 0.031 25 0.032 0.039 mV/°C V nA µA A  S Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time 670 VDS = 20 V, VGS = 0 V, f = 1 MHz VDS = 20 V, VGS = 10 V, ID = 5 A VDS = 20 V, VGS = 4.5 V, ID = 5 A f = 1 MHz VDD = 20 V, RL = 4  ID  5 A, VGEN = 4.5 V, Rg = 1  90 50 12.5 5.5 2 2 3.4 16 142 16 7 9 VDD = 20 V, RL = 4  ID  5 A, VGEN = 10 V, Rg = 1  57 19 5 5.1 25 215 25 12 15 90 30 10 ns  19 8.5 nC pF www.vishay.com 2 Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) Parameter Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Current Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Fall Time Reverse Recovery Rise Time a Symbol IS ISM VSD trr Qrr ta tb Test Conditions TC = 25 °C IS = 2 A IF = 3.2 A, dI/dt = 100 A/µs, TJ = 25 °C Min. Typ. Max. 6 20 Unit A V ns nC ns 0.8 50 40 35 15 1.2 75 60 Notes: a. Pulse test; pulse width  300 µs, duty cycle  2 % b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 www.vishay.com 3 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 20 VGS = 10 thru 5 V 16 4V 2.0 1.6 I D - Drain Current (A) I D - Drain Current (A) 12 1.2 TC = 125 °C 0.8 8 4 3V 0 0.0 0.4 25 °C - 55 °C 0.0 0.3 0.6 0.9 1.2 1.5 0 1 2 3 4 5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics 0.05 1000 Transfer Characteristics 800 R DS(on) - On-Resistance (Ω) 0.04 C - Capacitance (pF) Ciss 600 VGS = 4.5 V 0.03 VGS = 10 V 400 200 Coss 0 0 6 12 18 24 30 0 Crss 8 16 24 32 40 0.02 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current and Gate Voltage 10 ID = 5 A 1.8 ID = 5 A Capacitance VGS = 10 V VGS - Gate-to-Source Voltage (V) VDS = 20 V 6 (Normalized) VDS = 40 V R DS(on) - On-Resistance 8 1.5 VGS = 4.5 V 1.2 VDS = 30 V 4 0.9 2 0 0 3 6 9 12 15 0.6 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature www.vishay.com 4 Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 100 0.20 10 1 R DS(on) - On-Resistance (Ω) I S - Source Current (A) 150 °C 0.16 0.12 0.1 25 C 0.01 0.08 125 °C 0.04 25 °C 0.001 0 0.2 0.4 0.6 0.8 1.0 1.2 0.00 0 1 2 3 4 5 6 7 8 9 10 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Source-Drain Diode Forward Voltage 0.4 ID = 250 µA 0.2 On-Resistance vs. Gate-to-Source Voltage 50 40 ID = 5 mA Power (W) - 25 0 25 50 75 100 125 150 VGS(th) Variance (V) 0 30 - 0.2 20 - 0.4 - 0.6 10 - 0.8 - 50 0 0.001 0.01 0.1 1 Time (s) 10 100 1000 TJ - Temperature (°C) Threshold Voltage 100 Limited by RDS(on)* 10 Single Pulse Power, Junction-to-Ambient 1 ms I D - Drain Current (A) 1 10 ms 0.1 TA = 25 °C Single Pulse 0.1 1 10 100 ms 1s 10 s DC 0.01 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum VGS at which RDS(on) is specified Safe Operating Area, Junction-to-Ambient Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 www.vishay.com 5 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 65 52 I D - Drain Current (A) 39 26 13 Package Limited 0 0 25 C 50 75 100 125 150 T - Case Temperature (°C) Current Derating* 25 1.8 20 1.5 1.2 Power (W) Power (W) 15 0.9 10 0.6 5 0.3 0 0 25 50 75 100 125 150 0.0 0 25 50 75 100 125 150 TC - Case Temperature (°C) TC - Case Temperature (°C) Power, Junction-to-Case Power, Junction-to-Ambient * The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-case thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. www.vishay.com 6 Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Si7216DN Vishay Siliconix TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 Notes: PDM t1 0.1 0.05 0.02 t2 1. Duty Cycle, D = t1 t2 2. Per Unit Base = RthJA = 65 C/W 3. TJM - TA = PDMZthJA(t) Single Pulse 0.01 10 -4 4. Surface Mounted 10 -3 10 -2 10 -1 1 Square Wave Pulse Duration (s) 10 100 1000 Normalized Thermal Transient Impedance, Junction-to-Ambient 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Case Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73771. Document Number: 73771 S11-1142-Rev. C, 13-Jun-11 www.vishay.com 7 This document is subject to change without notice. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix PowerPAK® 1212-8, (SINGLE/DUAL) W θ 1 8 M D4 H E2 E4 K L 1 Z D1 D2 2 D5 3 4 D 2 4 5 L1 θ θ θ e E3 A1 Backside View of Single Pad H H D2 D3(2x) D4 E2 E4 K L c 2 E1 E Notes: 1. Inch will govern 2 Dimensions exclusive of mold gate burrs Detail Z A 1 D1 2 D5 K1 3 4 b D2 3. Dimensions exclusive of mold flash and cutting burrs E3 Backside View of Dual Pad MILLIMETERS DIM. A A1 b c D D1 D2 D3 D4 D5 E E1 E2 E3 E4 e K K1 H L L1 θ W M ECN: S10-0951-Rev. J, 03-May-10 DWG: 5882 0.35 0.30 0.30 0.06 0° 0.15 3.20 2.95 1.47 1.75 MIN. 0.97 0.00 0.23 0.23 3.20 2.95 1.98 0.48 NOM. 1.04 0.30 0.28 3.30 3.05 2.11 0.47 TYP. 2.3 TYP. 3.30 3.05 1.60 1.85 0.34 TYP. 0.65 BSC 0.86 TYP. 0.41 0.43 0.13 0.25 0.125 TYP. 0.51 0.56 0.20 12° 0.36 0.014 0.012 0.012 0.002 0° 0.006 3.40 3.15 1.73 1.98 0.126 0.116 0.058 0.069 MAX. 1.12 0.05 0.41 0.33 3.40 3.15 2.24 0.89 MIN. 0.038 0.000 0.009 0.009 0.126 0.116 0.078 0.019 INCHES NOM. 0.041 0.012 0.011 0.130 0.120 0.083 0.0185 TYP. 0.090 TYP. 0.130 0.120 0.063 0.073 0.013 TYP. 0.026 BSC 0.034 TYP. 0.016 0.017 0.005 0.010 0.005 TYP. 0.020 0.022 0.008 12° 0.014 0.134 0.124 0.068 0.078 MAX. 0.044 0.002 0.016 0.013 0.134 0.124 0.088 0.035 Document Number: 71656 Revison: 03-May-10 www.vishay.com 1 b AN822 Vishay Siliconix PowerPAK® 1212 Mounting and Thermal Considerations Johnson Zhao MOSFETs for switching applications are now available with die on resistances around 1 mΩ and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed. THE PowerPAK PACKAGE The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”) The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option. Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints. PowerPAK 1212 SINGLE MOUNTING To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. Figure 1. PowerPAK 1212 Devices Document Number 71681 03-Mar-06 www.vishay.com 1 AN822 Vishay Siliconix PowerPAK 1212 DUAL To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257. Ramp-Up Rate Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature + 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C 20 - 40 Seconds + 6 °C/Second Maximum REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera- Time at Maximum Temperature Ramp-Down Rate Figure 2. Solder Reflow Temperature Profile 10 s (max) 210 - 220 °C 3 ° C/s (max) 183 °C 140 - 170 °C 50 s (max) 3° C/s (max) 60 s (min) Pre-Heating Zone Reflow Zone 4 ° C/s (max) Maximum peak temperature at 240 °C is allowed. Figure 3. Solder Reflow Temperatures and Time Durations www.vishay.com 2 Document Number 71681 03-Mar-06 AN822 Vishay Siliconix TABLE 1: EQIVALENT STEADY STATE PERFORMANCE Package Configuration Thermal Resiatance RthJC(C/W) 20 SO-8 Single Dual 40 TSSOP-8 Single 52 Dual 83 TSOP-8 Single 40 Dual 90 PPAK 1212 Single 2.4 Dual 5.5 PPAK SO-8 Single 1.8 Dual 5.5 PowerPAK 1212 49.8 °C Standard SO-8 85 °C Standard TSSOP-8 149 °C TSOP-6 125 °C 2.4 °C/W PC Board at 45 °C 20 °C/W 52 °C/W 40 °C/W Figure 4. Temperature of Devices on a PC Board THERMAL PERFORMANCE Introduction A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance. By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %. Spreading Copper Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. Document Number 71681 03-Mar-06 www.vishay.com 3 AN822 Vishay Siliconix 105 Spreading Copper (sq. in.) 95 110 85 RthJA (°C/W) RthJ A (°C/W) 100 90 80 50 % 70 50 % 0% 45 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 50 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 60 0% 100 % 130 120 Spreading Copper (sq. in.) 75 65 100 % 55 Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance CONCLUSIONS As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package. The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages. www.vishay.com 4 Document Number 71681 03-Mar-06 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Dual 0.152 (3.860) 0.152 (3.860) 0.039 0.039 (0.990) (0.990) 0.016 (0.405) 0.016 (0.405) 0.039 (0.990) 0.010 (0.225) 0.068 0.068 (1.725) (1.725) 0.010 (0.255) (2.235) 0.026 (0.660) 0.026 (0.660) 0.025 (0.635) 0.025 (0.635) 0.039 (0.990) 0.030 (0.760) 0.030 (0.760) Recommended Minimum PADs for PowerPAK 1212-8 Dual Dimensions in Inches/(mm) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE www.vishay.com 1 Document Number: 72598 Revision: 14-Apr-08 (2.390) 0.088 0.094 0.094 (2.390) Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. To the maximum extent permitted by applicable law, Vishay disclaims (i) any and all liability arising out of the application or use of any product, (ii) any and all liability, including without limitation special, consequential or incidental damages, and (iii) any and all implied warranties, including warranties of fitness for particular purpose, non-infringement and merchantability. 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Except as expressly indicated in writing, Vishay products are not designed for use in medical, life-saving, or life-sustaining applications or for any other application in which the failure of the Vishay product could result in personal injury or death. Customers using or selling Vishay products not expressly indicated for use in such applications do so at their own risk and agree to fully indemnify and hold Vishay and its distributors harmless from and against any and all claims, liabilities, expenses and damages arising or resulting in connection with such use or sale, including attorneys fees, even if such claim alleges that Vishay or its distributor was negligent regarding the design or manufacture of the part. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1