SI7220DN

Si7220DN Vishay Siliconix Dual N-Channel 60-V (D-S) MOSFET PRODUCT SUMMARY VDS (V) 60 RDS(on) (Ω) 0.060 at VGS = 10 V 0.075 at VGS = 4.5 V ID (A) 4.8 4.3 Qg (Typ.) 13 FEATURES • Halogen-free According to IEC 61249-2-21 Available • TrenchFET® Power MOSFET • New Low Thermal Resistance PowerPAK® Package, 1/3 the Space of An SO-8 While Thermally Comparable APPLICATIONS PowerPAK 1212-8 • Synchronous Rectification • Primary Side Switch 3.30 mm D1 D2 3.30 mm S1 1 2 G1 S2 3 4 D1 G2 8 7 D1 D2 G1 6 5 D2 G2 Bottom View S1 N-Channel MOSFET S2 N-Channel MOSFET Ordering Information: Si7220DN-T1-E3 (Lead (Pb)-free) Si7220DN-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage Continuous Drain Current (TJ = 150 °C)a Pulsed Drain Current Avalanche Current Single Avalanche Energy Continuous Source Current (Diode Conduction) Maximum Power Dissipationa Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) b, c a Symbol VDS VGS TA = 25 °C TA = 70 °C ID IDM L = 0 1 mH IAS EAS IS TA = 25 °C TA = 70 °C PD TJ, Tstg 10 s 60 Steady State ± 20 Unit V 4.8 3.8 20 11 6.1 2.2 2.6 1.4 - 55 to 150 260 3.4 2.7 A mJ 1.1 1.3 0.69 A W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Case (Drain) t ≤ 10 s Steady State Steady State Symbol RthJA RthJC Typical 38 77 4.3 Maximum 48 94 5.4 °C/W Unit Notes: a. Surface Mounted on 1" x 1" FR4 board. b. See Solder Profile (www.vishay.com/ppg?73257). The PowerPAK 1212-8 is a leadless package. The end of the lead terminal is exposed copper (not plated) as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to ensure adequate bottom side solder interconnection. c. Rework Conditions: manual soldering with a soldering iron is not recommended for leadless components. Document Number: 73117 S-83052-Rev. C, 29-Dec-08 www.vishay.com 1 Si7220DN Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Static Gate Threshold Voltage Gate-Body Leakage Zero Gate Voltage Drain Current On-State Drain Currenta Drain-Source On-State Resistancea Forward Transconductancea Diode Forward Voltage Dynamicb Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd Rg td(on) tr td(off) tf trr IF = 2.2 A, dI/dt = 100 A/µs VDD = 30 V, RL = 30 Ω ID ≅ 1 A, VGEN = 10 V, Rg = 6 Ω f = 1 MHz VDS = 30 V, VGS = 10 V, ID = 4.8 A 13 2.3 2.6 2 10 10 20 10 30 15 15 30 15 60 ns Ω 20 nC a Symbol VGS(th) IGSS IDSS ID(on) RDS(on) gfs VSD Test Conditions VDS = VGS, ID = 250 µA VDS = 0 V, VGS = ± 20 V VDS = 60 V, VGS = 0 V VDS = 60 V, VGS = 0 V, TJ = 85 °C VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 4.8 A VGS = 4.5 V, ID = 4.3 A VDS = 10 V, ID = 4.8 A IS = 2.2 A, VGS = 0 V Min. 1 Typ. Max. 3 ± 100 1 5 Unit V nA µA A 20 0.048 0.061 15 0.8 1.2 0.060 0.075 Ω S V Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 20 VGS = 10 thru 5 V 16 I D - Drain Current (A) I D - Drain Current (A) 4V 16 20 12 12 8 8 TC = 125 °C 4 25 °C - 55 °C 0 0.0 4 3V 0 0 1 2 3 4 5 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics www.vishay.com 2 Document Number: 73117 S-83052-Rev. C, 29-Dec-08 Si7220DN Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.10 1000 R DS(on) - On-Resistance (Ω) 0.08 C - Capacitance (pF) 800 Ciss 600 0.06 VGS = 4.5 V VGS = 10 V 0.04 400 0.02 200 Crss Coss 0.00 0 4 8 12 16 20 0 0 10 20 30 40 50 60 ID - Drain Current (A) VDS - Drain-to-Source Voltage (V) On-Resistance vs. Drain Current 10 VGS - Gate-to-Source Voltage (V) VDS = 30 V ID = 4.8 A 8 R DS(on) - On-Resistance (Normalized) 1.6 1.4 1.2 1.0 0.8 0 0 3 6 9 12 15 Qg - Total Gate Charge (nC) 0.6 - 50 2.0 1.8 VGS = 10 V ID = 4.8 A Capacitance 6 4 2 - 25 0 25 50 75 100 125 150 TJ - Junction Temperature (°C) Gate Charge 20 TJ = 150 °C R DS(on) - On-Resistance (Ω) 10 I S - Source Current (A) 0.12 On-Resistance vs. Junction Temperature 0.10 0.08 ID = 4.8 A 0.06 0.04 TJ = 25 °C 1 0.0 0.02 0.00 0.2 0.4 0.6 0.8 1.0 1.2 1.4 0 2 4 6 8 10 VGS - Gate-to-Source Voltage (V) VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage On-Resistance vs. Gate-to-Source Voltage Document Number: 73117 S-83052-Rev. C, 29-Dec-08 www.vishay.com 3 Si7220DN Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.6 0.4 40 0.2 V GS(th) Variance (V) 0.0 - 0.2 - 0.4 - 0.6 10 - 0.8 - 1.0 - 50 0 0.001 ID = 250 µA Power (W) 30 50 20 - 25 0 25 50 75 100 125 150 0.01 0.1 1 Time (s) 10 100 600 TJ - Temperature (°C) Threshold Voltage 100 Limited by R DS(on)* 10 I D - Drain Current (A) Single Pulse Power IDM Limited P(t) = 0.0001 1 ID(on) Limited P(t) = 0.001 P(t) = 0.01 P(t) = 0.1 TA = 25 °C Single Pulse BVDSS Limited P(t) = 1 P(t) = 10 DC 0.1 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, Junction-to-Ambient 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 t2 1. Duty Cycle, D = 2. Per Unit Base = R thJA = 77 °C/W t1 t2 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) 3. T JM - TA = PDMZthJA(t) 4. Surface Mounted 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient www.vishay.com 4 Document Number: 73117 S-83052-Rev. C, 29-Dec-08 Si7220DN Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 2 1 Normalized Effective Transient Thermal Impedance Duty Cycle = 0.5 0.2 0.1 0.1 0.02 Single Pulse 0.05 0.01 10-4 10-3 10-2 Square Wave Pulse Duration (s) 10-1 1 Normalized Thermal Transient Impedance, Junction-to-Case Notes: The minimum creepage between D1 and D2 for this 100 V device is 0.2 mm. Please see PowerPAK 1212-8 outline drawing, document # 71656, for more information. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73117. Document Number: 73117 S-83052-Rev. C, 29-Dec-08 www.vishay.com 5 Package Information Vishay Siliconix PowerPAK® 1212-8, (SINGLE/DUAL) W θ 1 8 M D4 H E2 E4 K L 1 Z D1 D2 2 D5 3 4 D 2 4 5 L1 θ θ θ e E3 A1 Backside View of Single Pad H H D2 D3(2x) D4 E2 E4 K L c 2 E1 E Notes: 1. Inch will govern 2 Dimensions exclusive of mold gate burrs Detail Z A 1 D1 2 D5 K1 3 4 b D2 3. Dimensions exclusive of mold flash and cutting burrs E3 Backside View of Dual Pad MILLIMETERS DIM. A A1 b c D D1 D2 D3 D4 D5 E E1 E2 E3 E4 e K K1 H L L1 θ W M ECN: S10-0951-Rev. J, 03-May-10 DWG: 5882 0.35 0.30 0.30 0.06 0° 0.15 3.20 2.95 1.47 1.75 MIN. 0.97 0.00 0.23 0.23 3.20 2.95 1.98 0.48 NOM. 1.04 0.30 0.28 3.30 3.05 2.11 0.47 TYP. 2.3 TYP. 3.30 3.05 1.60 1.85 0.34 TYP. 0.65 BSC 0.86 TYP. 0.41 0.43 0.13 0.25 0.125 TYP. 0.51 0.56 0.20 12° 0.36 0.014 0.012 0.012 0.002 0° 0.006 3.40 3.15 1.73 1.98 0.126 0.116 0.058 0.069 MAX. 1.12 0.05 0.41 0.33 3.40 3.15 2.24 0.89 MIN. 0.038 0.000 0.009 0.009 0.126 0.116 0.078 0.019 INCHES NOM. 0.041 0.012 0.011 0.130 0.120 0.083 0.0185 TYP. 0.090 TYP. 0.130 0.120 0.063 0.073 0.013 TYP. 0.026 BSC 0.034 TYP. 0.016 0.017 0.005 0.010 0.005 TYP. 0.020 0.022 0.008 12° 0.014 0.134 0.124 0.068 0.078 MAX. 0.044 0.002 0.016 0.013 0.134 0.124 0.088 0.035 Document Number: 71656 Revison: 03-May-10 www.vishay.com 1 b AN822 Vishay Siliconix PowerPAK® 1212 Mounting and Thermal Considerations Johnson Zhao MOSFETs for switching applications are now available with die on resistances around 1 mΩ and with the capability to handle 85 A. While these die capabilities represent a major advance over what was available just a few years ago, it is important for power MOSFET packaging technology to keep pace. It should be obvious that degradation of a high performance die by the package is undesirable. PowerPAK is a new package technology that addresses these issues. The PowerPAK 1212-8 provides ultra-low thermal impedance in a small package that is ideal for space-constrained applications. In this application note, the PowerPAK 1212-8’s construction is described. Following this, mounting information is presented. Finally, thermal and electrical performance is discussed. THE PowerPAK PACKAGE The PowerPAK 1212-8 package (Figure 1) is a derivative of PowerPAK SO-8. It utilizes the same packaging technology, maximizing the die area. The bottom of the die attach pad is exposed to provide a direct, low resistance thermal path to the substrate the device is mounted on. The PowerPAK 1212-8 thus translates the benefits of the PowerPAK SO-8 into a smaller package, with the same level of thermal performance. (Please refer to application note “PowerPAK SO-8 Mounting and Thermal Considerations.”) The PowerPAK 1212-8 has a footprint area comparable to TSOP-6. It is over 40 % smaller than standard TSSOP-8. Its die capacity is more than twice the size of the standard TSOP-6’s. It has thermal performance an order of magnitude better than the SO-8, and 20 times better than TSSOP-8. Its thermal performance is better than all current SMT packages in the market. It will take the advantage of any PC board heat sink capability. Bringing the junction temperature down also increases the die efficiency by around 20 % compared with TSSOP-8. For applications where bigger packages are typically required solely for thermal consideration, the PowerPAK 1212-8 is a good option. Both the single and dual PowerPAK 1212-8 utilize the same pin-outs as the single and dual PowerPAK SO-8. The low 1.05 mm PowerPAK height profile makes both versions an excellent choice for applications with space constraints. PowerPAK 1212 SINGLE MOUNTING To take the advantage of the single PowerPAK 1212-8’s thermal performance see Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 single in the index of this document. In this figure, the drain land pattern is given to make full contact to the drain pad on the PowerPAK package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. Figure 1. PowerPAK 1212 Devices Document Number 71681 03-Mar-06 www.vishay.com 1 AN822 Vishay Siliconix PowerPAK 1212 DUAL To take the advantage of the dual PowerPAK 1212-8’s thermal performance, the minimum recommended land pattern can be found in Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs. Click on the PowerPAK 1212-8 dual in the index of this document. The gap between the two drain pads is 10 mils. This matches the spacing of the two drain pads on the PowerPAK 1212-8 dual package. This land pattern can be extended to the left, right, and top of the drawn pattern. This extension will serve to increase the heat dissipation by decreasing the thermal resistance from the foot of the PowerPAK to the PC board and therefore to the ambient. Note that increasing the drain land area beyond a certain point will yield little decrease in foot-to-board and foot-toambient thermal resistance. Under specific conditions of board configuration, copper weight, and layer stack, experiments have found that adding copper beyond an area of about 0.3 to 0.5 in2 of will yield little improvement in thermal performance. ture profile used, and the temperatures and time duration, are shown in Figures 2 and 3. For the lead (Pb)-free solder profile, see http://www.vishay.com/ doc?73257. Ramp-Up Rate Temperature at 155 ± 15 °C Temperature Above 180 °C Maximum Temperature + 6 °C /Second Maximum 120 Seconds Maximum 70 - 180 Seconds 240 + 5/- 0 °C 20 - 40 Seconds + 6 °C/Second Maximum REFLOW SOLDERING Vishay Siliconix surface-mount packages meet solder reflow reliability requirements. Devices are subjected to solder reflow as a preconditioning test and are then reliability-tested using temperature cycle, bias humidity, HAST, or pressure pot. The solder reflow tempera- Time at Maximum Temperature Ramp-Down Rate Figure 2. Solder Reflow Temperature Profile 10 s (max) 210 - 220 °C 3 ° C/s (max) 183 °C 140 - 170 °C 50 s (max) 3° C/s (max) 60 s (min) Pre-Heating Zone Reflow Zone 4 ° C/s (max) Maximum peak temperature at 240 °C is allowed. Figure 3. Solder Reflow Temperatures and Time Durations www.vishay.com 2 Document Number 71681 03-Mar-06 AN822 Vishay Siliconix TABLE 1: EQIVALENT STEADY STATE PERFORMANCE Package Configuration Thermal Resiatance RthJC(C/W) 20 SO-8 Single Dual 40 TSSOP-8 Single 52 Dual 83 TSOP-8 Single 40 Dual 90 PPAK 1212 Single 2.4 Dual 5.5 PPAK SO-8 Single 1.8 Dual 5.5 PowerPAK 1212 49.8 °C Standard SO-8 85 °C Standard TSSOP-8 149 °C TSOP-6 125 °C 2.4 °C/W PC Board at 45 °C 20 °C/W 52 °C/W 40 °C/W Figure 4. Temperature of Devices on a PC Board THERMAL PERFORMANCE Introduction A basic measure of a device’s thermal performance is the junction-to-case thermal resistance, Rθjc, or the junction to- foot thermal resistance, Rθjf. This parameter is measured for the device mounted to an infinite heat sink and is therefore a characterization of the device only, in other words, independent of the properties of the object to which the device is mounted. Table 1 shows a comparison of the PowerPAK 1212-8, PowerPAK SO-8, standard TSSOP-8 and SO-8 equivalent steady state performance. By minimizing the junction-to-foot thermal resistance, the MOSFET die temperature is very close to the temperature of the PC board. Consider four devices mounted on a PC board with a board temperature of 45 °C (Figure 4). Suppose each device is dissipating 2 W. Using the junction-to-foot thermal resistance characteristics of the PowerPAK 1212-8 and the other SMT packages, die temperatures are determined to be 49.8 °C for the PowerPAK 1212-8, 85 °C for the standard SO-8, 149 °C for standard TSSOP-8, and 125 °C for TSOP-6. This is a 4.8 °C rise above the board temperature for the PowerPAK 1212-8, and over 40 °C for other SMT packages. A 4.8 °C rise has minimal effect on rDS(ON) whereas a rise of over 40 °C will cause an increase in rDS(ON) as high as 20 %. Spreading Copper Designers add additional copper, spreading copper, to the drain pad to aid in conducting heat from a device. It is helpful to have some information about the thermal performance for a given area of spreading copper. Figure 5 and Figure 6 show the thermal resistance of a PowerPAK 1212-8 single and dual devices mounted on a 2-in. x 2-in., four-layer FR-4 PC boards. The two internal layers and the backside layer are solid copper. The internal layers were chosen as solid copper to model the large power and ground planes common in many applications. The top layer was cut back to a smaller area and at each step junction-to-ambient thermal resistance measurements were taken. The results indicate that an area above 0.2 to 0.3 square inches of spreading copper gives no additional thermal performance improvement. A subsequent experiment was run where the copper on the back-side was reduced, first to 50 % in stripes to mimic circuit traces, and then totally removed. No significant effect was observed. Document Number 71681 03-Mar-06 www.vishay.com 3 AN822 Vishay Siliconix 105 Spreading Copper (sq. in.) 95 110 85 RthJA (°C/W) RthJ A (°C/W) 100 90 80 50 % 70 50 % 0% 45 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 50 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 60 0% 100 % 130 120 Spreading Copper (sq. in.) 75 65 100 % 55 Figure 5. Spreading Copper - Si7401DN Figure 6. Spreading Copper - Junction-to-Ambient Performance CONCLUSIONS As a derivative of the PowerPAK SO-8, the PowerPAK 1212-8 uses the same packaging technology and has been shown to have the same level of thermal performance while having a footprint that is more than 40 % smaller than the standard TSSOP-8. Recommended PowerPAK 1212-8 land patterns are provided to aid in PC board layout for designs using this new package. The PowerPAK 1212-8 combines small size with attractive thermal characteristics. By minimizing the thermal rise above the board temperature, PowerPAK simplifies thermal design considerations, allows the device to run cooler, keeps rDS(ON) low, and permits the device to handle more current than a same- or larger-size MOSFET die in the standard TSSOP-8 or SO-8 packages. www.vishay.com 4 Document Number 71681 03-Mar-06 Application Note 826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR PowerPAK® 1212-8 Dual 0.152 (3.860) 0.152 (3.860) 0.039 0.039 (0.990) (0.990) 0.016 (0.405) 0.016 (0.405) 0.039 (0.990) 0.010 (0.225) 0.068 0.068 (1.725) (1.725) 0.010 (0.255) (2.235) 0.026 (0.660) 0.026 (0.660) 0.025 (0.635) 0.025 (0.635) 0.039 (0.990) 0.030 (0.760) 0.030 (0.760) Recommended Minimum PADs for PowerPAK 1212-8 Dual Dimensions in Inches/(mm) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE www.vishay.com 1 Document Number: 72598 Revision: 14-Apr-08 (2.390) 0.088 0.094 0.094 (2.390) Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 11-Mar-11 www.vishay.com 1