SI7840BDP

Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model Si7840BDP Vishay Siliconix N-Channel 30-V (D-S) Fast Switching MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0 to 10V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 73244 04-Dec-04 www.vishay.com 1 Click Here & Upgrade PDF Complete SPICE Device Model Si7840BDP Vishay Siliconix Documents Expanded Features Unlimited Pages SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data Measured Data Unit VGS(th) ID(on) a VDS = VGS, ID = 250 µA VDS ≥ 5 V, VGS = 10 V VGS = 10 V, ID = 16.5 A VGS = 4.5 V, ID = 13 A 1.8 684 0.0070 0.0084 17 0.74 0.0070 0.0084 60 0.75 V A Ω S V Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltage a a rDS(on) gfs VSD VDS = 15 V, ID = 16.5 A IS = 3.7 A, VGS = 0 V Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Qg Qgs Qgd VDS = 15 V, VGS = 4.5 V, ID = 16.5 A 13 6 3.5 14 6 3.5 nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 73244 04-Dec-04 Click Here & Upgrade PDF Complete Documents Expanded Features Unlimited Pages SPICE Device Model Si7840BDP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 73244 04-Dec-04 www.vishay.com 3