SI7858DP

SPICE Device Model Si7858DP Vishay Siliconix N-Channel 12-V (D-S) MOSFET CHARACTERISTICS • N-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71024 20-May-02 www.vishay.com 1 SPICE Device Model Si7858DP Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Conditions Simulated Data 0.91 1265 0.0019 0.0031 142 0.76 Measured Data Unit VGS(th) ID(on) a VDS = VGS, ID = 250µA VDS ≥ 5V, VGS = 4.5V VGS = 4.5V, ID = 25A VGS = 2.5V, ID =20A VDS = 6V, ID = 25A IS = 2.9A, VGS = 0V V A 0.0024 0.0031 130 0.75 Ω S V Drain-Source On-State Resistance Forward Transconductance Diode Forward Voltage a a rDS(on) gfs VSD Dynamic b Total Gate Charge Gate-Source Charge Gate-Drain Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Source-Drain Reverse Recovery Time Qg Qgs Qgd td(on) tr td(off) tf trr IF = 2.9A, di/dt = 100 A/µs VDD = 6V, RL = 6Ω ID ≅ 1A, VGEN = 4.5V, RG = 6Ω VDS = 6V, VGS = 4.5V, ID = 25A 42 6.7 9.2 41 58 66 118 39 40 6.7 9.2 40 40 140 70 50 ns nC Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 71024 20-May-02 SPICE Device Model Si7858DP Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 71024 20-May-02 www.vishay.com 3