SI8417DB

SPICE Device Model Si8417DB Vishay Siliconix P-Channel 1.8-V (G-S) MOSFET CHARACTERISTICS • P-Channel Vertical DMOS • Macro Model (Subcircuit Model) • Level 3 MOS • Apply for both Linear and Switching Application • Accurate over the −55 to 125°C Temperature Range • Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the p-channel vertical DMOS. The subcircuit model is extracted and optimized over the −55 to 125°C temperature ranges under the pulsed 0-V to 5-V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 74135 S-52282Rev. A, 31-Oct-05 www.vishay.com 1 SPICE Device Model Si8417DB Vishay Siliconix SPECIFICATIONS (TJ = 25°C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol Test Condition Simulated Data 0.80 191 0.0184 0.0211 0.0252 20 −0.78 Measured Data Unit VGS(th) ID(on) VDS = VGS, ID = −250µA VDS ≤ −5V, VGS = −4.5V VGS = −4.5V, ID = −1 A V A 0.0174 0.0214 0.0270 8.3 −0.80 S V Ω Drain-Source On-State Resistancea rDS(on) VGS = −2.5V, ID = −1 Α VGS = −1.8V, ID = −1 Α Forward Transconductancea Diode Forward Voltage a gfs VSD VDS = −4V, ID = −1 A IS = −1A, VGS = 0 V Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Ciss Coss Crss Qg Qgs Qgd VDS = −6 V, VGS = −5 V, ID = −1 A VDS = −6 V, VGS = −4.5 V, ID = −1 A VDS = −6 V, VGS = 0 V, f = 1 MHz 3228 913 542 25 23 7.3 5.9 2220 865 555 38 35 7.3 5.9 nC pF Notes a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2%. b. Guaranteed by design, not subject to production testing. www.vishay.com 2 Document Number: 74135 S-52282Rev. A, 31-Oct-05 SPICE Device Model Si8417DB Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25°C UNLESS OTHERWISE NOTED) Document Number: 74135 S-52282Rev. A, 31-Oct-05 www.vishay.com 3