SI8424DB-T1-E1

Si8424DB Vishay Siliconix N-Channel 1.2-V (G-S) MOSFET PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 0.031 at VGS = 4.5 V 0.033 at VGS = 2.5 V 8 0.035 at VGS = 1.8 V 0.043 at VGS = 1.5 V 0.077 at VGS = 1.2 V ID (A)a 12.2 11.6 11.2 10.2 1.3 20 nC Qg (Typ.) FEATURES • TrenchFET® Power MOSFET • Industry First 1.2 V Rated MOSFET RoHS • Ultra Small MICRO FOOT® Chipscale COMPLIANT Packaging Reduces Footprint Area, Profile (0.62 mm) and On-Resistance Per Footprint Area APPLICATIONS • Low Threshold Load Switch for Portable Devices - Low Power Consumption - Increased Battery Life • Ultra Low Voltage Load Switch D MICRO FOOT Bump Side View 3 D D 2 Backside View 8424 XXX Device Marking: 8424 xxx = Date/Lot Traceability Code G S 4 G 1 Ordering Information: Si8424DB-T1-E1 (Lead (Pb)-free) S N-Channel MOSFET ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Drain-Source Voltage Gate-Source Voltage TC = 25 °C Continuous Drain Current (TJ = 150 °C) TC = 70 °C TA = 25 °C TA = 70 °C Pulsed Drain Current Continuous Source-Drain Diode Current TC = 25 °C TA = 25 °C TC = 25 °C Maximum Power Dissipation TC = 70 °C TA = 25 °C TA = 70 °C Operating Junction and Storage Temperature Range Package Reflow Conditions d Symbol VDS VGS Limit 8 ±5 12.2 Unit V ID 9.8 8.1b,c 6.5b,c A 20 5.2 2.3b,c 6.25 4 2.78b,c 1.78b,c - 55 to 150 260 W IDM IS PD TJ, Tstg IR/Convection °C Notes: a. Based on TC = 25 °C. b. Surface Mounted on 1" x 1" FR4 board. c. t = 10 s. d. Refer to IPC/JEDEC (J-STD-020C), no manual or hand soldering. e. In this document, any reference to the Case represents the body of the MICRO FOOT device and Foot is the bump. Document Number: 74400 S-82119-Rev. B, 08-Sep-08 www.vishay.com 1 Si8424DB Vishay Siliconix THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambient a,b Symbol RthJA Steady State RthJF Typical 35 16 Maximum 45 20 Unit °C/W Maximum Junction-to-Foot (Drain) Notes a. Surface Mounted on 1" x 1" FR4 board. b. Maximum under Steady State conditions is 72 °C/W. SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VGS(th) Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current On-State Drain Currenta VDS ΔVDS/TJ ΔVGS(th)/TJ VGS(th) IGSS IDSS ID(on) VGS = 0 V, ID = 250 µA ID = 250 µA VDS = VGS, ID = 250 µA VDS = 0 V, VGS = 5 V VDS = 8 V, VGS = 0 V VDS = 8 V, VGS = 0 V , TJ = 70 °C VDS ≤ 5 V, VGS = 4.5 V VGS = 4.5 V, ID = 1 A Drain-Source On-State Resistancea VGS = 2.5 V, ID = 1 A RDS(on) VGS = 1.8 V, ID = 1 A VGS = 1.5 V, ID = 1 A VGS = 1.2 V, ID = 1 A Forward Transconductance Dynamicb Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Charge Gate-Source Charge Gate-Drain Charge Gate Resistance Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Ciss Coss Crss Qg Qgs Qgd Rg td(on) tr td(off) tf VDD = 4 V, RL = 4 Ω ID ≅ 1 A, VGEN = – 4.5 V, Rg = 1 Ω VGS = 0.1 V, f = 1 MHz VDS = 4 V, VGS = 5 V, ID = 1 A VDS = 4 V, VGS = 4.5 V, ID = 1 A VDS = 4 V, VGS = 0 V, f = 1 MHz 1950 610 350 22 20 3.5 1.8 13 8 12 110 40 12 18 165 60 ns Ω 33 30 nC pF a Symbol Test Conditions Min. 8 Typ. Max. Unit V 8.9 - 2.5 0.35 1.0 100 1 10 20 0.025 0.027 0.029 0.032 0.049 8.3 0.031 0.033 0.035 0.043 0.077 13 S Ω µA A mV/°C V nA gfs VDS = 4 V, ID = 1 A www.vishay.com 2 Document Number: 74400 S-82119-Rev. B, 08-Sep-08 Si8424DB Vishay Siliconix SPECIFICATIONS TJ = 25 °C, unless otherwise noted Parameter Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulse Diode Forward Current Body Diode Voltage Body Diode Reverse Recovery Time Body Diode Reverse Recovery Charge Reverse Recovery Fall Time Reverse Recovery Rise Time IS ISM VSD trr Qrr ta tb IF = – 1 A, dI/dt = 100 A/µs, TJ = 25 °C IS = 1 A, VGS = 0 V 0.6 104 88 26 78 ns TC = 25 °C 6.25 20 1.2 156 132 A V ns nC Symbol Test Conditions Min. Typ. Max. Unit Notes: a. Pulse test; pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 20 TA = 25 °C, unless otherwise noted 20 VGS = 5 thru 1.5 V I D - Drain Current (A) I D - Drain Current (A) 15 15 10 10 TC = 125 °C 5 TC = 25 °C 5 VGS = 1 V 0 0.0 0.5 1.0 1.5 2.0 0 0.0 TC = - 55 °C 0.3 0.6 0.9 1.2 1.5 1.8 VDS - Drain-to-Source Voltage (V) VGS - Gate-to-Source Voltage (V) Output Characteristics Transfer Characteristics Document Number: 74400 S-82119-Rev. B, 08-Sep-08 www.vishay.com 3 Si8424DB Vishay Siliconix TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted 0.12 3000 RDS(on) - On-Resistance ( ) 0.09 C - Capacitance (pF) VGS = 1.2 V 2400 Ciss 1800 0.06 VGS = 1.5 V VGS = 1.8 V 1200 Coss 600 0.03 VGS = 2.5 V 0.00 0 5 VGS = 4.5 V 0 10 ID - Drain Current (A) 15 20 0 Crss 2 4 6 8 VDS - Drain-to-Source Voltage (V) RDS(on) vs. Drain Current 5 ID = 1 A 4 VDS = 4 V 3 VDS = 6.4 V RDS(on) - On-Resistance (Normalized) 1.3 1.5 ID = 1 A Capacitance VGS - Gate-to-Source Voltage (V) VGS = 4.5 V, 2.5 V, 1.8 V 1.1 VGS = 1.5 V 0.9 2 1 0 0 5 10 15 20 25 0.7 - 50 - 25 0 25 50 75 100 125 150 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge 10.00 0.050 On-Resistance vs. Junction Temperature ID = 1 A 0.045 I S - Source Current (A) TA = 150 °C RDS(on) - On-Resistance ( ) 1.00 0.040 0.035 TA = 125 °C 0.030 0.10 TA = 25 °C 0.025 TA = 25 °C 0.01 0.0 0.020 0.2 0.4 0.6 0.8 1.0 0 1 2 3 4 5 VSD - Source-to-Drain Voltage (V) VGS - Gate-to-Source Voltage (V) Forward Diode Voltage vs Temp RDS(on) vs VGS vs Temperature www.vishay.com 4 Document Number: 74400 S-82119-Rev. B, 08-Sep-08 Si8424DB Vishay Siliconix TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted 0.8 80 0.7 ID = 250 µA VGS(th) (V) Power (W) 0.6 60 0.5 40 0.4 20 0.3 0.2 - 50 0 - 25 0 25 50 75 100 125 150 0.001 0.01 0.1 Time (s) 1 10 TJ - Temperature (°C) Threshold Voltage 14 12 10 8 6 4 2 0 0 25 50 75 100 125 150 TF - Foot Temperature (°C) Power (W) 8 7 6 5 4 3 2 1 0 0 Single Pulse Power, Junction-to-Ambient ID - Drain Current (A) 25 50 75 100 125 150 Case Temperature (°C) Current Derating** 100 Limited by RDS(on)* 10 I D - Drain Current (A) P(t) = 100 ms P(t) = 1s 1 P(t) = 10s DC 0.1 Power Derating 0.01 TA = 25 °C Single Pulse 0.001 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * V GS > minimum V GS at which R DS(on) is specified Safe Operating Area, Junction-to-Ambient ** The power dissipation PD is based on TJ(max) = 150 °C, using junction-to-foot thermal resistance, and is more useful in settling the upper dissipation limit for cases where additional heatsinking is used. It is used to determine the current rating, when this rating falls below the package limit. www.vishay.com 5 Document Number: 74400 S-82119-Rev. B, 08-Sep-08 Si8424DB Vishay Siliconix TYPICAL CHARACTERISTICS TA = 25 °C, unless otherwise noted 2 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 Notes: 0.1 0.1 0.05 t1 PDM 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 1 Square Wave Pulse Duration (s) t2 1. Duty Cycle, D = 2. Per Unit Base = R thJ A = 72 °C/W 3. T JM - T A = P ZthJA(t) DM 4. Surface Mounted t1 t2 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient 2 1 Duty Cycle = 0.5 Normalized Effective Transient Thermal Impedance 0.2 0.1 0.1 0.05 0.02 Single Pulse 0.01 10-4 10-3 10-2 10-1 Square Wave Pulse Duration (s) 1 10 Normalized Thermal Transient Impedance, Junction-to-Foot www.vishay.com 6 Document Number: 74400 S-82119-Rev. B, 08-Sep-08 Si8424DB Vishay Siliconix PACKAGE OUTLINE MICRO FOOT: 4-BUMP (2 x 2, 0.8-mm PITCH) 4 x ∅ 0.30 ~ 0.31 Note 3 Solder Mask ∅ ~ 0.40 e A2 A A1 Bump Note 2 b Diameter e Recommended Land S Silicon E e 8424 XXX e D Mark on Backside of Die S Notes (Unless Otherwise Specified): 1. Laser mark on the silicon die back, coated with a thin metal. 2. Bumps are Sn/Ag/Cu. 3. Non-solder mask defined copper landing pad. 4. The flat side of wafers is oriented at the bottom. Millimetersa Min. 0.600 0.260 0.340 0.370 1.520 1.520 0.750 0.370 Max. 0.650 0.290 0.360 0.410 1.600 1.600 0.850 0.380 Min. 0.0236 0.0102 0.0134 0.0146 0.0598 0.0598 0.0295 0.0146 Dim. A A1 A2 b D E e S Inches Max. 0.0256 0.0114 0.0142 0.0161 0.0630 0.0630 0.0335 0.0150 Notes: a. Use millimeters as the primary measurement. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?74400. Document Number: 74400 S-82119-Rev. B, 08-Sep-08 www.vishay.com 7 AN824 Vishay Siliconix PCB Design and Assembly Guidelines For MICRO FOOTr Products Johnson Zhao INTRODUCTION Vishay Siliconix’s MICRO FOOT product family is based on a wafer-level chip-scale packaging (WL-CSP) technology that implements a solder bump process to eliminate the need for an outer package to encase the silicon die. MICRO FOOT products include power MOSFETs, analog switches, and power ICs. For battery powered compact devices, this new packaging technology reduces board space requirements, improves thermal performance, and mitigates the parasitic effect typical of leaded packaged products. For example, the 6−bump MICRO FOOT Si8902EDB common drain power MOSFET, which measures just 1.6 mm x 2.4 mm, achieves the same performance as TSSOP−8 devices in a footprint that is 80% smaller and with a 50% lower height profile (Figure 1). A MICRO FOOT analog switch, the 6−bump DG3000DB, offers low charge injection and 1.4 W on−resistance in a footprint measuring just 1.08 mm x 1.58 mm (Figure 2). Vishay Siliconix MICRO FOOT products can be handled with the same process techniques used for high-volume assembly of packaged surface-mount devices. With proper attention to PCB and stencil design, the device will achieve reliable performance without underfill. The advantage of the device’s small footprint and short thermal path make it an ideal option for space-constrained applications in portable devices such as battery packs, PDAs, cellular phones, and notebook computers. This application note discusses the mechanical design and reliability of MICRO FOOT, and then provides guidelines for board layout, the assembly process, and the PCB rework process. FIGURE 1. 3D View of MICRO FOOT Products Si8902DB and Si8900EDB 3 0.18 ~ 0.25 A 0.5 B 0.285 0.285 0.5 1.58 1.08 2 1 FIGURE 2. Outline of MICRO FOOT CSP & Analog Switch DG3000DB Document Number: 71990 06-Jan-03 www.vishay.com 1 AN824 Vishay Siliconix TABLE 1 MICRO FOOT’S DESIGN AND RELIABILITY As a mechanical, electrical, and thermal connection between the device and PCB, the solder bumps of MICRO FOOT products are mounted on the top active surface of the die. Table 1 shows the main parameters for solder bumps used in MICRO FOOT products. A silicon nitride passivation layer is applied to the active area as the last masking process in fabrication,ensuring that the device passes the pressure pot test. A green laser is used to mark the backside of the die without damaging it. Reliability results for MICRO FOOT products mounted on a FR-4 board without underfill are shown in Table 2. ÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁ Test Condition C: −65_ to 150_C Test condition B: −40_ to 125_C 121_C @ 15PSI 100% Humidity Test The main failure mechanism associated with wafer-level chip-scale packaging is fatigue of the solder joint. The results shown in Table 2 demonstrate that a high level of reliability can be achieved with proper board design and assembly techniques. www.vishay.com 2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁ Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á MICRO FOOT CSP Bump Material Eutectic Solder: 63Sm/37Pb 63Sm/37Pb Main Parameters of Solder Bumps in MICRO FOOT Designs Bump Pitch* 0.8 0.5 0.5 0.37-0.41 0.18-0.25 0.32-0.34 Bump Diameter* Bump Height* 0.26-0.29 0.14-0.19 0.21-0.24 MICRO FOOT CSP MOSFET MICRO FOOT CSP Analog Switch * All measurements in millimeters MICRO FOOT UCSP Analog Switch BOARD LAYOUT GUIDELINES Board materials. Vishay Siliconix MICRO FOOT products are designed to be reliable on most board types, including organic boards such as FR-4 or polyamide boards. The package qualification information is based on the test on 0.5-oz. FR-4 and polyamide boards with NSMD pad design. Land patterns. Two types of land patterns are used for surface-mount packages. Solder mask defined (SMD) pads have a solder mask opening smaller than the metal pad (Figure 3), whereas on-solder mask defined (NSMD) pads have a metal pad smaller than the solder-mask opening (Figure 4). NSMD is recommended for copper etch processes, since it provides a higher level of control compared to SMD etch processes. A small-size NSMD pad definition provides more area (both lateral and vertical) for soldering and more room for escape routing on the PCB. By contrast, SMD pad definition introduces a stress concentration point near the solder mask on the PCB side that may result in solder joint cracking under extreme fatigue conditions. Copper pads should be finished with an organic solderability preservative (OSP) coating. For electroplated nickel-immersion gold finish pads, the gold thickness must be less than 0.5 mm to avoid solder joint embrittlement. MICRO FOOT Reliability Results >500 Cycles 96 Hours >1000 Cycles TABLE 2 Solder Mask Copper Copper Solder Mask FIGURE 3. SMD FIGURE 4. NSMD Document Number: 71990 06-Jan-03 AN824 Vishay Siliconix Board pad design. The landing-pad size for MICRO FOOT products is determined by the bump pitch as shown in Table 3. The pad pattern is circular to ensure a symmetric, barrel-shaped solder bump. Chip pick-and-placement. MICRO FOOT products can be picked and placed with standard pick-and-place equipment. The recommended pick-and-place force is 150 g. Though the part will self-center during solder reflow, the maximum placement offset is 0.02 mm. Reflow Process. MICRO FOOT products can be assembled using standard SMT reflow processes. Similar to any other package, the thermal profile at specific board locations must be determined. Nitrogen purge is recommended during reflow operation. Figure 6 shows a typical reflow profile. Thermal Profile 250 Dimensions of Copper Pad and Solder Mask Opening in PCB and Stencil Aperture TABLE 3 Temperature (_C) Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁ ÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁ ÁÁ Á Á ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁ ÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁ Pitch Copper Pad Solder Mask Opening 0.41 " 0.01 mm 0.27 " 0.01 mm Stencil Aperture 0.80 mm 0.50 mm 0.30 " 0.01 mm 0.17 " 0.01 mm 0.33 " 0.01 mm in ciircle aperture 0.30 " 0.01 mm in square aperture 200 ASSEMBLY PROCESS MICRO FOOT products’ surface-mount-assembly operations include solder paste printing, component placement, and solder reflow as shown in the process flow chart (Figure 5). Stencil Design IIncoming Tape and Reel Inspection Solder Paste Printing Chip Placement Reflow Solder Joint Inspection Pack and Ship 150 100 50 0 0 100 200 Time (Seconds 300 400 FIGURE 6. Reflow Profile PCB REWORK To replace MICRO FOOT products on PCB, the rework procedure is much like the rework process for a standard BGA or CSP, as long as the rework process duplicates the original reflow profile. The key steps are as follows: 1. Remove the MICRO FOOT device using a convection nozzle to create localized heating similar to the original reflow profile. Preheat from the bottom. Once the nozzle temperature is +190_C, use tweezers to remove the part to be replaced. Resurface the pads using a temperature-controlled soldering iron. Apply gel flux to the pad. Use a vacuum needle pick-up tip to pick up the replacement part, and use a placement jig to placed it accurately. Reflow the part using the same convection nozzle, and preheat from the bottom, matching the original reflow profile. www.vishay.com FIGURE 5. SMT Assembly Process Flow Stencil design. Stencil design is the key to ensuring maximum solder paste deposition without compromising the assembly yield from solder joint defects (such as bridging and extraneous solder spheres). The stencil aperture is dependent on the copper pad size, the solder mask opening, and the quantity of solder paste. In MICRO FOOT products, the stencil is 0.125-mm (5-mils) thick. The recommended apertures are shown in Table 3 and are fabricated by laser cut. Solder-paste printing. The solder-paste printing process involves transferring solder paste through pre-defined apertures via application of pressure. In MICRO FOOT products, the solder paste used is UP78 No-clean eutectic 63 Sn/37Pb type3 or finer solder paste. Document Number: 71990 06-Jan-03 2. 3. 4. 5. 6. 3 Legal Disclaimer Notice Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. Vishay makes no warranty, representation or guarantee regarding the suitability of the products for any particular purpose or the continuing production of any product. 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