SI9112

Si9112 Vishay Siliconix High-Voltage Switchmode Controller FEATURES D 9- to 80-V Input Range D Current-Mode Control D High-Speed, Source-Sink Output Drive D High Efficiency Operation (> 80%) D Internal Start-Up Circuit D Internal Oscillator (1 MHz) D SHUTDOWN and RESET DESCRIPTION The Si9112 is a BiC/DMOS integrated circuit designed for use in high-efficiency switchmode power converters. A high-voltage DMOS input allows this controller to work over a wide range of input voltages (9- to 80-VDC). Current-mode PWM control circuitry is implemented in CMOS to reduce internal power consumption to less than 10 mW. A CMOS output driver provides high-speed switching of MOSPOWER devices large enough to supply 50 W of output power. When combined with an output MOSFET and transformer, the Si9112 can be used to implement single-ended power converter topologies (i.e., flyback, forward, and cuk). The Si9112 is available in both standard and lead (Pb)-free 14-pin plastic DIP and SOIC packages which are specified to operate over the industrial temperature range of −40 _C to 85 _C. FUNCTIONAL BLOCK DIAGRAM OSC IN 8 OSC OUT 7 FB 14 COMP 13 DISCHARGE 9 Error Amplifier 10 − + 4 V (2%) Ref Gen 2V − + + − 1 Current Sources To Internal Circuits 1.2 V C/L Comparator Current-Mode Comparator OSC Clock (1/2 fOSC) VREF To VCC 4 R Q S 5 OUTPUT −VIN BIAS 3 VCC VCC 6 SENSE +VIN 2 8.1 V − + 8.7 V − + Undervoltage Comparator Q S R 11 12 SHUTDOWN RESET Pre-Regulator/Start-Up Applications information, see AN703. sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 www.vishay.com 1 Si9112 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to −VIN (VCC < +VIN + 0.3 V) VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 V Logic Inputs (RESET, SHUTDOWN, OSC IN) . . . . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V Linear Inputs (FEEDBACK, SENSE) . . . . . . . . . . . . . . −0.3 V to VCC + 0.3 V HV Pre-Regulator Input Current (continuous) . . . . . . . . . . . . . . . . . . . . 25 mA (Power Dissipation Limited) Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 150_C Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −40 to 85_C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 14-Pin Plastic DIP (J Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750 mW 14-Pin SOIC (Y Suffix)c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 14-Pin Plastic DIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167_C/W 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 6 mW/_C above 25_C. c. Derate 7.2 mW/_C above 25_C. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. RECOMMENDED OPERATING RANGE Voltages Referenced to −VIN VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 13.5 V +VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 V to 80 V fOSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 kHz to 1 MHz ROSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 kW to 1 MW Linear Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC − 3 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE DISCHARGE = −VIN = 0 V VCC = 9 V, +VIN = 12 V RBIAS = 270 kW , ROSC = 330 kW OSC IN = − VIN (OSC Disabled) RL = 10 MW VREF = −VIN Limits D Suffix −40 to 85_C Parameter Reference Output Voltage Output Impedancee Short Circuit Current Temperature Stabilitye Symbol Tempb Room Fulle Room Room Full Mind 3.88 3.82 15 70 Typc 4.0 30 100 0.5 Maxe 4.12 4.14 45 130 1.0 Unit VR ZOUT ISREF TREF V kW mA mV/_C Oscillator Maximum Frequencye Initial Accuracy Voltage Stability Temperature Coefficiente fMAX fOSC Df/f TOSC ROSC = 0 ROSC = 330 k, See Note f ROSC = 150 k, See Note f Df/f = f(13.5 V) − f(9.5 V) / f(9.5 V) Room Room Room Room Full 1 80 160 3 100 200 9 200 120 240 15 500 MHz kHz % ppm/_C Error Amplifier Feedback Input Voltage Input Offset Voltage Input BIAS Current Open Loop Voltage Gaine Unity Gain Bandwidthe Dynamic Output Impedancee Output Current Power Supply Rejectione www.vishay.com VFB VOS IFB AVOL BW ZOUT IOUT PSRR FB Tied to COMP OSC IN = − VIN (OSC Disabled) OSC IN = − VIN (OSC Disabled) OSC IN = − VIN, VFB = 4 V OSC IN = − VIN OSC IN = − VIN (OSC Disabled) Error Amp Configured for 60 dB gain Source VFB = 3.4 V Sink VFB = 4.5 V 9 V v VCC v 13.5 V Room Room Room Room Room Room Room Room Room 0.12 50 60 1 3.92 4.00 "15 25 80 1.5 1000 −2.0 0.15 70 2000 −1.4 4.08 "40 500 V mV nA dB MHz W mA dB sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 2 Si9112 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified DISCHARGE = −VIN = 0 V VCC = 9 V, +VIN = 12 V RBIAS = 270 kW , ROSC = 330 kW VFB = 0 V VSENSE = 1.5 V, See Figure 1 Limits D Suffix −40 to 85_C Parameter Current Limit Threshold Voltage Delay to Outpute Symbol VSOURCE td Tempb Room Room Mind 1.1 Typc 1.3 100 Maxe 1.5 150 Unit V ns Pre-Regulator/Start-Up Input Voltage Input Leakage Current Pre-Regulator Start-Up Current Pre-Regulator Dropout Voltage VCC Pre-Regulator Turn-Off Threshold Voltage Undervoltage Lockout VREG −VUVLO +VIN +IIN ISTART VCC VREG VUVLO VDELTA IIN = 10 mA VCC w 9.4 V +VIN = 48 V +VIN = 10 V, RLOAD = 4 k at Pin 6 IPRE-REGULATOR = 10 mA See Detailed Description Room Room Room Room Room Room Room 12 VUVLO +0.1 8.0 7.2 0.3 8.7 8.1 0.6 9.4 8.9 V 20 80 10 V mA mA Supply Supply Current Bias Current ICC IBIAS CL v 75 pF (Pin 4) Room Room 0.6 15 1.0 mA mA Logic SHUTDOWN Delaye SHUTDOWN Pulse Widthe tSD tSW tRW tLW VIL VIH IIH IIL VLOGIC = VCC VIN = 0 V See Figure 3 Figure CL = 500 pF VSENSE = −VIN, See Figure 2 Room Room Room Room Room Room Room Room −35 7.0 1 25 5 mA 50 50 25 2.0 V 50 100 ns RESET Pulse Widthe Latching Pulse Width SHUTDOWN and RESET Lowe Input Low Voltage Input High Voltage Input Current Input Voltage High Input Current Input Voltage Low Output Output High Voltage Output Low Voltage Output Resistancee Rise Timee Fall Timee VOH VOL ROUT tr tf IOUT = −10 mA IOUT = 10 mA IOUT = 10 mA, Source or Sink CL = 500 pF pF Room Full Room Full Room Full Room Room 20 25 40 40 8.7 8.5 0.3 0.5 30 50 75 75 V W ns Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. Room = 25_C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum. e. Guaranteed by design, not subject to production test. f. CSTRAY Pin 8 = v 5 pF. sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 www.vishay.com 3 Si9112 Vishay Siliconix TIMING WAVEFORMS SENSE 0 VCC OUTPUT 0− 1.5 V − 50% td tr v 10 ns VCC SHUTDOWN 0 VCC OUTPUT 0 50% − tSD tf v 10 ns 90% 90% − FIGURE 1. FIGURE 2. VCC SHUTDOWN 0 VCC RESET 0 50% − 50% − tSW 50% tLW 50% tRW 50% tf, tf v 10 ns FIGURE 3. TYPICAL CHARACTERISTICS +VIN vs. +IIN at Start-Up 140 VCC = −VIN 120 100 +V IN (V) 80 60 40 20 0 10 15 +IIN (mA) 20 10 k 10 k f OUT (Hz) 1M Output Switching Frequency vs. Oscillator Resistance 100 k 100 k rOSC − Oscillator Resistance (W) 1M FIGURE 4. FIGURE 5. www.vishay.com 4 sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 Si9112 Vishay Siliconix PIN CONFIGURATIONS AND ORDERING INFORMATION Dual-In-Line and SOIC BIAS +VIN SENSE OUTPUT −VIN VCC OSC OUT 1 2 3 4 5 6 7 Top View 14 FB 13 COMP 12 RESET 11 SHUTDOWN 10 VREF 9 8 DISCHARGE OSC IN ORDERING INFORMATION Part Number Si9112DY Si9112DY-T1 Si9112DY-T1—E3 Si9112DJ Si9112DJ—E3 −40 to 85_C PDIP-14 PDIP-14 SOIC-14 Temperature Range Package DETAILED DESCRIPTION Pre-Regulator/Start-Up Section Due to the low quiescent current requirement of the Si9112 control circuitry, bias power can be supplied from the unregulated input power source, from an external regulated low-voltage supply, or from an auxiliary “bootstrap” winding on the output inductor or transformer. When power is first applied during start-up, +VIN (pin 2) will draw a constant current. The magnitude of this current is determined by a high-voltage depletion MOSFET device which is connected between +VIN and VCC (pin 6). This start-up circuitry provides initial power to the IC by charging an external bypass capacitance connected to the VCC pin. The charging current is disabled when VCC exceeds 8.7 V. If VCC is not forced to exceed the 8.7-V threshold, then VCC will be regulated to a nominal value of 8.7 V by the pre-regulator circuit. As the supply voltage rises toward the normal operating conditions, an internal undervoltage (UV) lockout circuit keeps the output driver disabled until VCC exceeds the UV lockout threshold (typically 8.1 V). This guarantees that the control logic will be functioning properly and that sufficient gate drive voltage is available before the MOSFET turns on. The design of the IC is such that the undervoltage lockout threshold will be at least 300 mV less than the pre-regulator turn-off voltage. Power dissipation can be minimized by providing an external power source to VCC such that the pre-regulator circuit is disabled. BIAS To properly set the bias for the Si9112, a 270-k W resistor should be tied from BIAS (pin 1) to −VIN (pin 5). This sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 determines the magnitude of bias current in all of the analog sections and the pull-up current for the SHUTDOWN and RESET pins. The current flowing in the bias resistor is nominally 15 mA. Reference Section The reference section of the Si9112 consists of a temperature compensated buried zener and trimmable divider network. The output of the reference section is connected internally to the non-inverting input of the error amplifier. Nominal reference output voltage is 4 V. The trimming procedure that is used on the Si9112 brings the output of the error amplifier (which is configured for unity gain during trimming) to within "2% of 4 V. This automatically compensates for input offset voltage in the error amplifier. The output impedance of the reference section has been purposely made high so that a low impedance external voltage source can be used to override the internal voltage source, if desired, without otherwise altering the performance of the device. Error Amplifier Closed-loop regulation is provided by the error amplifier. The emitter follower output has a typical dynamic output impedance of 1000 W , and is intended for use with “around-the-amplifier” compensation. A MOS differential input stage provides low input leakage current. The noninverting input to the error amplifier (VREF) is internally connected to the output of the reference supply and should be bypassed with a small capacitor to ground. www.vishay.com 5 Si9112 Vishay Siliconix DETAILED DESCRIPTION (CONT’D) Oscillator Section The oscillator consists of a ring of CMOS inverters, capacitors, and a capacitor discharge switch. Frequency is set by an external resistor between the OSC IN and OSC OUT pins. (See Typical Characteristics for details of resistor value vs. frequency.) The DISCHARGE pin should be tied to −VIN for normal internal oscillator operation. A frequency divider in the logic section limits switch duty cycle to v50% by locking the switching frequency to one half of the oscillator frequency. Remote synchronization can be accomplished by capacitive coupling of a SYNC pulse into the OSC IN (pin 8) terminal. For a 5-V pulse amplitude and 0.5-ms pulse width, typical values would be 100 pF in series with 3 k W to pin 8. SHUTDOWN and RESET SHUTDOWN (pin 11) and RESET (pin 12) are intended for overriding the output MOSFET switch via external control logic. The two inputs are fed through a latch preceding the output switch. Depending on the logic state of RESET, SHUTDOWN can be either a latched or unlatched input. The output is off whenever SHUTDOWN is low. By simultaneously having SHUTDOWN and RESET low, the latch is set and SHUTDOWN has no effect until RESET goes high. The truth table for these inputs is given in Table 1. Table 1: Truth Table for the SHUTDOWN and RESET Pins SHUTDOWN H H L L H L L RESET H Output Normal Operation Normal Operation (No Change) Off (Not Latched) Off (Latched) Off (Latched, No Change) Both pins have internal current source pull-ups and should be left disconnected when not in use. An added feature of the current sources is the ability to connect a capacitor and an open-collector driver to the SHUTDOWN or RESET pins to provide variable shutdown time. Output Driver The push-pull driver output has a typical on-resistance of 20 W. Maximum switching times are specified at 75 ns for a 500 pF load. This is sufficient to directly drive 60-V, 25-A MOSFETs. Larger devices can be driven, but switching times will be longer, resulting in higher switching losses. For applications information refer to AN703. Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70005. www.vishay.com sDocument Number: 70005 S-42036—Rev. H, 15-Nov-04 6