SI9122

Si9122 Vishay Siliconix 500-kHz Half-Bridge DC-DC Converter With Integrated Secondary Synchronous Rectification Drivers FEATURES D 12-V to 72-V Input Voltage Range D Compatible with ETSI 300 132-2 D Integrated Half Bridge Primary Drivers (1-A Drive Capability) D Secondary Synchronous Signals With Programmable Deadtime Delay D Voltage Mode Control D Voltage Feedforward Compensation D High Voltage Pre-Regulator Operates During Start-Up D Current Sensing On Low-Side Primary Device D Frequency Foldback Eliminates Constant Current Tail D Advanced Maximum Current Control During Start-Up and Shorted Load D Low Input Voltage Detection D Programmable Soft-Start Function D Over Temperature Protection APPLICATIONS D Network Cards D Power Supply Modules DESCRIPTION Si9122 is a dedicated half-bridge IC ideally suited to fixed telecom applications where efficiency is required at low output voltages (e.g. 680 pF CSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 nF CREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF CBOOST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.1 mF CLOAD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150 mF Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC − 2 V Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to VCC Reference Voltage Output Current . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 2.5 mA SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Reference (3.3 V) Output Voltage Short Circuit Current Load Regulation Power Supply Rejection VREF ISREF dVr/dlr PSRR VCC = 12 V, 25_C Load = 0 mA VREF = 0 V IREF = 0 to −2.5 mA @ 100Hz −30 60 3.2 3.3 3.4 −50 −75 V mA mV dB Limits −40 to 85_C Symbol fNOM = 500 kHz, VIN = 72 V 500 kH 72 VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb Typc Maxb Unit Oscillator Accuracy (1% ROSC) Max Frequency Foldback Frequencyd FMAX FFOBK ROSC = 30 kW, fNOM = 500 kHz ROSC = 24 kW fNOM = 500 kHz, VCS2 − VCS1 u 150 mV −20 600 100 20 % kHz Error Amplifier Input Bias Current Gain Bandwidth Power Supply Rejection Slew Rate IBIAS AV BW PSRR SR @ 100Hz VEP = 0 V −40 −2.2 5 60 0.5 −15 mA V/V MHz dB V/ms Current Sense Amplifier Input Voltage CM Range Input Amplifier Gain Input Amplifier Bandwidth Document Number: 71815 S-41944—Rev. F, 18-Oct-04 VCM AVOL BW VCS1 − GND, VCS2 − GND "150 17.5 5 mV dB MHz www.vishay.com 3 Si9122 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Current Sense Amplifier Input amplifier Offset Voltage CL_CONT CL_CONT Current Lower Current Limit Threshold Upper Current Limit Threshold Hysteresis CL_CONT Clamp Level CL_CONT(min) VOS dVCS = 0 ICL_CONT CL_CONT VTLCL VTHCL dVCS = 100 mV dVCS = 170 mV IPD = IPU − ICL_CONT = 0 See Figure 6 IPD u 2 mA IPU t 500 mA IPU = 500 mA 0.6 "5 120 0 u2 100 150 −50 1.5 V mV V mV mA mA Limits −40 to 85_C Symbol fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb Typc Maxb Unit PWM Operation DMAX Duty Cyclee yy DMIN fOSC = 500 kHz kHz VEP= 0 V VEP= 1.75 V 90 92 t15 3 95 % VCS2 − VCS1 u 150 mV Pre-Regulator Input Voltage Input Leakage Current Regulator Bias Current Regulator_Comp Regulator Comp Pre-Regulator Drive Capacility VCC Pre-Regulator T R l t Turn Off Threshold Voltage Threshold Voltage Undervoltage Lockout VUVLO Hysteresisg +VIN ILKG IREG1 IREG2 ISOURCE ISINK ISTART VREG1 VREG2 VUVLO VUVLOHYS IIN = 10 mA VIN = 72 V, VCC u VREG VIN = 72 V, VINDET t VSD VIN = 72 V, VINDET u VREF VCC = 12 V VCC t VREG VINDET u VREF VINDET = 0 V VCC Rising 7.15 TA = 25_C 8.1 TA = 25_C −29 50 20 7.4 8.5 9.1 9.1 9.2 8.8 8.8 0.5 9.8 9.3 10.4 9.7 V 86 8 −19 82 72 10 200 14 −9 110 V mA mA mA mA Soft-Start Soft-Start Current Output Soft-Start Completion Voltage ISS VSS_COMP Start-Up Condition Normal Operation 12 7.35 20 8.05 28 8.85 mA V Shutdown VINDET Shutdown FN VINDET Hysteresis VSD VINDET Rising VINDET 350 550 200 720 mV mV VINDET Input Threshold Voltages VINDET − VIN Under Voltage VINDET Hysteresis VUV VINDET Rising VINDET 3.13 3.3 0.3 3.46 V Over Temperature Protection Activating Temperature De-Activating Temperature TJ Increasing TJ Decreasing 160 130 _C Converter Supply Current (VCC) Shutdown Switching Disabled Switching w/o Load Switching with CLOAD ICC1 ICC2 ICC3 ICC4 Shutdown, VINDET = 0 V VINDET t VREF VINDET u VREF, fNOM = 500 kHz VCC = 12 V, CDH = CDL = 3 nF CSRH = CSRL = 0.3 nF 50 4 5 8 10 21 350 12 14 mA mA mA www.vishay.com 4 Document Number: 71815 S-41944—Rev. F, 18-Oct-04 Si9122 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Output High Voltage Output Low Voltage Boost Current LX Current Peak Output Source Peak Output Sink Rise Time Fall Time Limits −40 to 85_C Symbol VOH VOL IBST ILX ISOURCE ISINK tr tf fNOM = 500 kHz, VIN = 72 V VINDET = 7.2 V; 10 V v VCC v 13.2 V Minb VBST − 0.3 Typc Maxb Unit Output MOSFET DH Driver (High-Side) Sourcing 10 mA Sinking 10 mA VLX = 72 V, VBST = VLX + VCC VLX = 72 V, VBST = VLX + VCC VCC = 10 V CDH = 3 nF 1.3 −1.1 0.75 1.9 −0.7 −1.0 1.0 35 35 VLX + 0.3 2.7 −0.4 −0.75 V mA A ns Output MOSFET DLDriver (Low-Side) Output High Voltage Output Low Voltage Peak Output Source Peak Output Sink Rise Time Fall Time VOH VOL ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA VCC = 10 V CDL = 3 nF −1.0 0.75 1.0 35 35 VCC − 0.3 0.3 −0.75 V A ns Synchronous Rectifier (SRH, SRL) Drivers Output High Voltage Output Low Voltage VOH VOL tBBM1 Break-Before-Make Break Before Make Timef tBBM2 tBBM3 tBBM4 Peak Output Source Peak Output Sink Rise Time Fall Time ISOURCE ISINK tr tf Sourcing 10 mA Sinking 10 mA TA = 25_C RBBM = 33 kW, See Figure 3 C, See TA = 25_C RBBM = 33 kW, LX = 72 V C,R VCC = 10 V CSRH = CSRL = 0.3 nF 3 55 40 35 55 −100 100 35 35 mA ns ns VCC − 0.4 0.4 V Voltage Mode Error Amplifier Error Amplifier td1DH td2DL Input to high-side switch off Input to low-side switch off t200 t200 ns Current Mode Current Amplifier Current Amplifier td3DH td4DL Input to high-side switch off Input to low-side switch off t200 t200 ns Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum (−40_ to 85_C). c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. FMIN when VCL_CONT at clamp level. Typical foldback frequency change +20%, −30% over temperature. e. Measured on SRL or SRH outputs. f. See Figure 3 for Break-Before-Make time definition. g. VUVLO tracks VREG1 by a diode drop h. CBBM may be required to reduce noise into BBM pin for non-optimum layout. Document Number: 71815 S-41944—Rev. F, 18-Oct-04 www.vishay.com 5 Si9122 Vishay Siliconix TIMING DIAGRAM FOR MOS DRIVERS VCC GND VCC DL GND VCC SRL SRL DL PWM PWM PWM PWM GND VBST VMID DH DH DH GND DH VCC GND SRH SRH Time DH 50% V LX LX tBBM1 tBBM2 tBBM3 tBBM4 BST = LX + VCC DH, LX DH, LX VMID SRH DH, LX 50% VCC GND SRL DL tBBM3 SRL tBBM4 VCC GND Return to: Specification Table Rectification Timing Sequence Primary MOSFET Drivers Secondary MOSFET Drivers tBBM1 tBBM2 Figure 3. www.vishay.com 6 Document Number: 71815 S-41944—Rev. F, 18-Oct-04 Si9122 Vishay Siliconix PIN CONFIGURATION Si9122DQ (TSSOP-20) VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 1 2 3 4 5 6 7 8 9 10 Top View Top View 20 19 18 17 16 15 14 13 12 11 BST DH LX DL PGND SRH SRL SS BBM CL_CONT VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 Si9122DLP (MLP65-20) BST DH LX DL PGND SRH SRL SS BBM CL_CONT ORDERING INFORMATION Standard Part Number Si9122DQ-T1 Lead (Pb)-Free Part Number Si9122DQ-T1—E3 Si9122DLP-T1—E3 Temperature Range −40 to 85_C Package TSSOP-20 MLP65-20 Eval Kit Si9122DB Issue 3 Temperature Range −10 to 70_C Board Type Surface Mount and Thru-Hole PIN DESCRIPTION Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Document Number: 71815 S-41944—Rev. F, 18-Oct-04 Name VIN REG_COMP VCC VREF GND ROSC EP VINDET CS1 CS2 CL_CONT BBM SS SRL SRH PGND DL LX DH BST Input supply voltage for the start-up circuit. Control signal for an external pass transistor. Supply voltage for internal circuitry 3.3-V reference, decoupled with 1-mF capacitor Ground External resistor connection to oscillator Voltage control input Function VIN under voltage detect and shutdown function input. Shuts down or disables switching when VINDET falls below preset threshold voltages and provides the feed forward voltage. Current limit amplifier negative input Current limit amplifier positive input Current limit compensation Programmable Break-Before-Make time connection to an external resistor to set time delay Soft-Start control − external capacitor connection Signal transformer drive, sequenced with the primary side. Signal transformer drive, sequenced with the primary side. Power ground. Low-side gate drive signal – primary High-side source and transformer connection node High-side gate drive signal – primary Bootstrap voltage to drive the high-side n-channel MOSFET switch www.vishay.com 7 Si9122 Vishay Siliconix VCC VIN Pre-Regulator Bandgap Reference 3.3 V + − VINDET CL_CONT VREF + − VSD 160_C Temp Protection VSD Clock Clock 132 kW 60 kW EP − + VREF/2 − + PWM Generator Timer VCC Logic PGND Logic VUV VUVLO OTP VCC Low-Side Driver DL High Voltage Interface VREG 9.1 V VREF + − VUVLO 9.1 V VUV + − 8.6 V High-Side Primary Driver BST DH LX Voltage Feedforward Frequency Foldback 550 mV ROSC Oscillator OSC CS2 CS1 Current Control + − 100 mV Gain Loop Control Blanking Synchronous Driver (High) SRH VCC CL_CONT VCC 8V 20 mA GND BBM Synchronous Driver (Low) SRL Si9122 Soft-Start SS Enable SS Figure 4. Detailed Functional Block DETAILED OPERATION Start-Up When VINEXT rises above 0 V, the internal pre-regulator begins to charge up the Vcc capacitor. Current into the external VCC capacitor is limited to typically 40 mA by the internal DMOS device. When Vcc exceeds the UVLO voltage of 8.8 V a soft-start cycle of the switch mode supply is initiated. The VCC supply continues to be charged by the pre-regulator until VCC equals Vreg. During this period, between VUVLO and VREG, excessive load current will result in VCC falling below VUVLO and stopping switch mode operation. This situation is avoided by the hysteresis between VREG and VUVLO and correct sizing www.vishay.com of the VCC capacitor, bootstrap capacitor and the soft-start capacitor. The value of the VCC capacitor should therefore be chosen to be capable of maintaining switch mode operation until the VCC can be supplied from the external circuit (e.g via a power transformer winding and zener regulator). Feedback from the output of the switch mode supply charges VCC above VREG and fully disconnects the pre-regulator, isolating VCC from VIN. VCC is then maintained above VREG for the duration of switch mode operation. In the event of an over voltage condition on VCC, an internal voltage clamp turns on at 14.5 V to shunt excessive current to GND. Document Number: 71815 S-41944—Rev. F, 18-Oct-04 8 Si9122 Vishay Siliconix Care needs to be taken if there is a delay prior to the external circuit feeding back to the VCC supply. To prevent excessive power dissipation within the IC it is advisable to use an external PNP device. A pin has been incorporated on the IC, (REG_COMP) to provide compensation when employing the external device. In this case the VIN pin is connected to the base of the PNP device and controls the current, while the REG_COMP pin determines the frequency compensation of the circuit. To understand the operation please refer to Figure 5. The soft-start circuit is designed for the dc-dc converter to start-up in an orderly manner and reduce component stress on the IC. This feature is programmable by selecting an external CSS. An internal 20-mA current source charges CSS from 0 V to the final clamped voltage of 8 V. In the event of UVLO or shutdown, VSS will be held low (