SI9150DY-T1

Si9150 Vishay Siliconix Synchronous Buck Converter Controller FEATURES D 6- to 16.5-V Input Range (Si9150CY) D Voltage-Mode PWM Control D Low-Current Standby Mode D Enable Control D Dual 100-mA Output Drivers D 2% Band Gap Reference D Multiple Converters Easily Synchronized D Over-Current Protection DESCRIPTION The Si9150 synchronous buck regulator controller is ideally suited for high-efficiency step down converters in battery-powered equipment. Combined with the Si9943DY MOSFET half-bridge, a 90% efficient, 7.5-W, 3.3-V or 5-V power supply can be implemented using standard surfacemount assembly techniques. The wide input range allows operation from NiCd or NiMH battery packs using six to ten cells. Over-current protection is achieved by sensing the on-state voltage drop across the high side p-channel MOSFET, which eliminates the need for a current sense resistor. Duty ratios of 0 to 100% and switching frequencies up to 300 kHz are possible. The IC can be disabled by pulling EN low (IDD = 100 mA), or the 2.5-V reference can be maintained, with all other functions disabled, by pulling STBY low (IDD = 500 mA). The Si9150 is available in both standard and lead (Pb)-free 14-pin SOIC and rated for the commercial temperature range of 0 to 70_C (C suffix), and the industrial temperature range of −40 to +85_C (D suffix). FUNCTIONAL BLOCK DIAGRAM VDD 14 500 kW EN 1 Power Down UVLO 20 mA 0.5 V 13 P-GATE Q R S Oscillator, Comparators, & Error Amp Reference Generator Current Limit + − Strobe 7 2 STBY 4.7 V ISENSE SS 3 Ref Gen Error Amplifier + − 5 FB 4 COMP 1V − + R OSC S Q BreakBeforeMake Logic VDD 12 N-GATE 5W 6 VREF CT 9 RT 10 8 SYNC 11 GND Synchronous Buck Regulator Controller Document Number: 70020 S-40752—Rev. F, 19-Apr-04 www.vishay.com 1 Si9150 Vishay Siliconix ABSOLUTE MAXIMUM RATINGS Voltages Referenced to GND. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 V ISENSE Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −2 V to VDD +2 V All Other Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.3 to VDD + 0.3 V P-Gate, N-Gate Continuous Source/Sink Current . . . . . . . . . . . . . . . . 50 mA Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −65 to 125_C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150_C Power Dissipation (Package)a 14-Pin SOIC (Y Suffix)b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 900 mW Thermal Impedance (QJA) 14-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140_C/W Notes a. Device mounted with all leads soldered or welded to PC board. b. Derate 7.2 mW/_C. SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Reference Output Voltage VREF TA = 25_C Measured at Feedbacke Pin 5 TMIN to TMAXd 2.45 2.425 2.50 2.500 2.55 2.575 2.45 2.40 2.50 2.500 2.55 2.60 V Limits C Suffix 0 to 70_C Limits D Suffix −40 to 85_C Symbol 6.0 v VDD v 16.5 V Minb Typc Maxb Minb Typc Maxb Unit Oscillator Maximum Frequency Initial Accuracy Oscillator Ramp Amplitude Temperature Stabilityd fMAX fOSC VOSC fTEMP COSC =94.3 pF, ROSC = 28.7 kW TA = 25_Cf COSC =212 pF, ROSC = 41.2 kW TA = 25_Cf TA = 25_C, 100 kHz VDD = 10 V, TMIN to TMAX 255 85 2.05 −5 300 100 2.65 "3 345 115 2.85 +5 255 85 2.05 −6 300 100 2.65 "4 345 kHz kHz 115 2.85 +6 V % Error Amplifier Input BIAS Current Open Loop Voltage Gaind Offset Voltage Unity Gain Bandwidthd Output Current Power Supply Rejection IB AVOL VOS BW IOUT PSRR Source, VCOMP = 2.50 V Sink, VCOMP = 1.0 V 1 50 1 VFB = VREF 60 25 72 10 1.5 −0.30 2.5 70 −0.20 0.9 48 25 1 500 58 25 72 10 1.5 −0.30 2.5 70 −0.15 30 750 nA dB mV MHz mA dB Protection Current Limit Threshold Voltage Current Limit Delay to Outputd Undervoltage Lockout Voltage Undervoltage Hysteresis Softstart Pull-Up Current VCL td VUVLO VHYS ISS TA = 25_C, VDD = 10 V TA = 25_C Upper Threshold 5.4 0.10 0.43 0.49 500 5.7 0.17 20 0.55 1000 6.0 0.25 5.38 0.10 0.43 0.49 500 5.7 0.17 20 0.55 1000 6.01 0.26 mA V ns V Supply Supply Current (Enable Low) Supply Current (Enable High) Supply Current (STBY Low) IOFF ICC ISB CL = 0 pF, fOSC = 100 kHz VDD = 10 V 60 2.2 300 100 3.0 500 60 2.2 300 100 3.0 550 mA mA mA www.vishay.com 2 Document Number: 70020 S-40752—Rev. F, 19-Apr-04 Si9150 Vishay Siliconix SPECIFICATIONSa Test Conditions Unless Otherwise Specified Parameter Output Output High Voltage Output Low Voltage Output Resistance Rise Timed Fall Timed VOH VOL ROUT tr tf IOUT = 10 mA, VDD = 10 V IOUT = −10 mA, VDD = 10 V IOUT = 100 mA, VDD = 10 V CL = 800 pF, VDD = 10 V pF 10 30 30 9.75 0.25 20 60 60 10 30 30 9.7 0.3 25 70 70 V W ns Limits C Suffix 0 to 70_C Limits D Suffix −40 to 85_C Symbol 6.0 v VDD v 16.5 V Minb Typc Maxb Minb Typc Maxb Unit Logic Delay to Output Enable Pull-Up Resistance STBY Pull-Up Current Turn-On Threshold Turn-Off Threshold td(EN) REN ISTBY VENH VENL TA = 25_C, VSTBY = 0 V VDD = 10 V VDD = 10 V, Rising Input Voltage VDD = 10 V, Falling Input Voltage −25 6 2 Transition High to Low 0.25 500 −20 6.8 3.75 −15 8 5 −28 6 2 1 0.25 500 −20 6.8 3.75 −12 8 5 1 ms kW mA V Notes a. Refer to PROCESS OPTION FLOWCHART for additional information. b. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. Guaranteed by design, not subject to production test. e. The voltage reference is trimmed with the feedback (Pin 5) connected to compensation (Pin 4) so that the effect of the error amplifier’s input offset voltage is eliminated. f. COSC includes the PC board’s parasitic capacitance. TYPICAL CHARACTERISTICS (25_C UNLESS OTHERWISE NOTED) 1000 Oscillator Characteristics Frequency (kHz) 100 50 pF 100 pF 150 pF 200 pF 10 10 100 rOSC − Oscillator Resistance (kW) 1000 Document Number: 70020 S-40752—Rev. F, 19-Apr-04 www.vishay.com 3 Si9150 Vishay Siliconix PIN CONFIGURATION AND ORDERING INFORMATION SOIC EN STANDBY SS COMP FB VREF ISENSE 1 2 3 4 5 6 7 Top View 14 13 12 11 10 9 8 VDD P-GATE N-GATE GND RT CT SYNC ORDERING INFORMATION Part Number Si9150CY Si9150CY-T1 Si9150CY-T1—E3 Si9150DY Si9150DY-T1 Si9150DY-T1—E3 −40 to 85_C 0 to 70_C SOIC-14 14 Temperature Range Package PIN DESCRIPTION Pin 1: EN When this pin is low, the IC is shut down. After a low signal is applied to EN, then COMP, REF, RT, and CT settle toward ground; N-GATE, STBY and Soft-Start are grounded; and P-GATE is pulled high. The current consumption is no more than 100 mA in this state. This input’s threshold has substantial hysteresis so that a capacitor to GND can be used to delay restart after the current limit is activated. After VENH is exceeded, one clock cycle elapses before N-GATE and P-GATE are enabled. EN is pulled up to VDD through a 500-k resistor and is pulled down internally when the current limit is triggered. uses this pin. COMP settles low when either EN or STBY is pulled low. Pin 5: Feedback (FB) This pin is attached directly to the inverting input of the error amplifier. This pin is used to regulate the power supply’s output voltage. Pin 6: Reference (VREF) The internal 2.5-V reference generator is attached to this pin through a 5-W resistor. A 0.1-mF bypass capacitor is needed to suppress noise. Also note that the generator has an open emitter; it will not pull down. The maximum current that the generator will source before it current limits is about 10 mA. Many parts of the IC use this voltage, so it is important not to overload the reference generator. Pin 7: ISENSE This pin should be attached to the switched node (the drains of the application’s p-channel and n-channel MOSFETs). If the voltage between VDD and this pin is more then 0.46 V while the P-GATE is low, the current limit is activated. The current limit is relatively slow to prevent false triggering due to noise. Activating the current limit causes EN to be pulled to GND. ISENSE may be operated from VDD + 2 V to GND − 2 V. For operation above 13.5 VDD a filter (1 kW, 33 pF) is needed between the MOSFET drains and the ISENSE pin; refer to Figure 1. Pin 8: SYNC Pin 4: Compensation (COMP) This pin is tied directly to the output of the error amplifier. The feedback network which insures the stability of an application www.vishay.com Pin 2: STBY Has a function similar to EN. The differences are that the EN pin is unaffected, that the reference is still available, that bias currents are still present internally, and that this pin’s pull up current is present. This pin should be used to disable an application if the reference voltage is still needed. Pin 3: Soft-Start (SS) This pin limits the maximum voltage that the error amplifier can output. A capacitor between this pin and ground will limit the rate at which the duty factor can increase during initial power up, during a restart when EN or STBY goes high, or after the current limit is triggered. A capacitor here can prevent an application from triggering the Si9150’s current limit during startup. Soft-Start is pulled low if either EN or STBY is low. This pin forces the clock to reset when low, and is also pulled low when the clock resets itself. Thus if several Si9150’s have their sync pins shorted together, they will be synchronized; the shortest duration clock will control the other clocks. Document Number: 70020 S-40752—Rev. F, 19-Apr-04 4 Si9150 Vishay Siliconix Pin 9: CT A capacitor from this pin to ground is charged until it reaches 2.5 V, at which point the capacitor is rapidly discharged. The resulting sawtooth with about 1 V added is compared to the input voltage at COMP to determine whether P-GATE and N-GATE should be high or low. The maximum recommended value for COSC is 200 pF (See Typical Characteristics). The capacitor’s charging current is controlled by Pin 10, RT. the the path from VDD to the source of the application’s p-channel MOSFET. Pin 12: N-GATE This pin is used to drive the application’s n-channel MOSFET. When turning the n-channel MOSFET off, the p-channel MOSFET will not be turned on until N-GATE is within a few volts of ground. This pin is low while either EN or STBY is low. Pin 10: RT Pin 13: P-GATE The IC applies 2.5 V to this pin, and the current is mirrored and applied to Pin 9 while charging the capacitor. The minimum recommended value of ROSC is 20 kW (Figure 1). This pin is used to drive the application’s p-channel MOSFET. The break before make circuitry for the P-GATE is complimentary to that for the N-GATE. This pin is high while either EN or STBY is low. Pin 11: GND Since the Si9150 has a high-side current limit, it is important that VDD track the voltage on the source of the p-channel power MOSFET. For noise immunity, it is best to separate the logic ground from the power ground. The logic ground should be decoupled to VDD through at least a 1-mF capacitor. The two grounds may be connected by a path that is long compared to Pin 14: VDD This pin powers the IC. The connection between this pin and the source of the p-channel FET should be as short as practical. Read Pin 11’s description for bypassing suggestions. APPLICATIONS VIN 100 mF (20 V) Si9943 47 pF 1 220 pF 3.32 kW 0.039 mF 5600 pF 2 3 4 5 6 7 Si9150 14 13 12 11 10 9 8 56.2 kW 200 pF 33 pF 1 kW VIN 33.2 kW 10MQ060 33.2 kW 14.7 kW 1000 pF 43 mH +5 V 100 mF 1 mF FIGURE 1. Typical Application Circuit Document Number: 70020 S-40752—Rev. F, 19-Apr-04 www.vishay.com 5